4x1 Mux 171p

EXPERIMENT NO. 4    EXPERIMENT NAME: Write a VHDL code to implement 4 x 1 MUX using LOGIC GATES, IF ELSE AND WITH SELECT and simulate the design.

RESOURCES USED: Computer System, Xilinx ISE 9.2i

PRINCIPLE: A Multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data selector. Multiplexers can also be used to implement Boolean functions of multiple variables.

​Truth Table

Block Diagram

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VHDL CODE: 1) LOGIC GATE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity full_adder is port ( a : in std_logic; b : in std_logic; cin : in std_logic; -s : out std_logic; cout : out std_logic ); end​ half_adder; architecture Behavioral of full_adder is Begin s cout

<= a xor b xor cin; <= (a and b) or (b and cin) or (a and cin);

end​ rtl

2) IF ELSE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Mux is Port ( S : in STD_LOGIC_VECTOR (1 downto 0); I0 : in STD_LOGIC; I1 : in STD_LOGIC; I2 : in STD_LOGIC; I3 : in STD_LOGIC; Y : out STD_LOGIC); end Mux; architecture Behavioral of Mux is begin Y <= I0 when S= "00" else I1 when S= "01" else I2 when S= "10" else I3; end Behavioral;

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3) WITH SELECT library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Mux is Port ( S : in STD_LOGIC_VECTOR (1 downto 0); I0 : in STD_LOGIC; I1 : in STD_LOGIC; I2 : in STD_LOGIC; I3 : in STD_LOGIC; Y : out STD_LOGIC); end Mux; architecture Behavioral of Mux is begin with S select Y <= I0 when "00", I1 when "01", I2 when "10", I3 when others; end Behavioral;

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RTL SCHEMATIC: 1) LOGIC GATE

2) IF ELSE

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3) WITH SELECT

OUTPUT WAVEFORM: 1) LOGIC GATE

2) IF ELSE

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3) WITH SELECT

RESULT: The truth table of Full Adder is verified with the simulated circuit using basic ‘AND’, ‘OR’ and ‘XOR’ gate.

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