Datasheet Ic 74ls Series-national-semiconductor 2186c

54LS00/DM54LS00/DM74LS00 Quad 2-Input NAND Gates General Description

Features

This device contains four independent gates each of which performs the logic NAND function.

Y

Alternate Military/Aerospace device (54LS00) is available. a National Semiconductor Sales Office/ Distributor for specifications.

Connection Diagram Dual-In-Line Package

TL/F/6439 – 1

Order Number 54LS00DMQB, 54LS00FMQB, 54LS00LMQB, DM54LS00J, DM54LS00W, DM74LS00M or DM74LS00N See NS Package Number E20A, J14A, M14A, N14A or W14B

Function Table Y e AB Inputs

Output

A

B

Y

L L H H

L H L H

H H H L

H e High Logic Level L e Low Logic Level

C1995 National Semiconductor Corporation

TL/F/6439

RRD-B30M105/Printed in U. S. A.

54LS00/DM54LS00/DM74LS00 Quad 2-Input NAND Gates

June 1989

Absolute Maximum Ratings (Note) If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications.

Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation.

Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS and 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range

b 65§ C to a 150§ C

Recommended Operating Conditions Symbol

DM54LS00

Parameter

VCC

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IOH

High Level Output Current

IOL

Low Level Output Current

TA

Free Air Operating Temperature

DM74LS00

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

4 b 55

125

0

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol

Parameter

Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

Units

b 1.5

V

VI

Input Clamp Voltage

VCC e Min, II e b18 mA

VOH

High Level Output Voltage

VCC e Min, IOH e Max, VIL e Max

Low Level Output Voltage

VCC e Min, IOL e Max, VIH e Min

DM54

0.25

DM74

0.35

0.5

IOL e 4 mA, VCC e Min

DM74

0.25

0.4

VOL

V 0.4 V

II

Input Current @ Max Input Voltage

VCC e Max, VI e 7V

IIH

High Level Input Current

VCC e Max, VI e 2.7V

20

mA

IIL

Low Level Input Current


b 0.36

mA

IOS

Short Circuit Output Current

VCC e Max (Note 2)

ICCH

Supply Current with Outputs High

VCC e Max

0.8

1.6

mA

ICCL

Supply Current with Outputs Low

VCC e Max

2.4

4.4

mA

0.1

DM54

b 20

b 100

DM74

b 20

b 100

mA

mA

Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) RL e 2 kX Symbol

Parameter

CL e 15 pF

CL e 50 pF

Units

Min

Max

Min

Max

tPLH

Propagation Delay Time Low to High Level Output

3

10

4

15

ns

tPHL

Propagation Delay Time High to Low Level Output

3

10

4

15

ns

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

2

Physical Dimensions inches (millimeters)

Ceramic Leadless Chip Carrier Package (E) Order Number 54LS00LMQB NS Package Number E20A

3


14-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS00DMQB or DM54LS00J NS Package Number J14A

14-Lead Small Outline Molded Package (M) Order Number DM74LS00M NS Package Number M14A

4

Physical Dimensions inches (millimeters) (Continued)

14-Lead Molded Dual-In-Line Package (N) Order Number DM74LS00N NS Package Number N14A

5

54LS00/DM54LS00/DM74LS00 Quad 2-Input NAND Gates


14-Lead Ceramic Flat Package (W) Order Number 54LS00FMQB or DM54LS00W NS Package Number W14B

LIFE POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the . National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018

2. A critical component is any component of a life device or system whose failure to perform can be reasonably expected to cause the failure of the life device or system, or to affect its safety or effectiveness.

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National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to , before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE- APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.

Copyright  1996, Texas Instruments Incorporated

54LS02/DM54LS02/DM74LS02 Quad 2-Input NOR Gates General Description

Features

This device contains four independent gates each of which performs the logic NOR function.

Y

Alternate Military/Aerospace device (54LS02) is available. a National Semiconductor Sales Office/ Distributor for specifications


TL/F/6441 – 1


Function Table YeAaB Inputs

Output

A

B

Y

L L H H

L H L H

H L L L



TL/F/6441


54LS02/DM54LS02/DM74LS02 Quad 2-Input NOR Gates

June 1989




b 65§ C to a 150§ C


DM54LS02

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS02

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

4 b 55

125

0


Parameter

Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH





DM54

0.25

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V 0.4 V

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.40

mA

IOS


VCC e Max (Note 2)

ICCH


VCC e Max

1.6

3.2

mA

ICCL


VCC e Max

2.8

5.4

mA

0.1

DM54

b 20

b 100

DM74

b 20

b 100

mA

mA


Parameter

CL e 15 pF Min

CL e 50 pF

Max

Min

Units

Max

tPLH


13

18

ns

tPHL


10

15

ns


2



3




4



5

54LS02/DM54LS02/DM74LS02 Quad 2-Input NOR Gates









54LS03/DM54LS03/DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs General Description

Pull-Up Resistor Equations

This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

Features Y


RMAX e

VCC (Min) b VOH N1 (IOH) a N2 (IIH)

VCC (Max) b VOL RMIN e IOL b N3 (IIL) Where: N1 (IOH) e total maximum output high current for all outputs tied to pull-up resistor N2 (IIH) e total maximum input high current for all inputs tied to pull-up resistor N3 (IIL) e total maximum input low current for all inputs tied to pull-up resistor


TL/F/6344 – 1



Output

A

B

Y

L L H H

L H L H

H H H L



TL/F/6344


54LS03/DM54LS03/DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs

June 1989



Supply Voltage 7V Input Voltage 7V Output Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS and 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range

b 65§ C to a 150§ C


DM54LS03

Parameter

DM74LS03

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

V

VCC

Supply Voltage

VIH


VIL


0.7

0.8

VOH


5.5

5.5

V

IOL


4

8

mA

TA


70

§C

2

2

b 55

125

V

0

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI

Parameter

Conditions

Typ (Note 1)

Min

Max

Units

b 1.5

V

100

mA

Input Clamp Voltage


ICEX


VCC e Min, VO e 5.5V, VIL e Max

VOL



DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

II


VCC e Max, VI e 7V

IIH


IIL ICCH ICCL

V

0.1

mA


20

mA



b 0.36

mA


VCC e Max

0.8

1.6

mA


VCC e Max

2.4

4.4

mA


Parameter

CL e 15 pF

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


6

20

20

45

ns

tPHL


3

15

4

20

ns

Note 1: All typicals are at VCC e 5V, TA e 25§ C.

2

3




4




5

54LS03/DM54LS03/DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs









SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS SDLS029B – DECEMBER 1983 – REVISED FEBRUARY 2002

D

Dependable Texas Instruments Quality and Reliability

description These devices contain six independent inverters.

SN5404 . . . J PACKAGE SN54LS04, SN54S04 . . . J OR W PACKAGE SN7404 . . . D, N, OR NS PACKAGE SN74LS04 . . . D, DB, N, OR NS PACKAGE SN74S04 . . . D OR N PACKAGE (TOP VIEW)

1A 1Y 2A 2Y 3A 3Y GND

1

14

2

13

3

12

4

11

5

10

6

9

7

8

VCC 6A 6Y 5A 5Y 4A 4Y

SN5404 . . . W PACKAGE (TOP VIEW)

1A 2Y 2A

1

14

2

13

3

12

VCC 3A 3Y 4A

4

11

5

10

6

9

7

8

1Y 6A 6Y GND 5Y 5A 4Y

1Y 1A NC VCC 6A

SN54LS04, SN54S04 . . . FK PACKAGE (TOP VIEW)

4

3 2 1 20 19 18

5

17

6

16

7

15

8

14 9 10 11 12 13

6Y NC 5A NC 5Y

3Y GND NC 4Y 4A

2A NC 2Y NC 3A

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

1


ORDERING INFORMATION

PDIP – N

0°C to 70°C

ORDERABLE PART NUMBER

PACKAGE†

TA

SOIC – D

SOP – NS SSOP – DB

CDIP – J

–55°C to 125°C CFP – W

LCCC – FK

TOP-SIDE MARKING

Tube

SN7404N

SN7404N

Tube

SN74LS04N

SN74LS04N

Tube

SN74S04N

SN74S04N

Tube

SN7404D

7404

Tube

SN74LS04D

Tape and reel

SN74LS04DR

Tube

SN74S04D

Tape and reel

SN74S04DR

Tape and reel

SN7404NSR

SN7404

Tape and reel

SN74LS04NSR

74LS04

Tape and reel

SN74LS04DBR

LS04

Tube

SN5404J

SN5404J

Tube

SNJ5404J

SNJ5404J

Tube

SN54LS04J

SN54LS04J

Tube

SN54S04J

SN54S04J

Tube

SNJ54LS04J

SNJ54LS04J

Tube

SNJ54S04J

SNJ54S04J

Tube

SNJ5404W

SNJ5404W

Tube

SNJ54LS04W

SNJ54LS04W

Tube

SNJ54S04W

SNJ54S04W

Tube

SNJ54LS04FK

SNJ54LS04FK

Tube

SNJ54S04FK

LS04 S04

SNJ54S04FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each inverter)

2

INPUT A

OUTPUT Y

H

L

L

H




logic diagram (positive logic) 1A

1Y

2A

2Y

3A

3Y

4A

4Y

5A

5Y

6A

6Y

Y=A



3


schematics (each gate) ’04 VCC

4 kΩ

130 Ω

1.6 kΩ

Input A Output Y

1 kΩ GND

’LS04

’S04

VCC 20 kΩ

120 Ω

8 kΩ

Input A

VCC

4 kΩ

2.8 kΩ

Output Y

50 Ω

900 Ω

Input A

3.5 kΩ

Output Y

12 kΩ 500 Ω

250 Ω

3 kΩ 1.5 kΩ

GND GND

Resistor values shown are nominal.

4




absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V ’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions SN7404

SN5404 VCC VIH

Supply voltage

VIL IOH

Low-level input voltage

IOL TA

Low-level output current

High-level input voltage

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

2

2

High-level output current – 55

V V

0.8

0.8

V

–0.4

–0.4

mA

16

mA

70

°C

16

Operating free-air temperature

UNIT

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN5404 MIN TYP§

TEST CONDITIONS‡

PARAMETER VIK VOH

VCC = MIN, VCC = MIN,

II = – 12 mA VIL = 0.8 V,

VOL II

VCC = MIN, VCC = MAX,

VIH = 2 V, VI = 5.5 V

IIH IIL

VCC = MAX, VCC = MAX,

VI = 2.4 V VI = 0.4 V

IOS¶ ICCH

VCC = MAX VCC = MAX,

MAX

SN7404 MIN TYP§

– 1.5 IOH = –0.4 mA IOL = 16 mA

2.4

3.4 0.2

– 1.5 2.4

0.4

3.4 0.2

1

–20

MAX

UNIT V V

0.4 1

V mA

40

40

µA

– 1.6

– 1.6

mA

–55

mA

6

12

mA

ICCL VCC = MAX, 18 33 18 ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § All typical values are at VCC = 5 V, TA = 25°C. ¶ Not more than one output should be shorted at a time.

33

mA

VI = 0 V VI = 4.5 V

–55 6

–18

12

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER tPLH tPHL

FROM (INPUT)

TO (OUTPUT)

A

Y

SN5404 SN7404

TEST CONDITIONS MIN RL = 400 Ω Ω,


CL = 15 pF F


UNIT

TYP

MAX

12

22

8

15

ns

5


recommended operating conditions SN74LS04

SN54LS04 VCC VIH

Supply voltage

VIL IOH


IOL TA



MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

2

2

High-level output current – 55

V V

0.7

0.8

V

–0.4

–0.4

mA

8

mA

70

°C

4


UNIT

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIK VOH

SN54LS04 MIN TYP‡ MAX

TEST CONDITIONS†

PARAMETER VCC = MIN, VCC = MIN,

II = – 18 mA VIL = MAX,

VOL

VCC = MIN MIN,

VIH = 2 V

II IIH


VI = 7 V VI = 2.7 V

IIL IOS§

VCC = MAX, VCC = MAX

VI = 0.4 V

ICCH ICCL


VI = 0 V VI = 4.5 V


– 1.5 IOH = –0.4 mA IOL = 4 mA

2.5

3.4 0.25

– 1.5 2.7

3.4

0.4 0.25

0.5

V

0.1

0.1

mA

20

20

µA

– 0.4 –20

V V

0.4

IOL = 8 mA

UNIT

–100

–20

– 0.4

mA

–100

mA

1.2

2.4

1.2

2.4

mA

3.6

6.6

3.6

6.6

mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2) PARAMETER tPLH tPHL

6

FROM (INPUT)

TO (OUTPUT)

A

Y

TEST CONDITIONS

SN54LS04 SN74LS04 MIN

RL = 2 kΩ kΩ,


CL = 15 pF F


UNIT

TYP

MAX

9

15

10

15

ns


recommended operating conditions SN74S04

SN54S04 MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

UNIT

VCC VIH

Supply voltage

VIL IOH


0.8

0.8

V

High-level output current

–1

–1

mA

IOL TA


20

mA

70

°C


2

2

V

20


– 55

125

V

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54S04 MIN TYP‡ MAX

TEST CONDITIONS†

PARAMETER VIK VOH

VCC = MIN, VCC = MIN,

II = – 18 mA VIL = 0.8 V,

VOL II

VCC = MIN, VCC = MAX,

VIH = 2 V, VI = 5.5 V

IIH IIL


VI = 2.7 V VI = 0.5 V

IOS§ ICCH

VCC = MAX VCC = MAX,

SN74S04 MIN TYP‡ MAX

– 1.2 IOH = –1 mA IOL = 20 mA

2.5

3.4

–40

– 1.2 2.7

3.4

UNIT V V

0.5

0.5

1

1

V mA

50

50

µA

–2

–2

mA

–100

mA

15

24

mA

ICCL VCC = MAX, 30 54 30 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second.

54

mA

VI = 0 V VI = 4.5 V

–100 15

–40

24

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) FROM (INPUT)

TO (OUTPUT)

tPLH tPHL

A

Y

RL = 280 Ω Ω,

CL = 15 pF F

tPLH tPHL

A

Y

RL = 280 Ω Ω,

CL = 50 pF F

PARAMETER

SN54S04 SN74S04

TEST CONDITIONS MIN



UNIT

TYP

MAX

3

4.5

3

5

4.5 5

ns ns

7


PARAMETER MEASUREMENT INFORMATION SERIES 54/74 AND 54S/74S DEVICES VCC Test Point

VCC

RL (see Note B)

From Output Under Test CL (see Note A)

High-Level Pulse

1.5 V

S2

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V

Timing Input

1.5 V

1 kΩ

Test Point

LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS

S1 (see Note B)

CL (see Note A)

RL

CL (see Note A)

RL

From Output Under Test

VCC


Test Point

1.5 V 0V

tw Low-Level Pulse

1.5 V

tsu Data Input

1.5 V

VOLTAGE WAVEFORMS PULSE DURATIONS

1.5 V

1.5 V

In-Phase Output (see Note D)

tPHL VOH 1.5 V

Out-of-Phase Output (see Note D)

0V

1.5 V

1.5 V

Waveform 1 (see Notes C and D)

tPLZ

VOH 1.5 V

1.5 V VOL

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

≈1.5 V

1.5 V VOL tPZH

tPLH

1.5 V 0V

tPZL

VOL

tPHL

1.5 V

3V

Output Control (low-level enabling)

0V tPLH

3V 1.5 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

3V Input

th


VOL + 0.5 V

tPHZ VOH 1.5 V

VOH – 0.5 V ≈1.5 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

8




PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES VCC Test Point

VCC

RL


CL (see Note A)

High-Level Pulse

1.3 V

S2


Timing Input

1.3 V

5 kΩ

Test Point



S1 (see Note B)

CL (see Note A)

RL (see Note B)

RL


VCC


Test Point

1.3 V 0V

tw Low-Level Pulse

1.3 V

tsu

0V


3V 1.3 V

1.3 V 0V

tPZL

tPLZ

tPHL VOH 1.3 V

1.3 V


VOL tPZH

tPLH VOH 1.3 V

1.3 V VOL



≈1.5 V

1.3 V

VOL

tPHL Out-of-Phase Output (see Note D)

1.3 V 0V


1.3 V

tPLH

1.3 V


3V 1.3 V

3V

Data Input

1.3 V


Input

th

VOL + 0.5 V

tPHZ VOH 1.3 V

VOH – 0.5 V ≈1.5 V


NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement.




9

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should that such information is current and complete. All products are sold subject to TI’s and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265


54LS05/DM54LS05/DM74LS05 Hex Inverters with Open-Collector Outputs General Description

Pull-Up Resistor Equations

This device contains six independent gates each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

Features Y


RMAX e

VCC (Min) b VOH N1 (IOH) a N2 (IIH)

VCC (Max) b VOL RMIN e IOL b N3 (IIL) Where: N1 (IOH) e total maximum output high current for all outputs tied to pull-up resistor N2 (IIH) e total maximum input high current for all inputs tied to pull-up resistor N3 (IIL) e total maximum input low current for all inputs tied to pull-up resistor


TL/F/6346 – 1

Order Number 54LS05DMQB, 54LS05FMQB, DM54LS05J, DM54LS05W, DM74LS05M or DM74LS05N See NS Package Number E20A, J14A, M14A, N14A or W14B

Function Table YeA Input

Output

A

Y

L H

H L



TL/F/6346


54LS05/DM54LS05/DM74LS05 Hex Inverters with Open-Collector Outputs

June 1989



Supply Voltage 7V Input Voltage 7V Output Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS and 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range

b 65§ C to a 150§ C


DM54LS05

Parameter

DM74LS05

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

V

VCC

Supply Voltage

VIH


VIL


0.7

0.8

VOH


5.5

5.5

V

IOL


4

8

mA

TA


70

§C

2

2

b 55

125

V

0

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI

Parameter

Conditions

Typ (Note 1)

Min

Max

Units

b 1.5

V

100

mA

Input Clamp Voltage


ICEX


VCC e Min, VO e 5.5V VIL e Max

VOL


VCC e Min, IOL e Max VIH e Min

DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

II


VCC e Max, VI e 7V

IIH


IIL ICCH ICCL

V

0.1

mA


20

mA



b 0.36

mA


VCC e Max

1.2

2.4

mA


VCC e Max

3.6

6.6

mA


Parameter

CL e 15 pF

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


6

20

20

45

ns

tPHL


3

15

4

20

ns


2




3

54LS05/DM54LS05/DM74LS05 Hex Inverters with Open-Collector Outputs










SN54LS06, SN74LS06, SN74LS16 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS

The SN74LS16 is obsolete and is no longer supplied.

D D D D D

SDLS020B – MAY 1990 – REVISED JANUARY 2002

SN54LS06 . . . J PACKAGE SN74LS06, SN74LS16 . . . D, N, OR NS PACKAGE (TOP VIEW)

Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Input Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays Inputs Fully Compatible With Most TTL Circuits


description These hex inverter buffers/drivers feature high-voltage open-collector outputs to interface with high-level circuits (such as MOS), or for driving high-current loads, and also are characterized for use as inverter buffers for driving TTL inputs. The ’LS06 devices have a rated output voltage of 30 V, and the SN74LS16 has a rated output voltage of 15 V. The maximum sink current for the SN54LS06 is 30 mA, and for the SN74LS06 and SN74LS16 is 40 mA.

1

14

2

13

3

12

4

11

5

10

6

9

7

8


1Y 1A NC VCC 6A

SN54LS06 . . . FK PACKAGE (TOP VIEW)

2A NC 2Y NC 3A

3

2

1 20 19 18

5

17

6

16

7

15

8

14 9 10 11 12 13

6Y NC 5A NC 5Y

3Y GND NC 4Y 4A

These devices are compatible with most TTL families. Inputs are diode-clamped to minimize transmission effects, which simplifies design. Typical power dissipation is 175 mW and average propagation delay time is 8 ns.

4


ORDERING INFORMATION TOP-SIDE MARKING

Tube

SN74LS06D

Tape and reel

SN74LS06DR

SOP – NS

Tape and reel

SN74LS06NSR

74LS06

SSOP – DB

Tape and reel

SN74LS06DBR

LS06

PDIP – N

Tube

SN74LS06N

SN74LS06N

Tube

SN54LS06J

SN54LS06J

Tube

SNJ54LS06J

SNJ54LS06J

Tube

SNJ54LS06FK

SNJ54LS06FK

SOIC – D 0°C to 70°C

ORDERABLE PART NUMBER

PACKAGE†

TA

CDIP – J –55°C to 125°C LCCC – FK

LS06

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.






1




logic diagram (positive logic) 1A

2A

3A

4A

5A

6A

1

2

1Y

3

4

2Y

5

6

9

8

11

10

13

12

3Y

4Y

5Y

6Y

Pin numbers shown are for the D, J, N, and NS packages.

schematic (each gate) VCC 9 kΩ

2.5 kΩ

15 kΩ

1 kΩ

Output

2.5 kΩ

Input

2 kΩ

2 kΩ GND


2






absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Output voltage, VO (see Notes 1 and 2): SN54LS06, SN74LS06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. This is the maximum voltage that should be applied to any output when it is in the off state. 3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions SN74LS06 SN74LS16

SN54LS06

VCC VIH

Supply voltage

VIL



VOH

High level output voltage High-level

IOL TA


NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

2

2

’LS06

0.8

0.8

V

30

30

V

15

V

40

mA

70

°C

30 –55

V V

SN74LS16


UNIT

MIN

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74LS06 SN74LS16

SN54LS06

TEST CONDITIONS‡

PARAMETER

MIN VIK

VCC = MIN,

II = –12 mA

IOH

VCC = MIN MIN,

VIL = 0 0.8 8V

’LS06, VOH = 30 V SN74LS16, VOH = 15 V

VOL

VCC = MIN,

VIH = 2 V

IOL = 16 mA IOL = 30 mA IOL = 40 mA

TYP§

MAX

MIN

TYP§

UNIT MAX

–1.5

–1.5

0.25

0.25 0.25

0.25

0.4

0.25

V V

0.4 V

0.7 0.7

II IIH


VI = 7 V VI = 2.4 V

1

1

20

20

µA

IIL ICCH


VI = 0.4 V

–0.2

–0.2

mA

18

18

mA

60

mA

ICCL VCC = MAX 60 ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § All typical values are at VCC = 5 V, and TA = 25°C.



mA

3




switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

4

PARAMETER

FROM (INPUT)

TO (OUTPUT)

tPLH tPHL

A

Y


TEST CONDITIONS RL = 110 Ω Ω,


CL = 15 pF

MIN

MAX

7

15

10

20

UNIT ns




PARAMETER MEASUREMENT INFORMATION VCC Test Point

VCC

RL


CL (see Note A)

High-Level Pulse

1.3 V

S2


Timing Input

1.3 V

5 kΩ

Test Point



S1 (see Note B)

CL (see Note A)

RL (see Note B)

RL


VCC


Test Point

1.3 V 0V

tw Low-Level Pulse

1.3 V

tsu

0V


3V 1.3 V

1.3 V 0V

tPZL

tPLZ

tPHL VOH 1.3 V

1.3 V


VOL tPZH

tPLH VOH 1.3 V

1.3 V VOL



≈1.5 V

1.3 V

VOL

tPHL Out-of-Phase Output (see Note D)

1.3 V 0V


1.3 V

tPLH

1.3 V


3V 1.3 V

3V

Data Input

1.3 V


Input

th

VOL + 0.5 V

tPHZ VOH 1.3 V

VOH – 0.5 V ≈1.5 V


NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement.




5

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should that such information is current and complete. All products are sold subject to TI’s and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.



SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032D – DECEMBER 1983 – REVISED AUGUST 2001

D D D D D

SN5407, SN5417 . . . J OR W PACKAGE SN7407 . . . D, N, OR NS PACKAGE SN7417 . . . D OR N PACKAGE (TOP VIEW)



description

1

14

2

13

3

12

4

11

5

10

6

9

7

8


These TTL hex buffers/drivers feature high-voltage open-collector outputs for interfacing with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and also are characterized for use as buffers for driving TTL inputs. The SN5407 and SN7407 have minimum breakdown voltages of 30 V, and the SN5417 and SN7417 have minimum breakdown voltages of 15 V. The maximum sink current is 30 mA for the SN5407 and SN5417 and 40 mA for the SN7407 and SN7417. These devices perform Boolean function Y = A in positive logic. These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average propagation delay time is 14 ns. ORDERING INFORMATION ORDERABLE PART NUMBER

PACKAGE†

TA


Tube

SN7407D

Tape and reel

SN7407DR

Tube

SN7417D

Tape and reel

SN7417DR

PDIP – N

Tube

SOP – NS

Tape and reel

CDIP – J

Tube

55°C to 125°C –55°C CFP – W

Tube

TOP-SIDE MARKING 7407 7417

SN7407N

SN7407N

SN7417N

SN7417N

SN7407NSR

SN7407

SNJ5407J

SNJ5407J

SNJ5417J

SNJ5417J

SNJ5407W

SNJ5407W

SNJ5417W

SNJ5417W


logic diagram, each buffer/driver (positive logic) A

Y






1


schematic VCC 6 kΩ

3.4 kΩ

1.6 kΩ

Input A Output Y

100 Ω

1 kΩ GND


absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V Output voltage, VO (see Notes 1 and 2): SN5407, SN7407 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V SN5417, SN7417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. This is the maximum voltage that should be applied to any output when it is in the off state. 3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

2

VCC

Supply voltage

VIH VIL


VOH


IOL

Low level output current Low-level

TA

Operating free-air free air temperature

MIN

NOM

MAX

SN5407, SN5417

4.5

5

5.5

SN7407, SN7417

4.75

5

5.25

2

Low-level input voltage SN5407, SN7407

30

SN5417, SN7417

15

SN5407, SN5417

30

SN7407, SN7417

40

SN5407, SN5417

–55

125

SN7407, SN7417

0

70


V V

0.8


UNIT

V V mA °C


electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS†

PARAMETER

MIN

TYP‡

MAX

UNIT

–1.5

V

VIK

VCC = MIN,

II = –12 mA

IOH

VCC = MIN MIN,

VIH = 2 V

VOH = 30 V (SN5407, SN7407) VOH = 15 V (SN5417, SN7417)

0.25

VCC = MIN,

VIL = 0.8 V

IOL = 16 mA IOL = 30 mA (SN5407, SN5417) IOL = 40 mA (SN7407, SN7417)

0.4

VOL

0.25 0.7

mA

V

0.7

II IIH


VI = 5.5 V VIH = 2.4 V

40

1

mA µA

IIL ICCH


VIL = 0.4 V

–1.6

mA

29

41

mA

ICCL VCC = MAX 21 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C.

30

mA

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER

FROM (INPUT)

TO (OUTPUT)

tPLH tPHL

A

Y

RL = 110 Ω Ω,

CL = 15 pF

tPLH tPHL

A

Y

RL = 150 Ω, Ω

CL = 50 pF


TEST CONDITIONS

MIN

TYP

MAX

6

10

20

30 15


26

UNIT ns ns

3


PARAMETER MEASUREMENT INFORMATION VCC

RL From Output Under Test

Test Point CL (see Note A)

LOAD CIRCUIT 3V 1.5 V

Input

1.5 V 0V

tPLH High-Level Pulse

1.5 V

1.5 V

1.5 V

1.5 V

tPLH VOH

Out-of-Phase Output

1.5 V

1.5 V VOL


CL includes probe and jig capacitance. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 7 ns, tf ≤ 7 ns. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

4

1.5 V VOL

tPHL

VOLTAGE WAVEFORMS PULSE WIDTHS NOTES: A. B. C. D.

VOH

In-Phase Output

1.5 V tw

Low-Level Pulse

tPHL




D D D D D

SN5407, SN5417 . . . J OR W PACKAGE SN7407 . . . D, N, OR NS PACKAGE SN7417 . . . D OR N PACKAGE (TOP VIEW)



description

1

14

2

13

3

12

4

11

5

10

6

9

7

8


These TTL hex buffers/drivers feature high-voltage open-collector outputs for interfacing with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and also are characterized for use as buffers for driving TTL inputs. The SN5407 and SN7407 have minimum breakdown voltages of 30 V, and the SN5417 and SN7417 have minimum breakdown voltages of 15 V. The maximum sink current is 30 mA for the SN5407 and SN5417 and 40 mA for the SN7407 and SN7417. These devices perform Boolean function Y = A in positive logic. These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average propagation delay time is 14 ns. ORDERING INFORMATION ORDERABLE PART NUMBER

PACKAGE†

TA


Tube

SN7407D

Tape and reel

SN7407DR

Tube

SN7417D

Tape and reel

SN7417DR

PDIP – N

Tube

SOP – NS

Tape and reel

CDIP – J

Tube

55°C to 125°C –55°C CFP – W

Tube

TOP-SIDE MARKING 7407 7417

SN7407N

SN7407N

SN7417N

SN7417N

SN7407NSR

SN7407

SNJ5407J

SNJ5407J

SNJ5417J

SNJ5417J

SNJ5407W

SNJ5407W

SNJ5417W

SNJ5417W


logic diagram, each buffer/driver (positive logic) A

Y






1


schematic VCC 6 kΩ

3.4 kΩ

1.6 kΩ

Input A Output Y

100 Ω

1 kΩ GND


absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V Output voltage, VO (see Notes 1 and 2): SN5407, SN7407 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V SN5417, SN7417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. This is the maximum voltage that should be applied to any output when it is in the off state. 3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

2

VCC

Supply voltage

VIH VIL


VOH


IOL

Low level output current Low-level

TA

Operating free-air free air temperature

MIN

NOM

MAX

SN5407, SN5417

4.5

5

5.5

SN7407, SN7417

4.75

5

5.25

2

Low-level input voltage SN5407, SN7407

30

SN5417, SN7417

15

SN5407, SN5417

30

SN7407, SN7417

40

SN5407, SN5417

–55

125

SN7407, SN7417

0

70


V V

0.8


UNIT

V V mA °C


electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS†

PARAMETER

MIN

TYP‡

MAX

UNIT

–1.5

V

VIK

VCC = MIN,

II = –12 mA

IOH

VCC = MIN MIN,

VIH = 2 V

VOH = 30 V (SN5407, SN7407) VOH = 15 V (SN5417, SN7417)

0.25

VCC = MIN,

VIL = 0.8 V

IOL = 16 mA IOL = 30 mA (SN5407, SN5417) IOL = 40 mA (SN7407, SN7417)

0.4

VOL

0.25 0.7

mA

V

0.7

II IIH


VI = 5.5 V VIH = 2.4 V

40

1

mA µA

IIL ICCH


VIL = 0.4 V

–1.6

mA

29

41

mA

ICCL VCC = MAX 21 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C.

30

mA

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER

FROM (INPUT)

TO (OUTPUT)

tPLH tPHL

A

Y

RL = 110 Ω Ω,

CL = 15 pF

tPLH tPHL

A

Y

RL = 150 Ω, Ω

CL = 50 pF


TEST CONDITIONS

MIN

TYP

MAX

6

10

20

30 15


26

UNIT ns ns

3


PARAMETER MEASUREMENT INFORMATION VCC

RL From Output Under Test

Test Point CL (see Note A)

LOAD CIRCUIT 3V 1.5 V

Input

1.5 V 0V

tPLH High-Level Pulse

1.5 V

1.5 V

1.5 V

1.5 V

tPLH VOH

Out-of-Phase Output

1.5 V

1.5 V VOL


CL includes probe and jig capacitance. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 7 ns, tf ≤ 7 ns. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

4

1.5 V VOL

tPHL

VOLTAGE WAVEFORMS PULSE WIDTHS NOTES: A. B. C. D.

VOH

In-Phase Output

1.5 V tw

Low-Level Pulse

tPHL



IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to , before placing orders, that information being relied on is current and complete. All products are sold subject to the and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, license, warranty or endorsement thereof. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Also see: Standard and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/std.htm



54LS08/DM54LS08/DM74LS08 Quad 2-Input AND Gates General Description

Features

This device contains four independent gates each of which performs the logic AND function.

Y



TL/F/6347 – 1



Output

A

B

Y

L L H H

L H L H

L L L H



TL/F/6347


54LS08/DM54LS08/DM74LS08 Quad 2-Input AND Gates

June 1989




b 65§ C to a 150§ C


DM54LS08

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS08

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

2

2

V

4 b 55

125

0


Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH


VCC e Min, IOH e Max, VIH e Min

DM54

2.5

3.4

DM74

2.7

3.4


VCC e Min, IOL e Max, VIL e Max

DM54

0.25

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V 0.4 V

II


VCC e Max, VI e 7V

IIH


IIL


VCC e Max, VI e 2.7V VCC e Max, VI e 0.4V

IOS


VCC e Max (Note 2)

ICCH


VCC e Max

2.4

4.8

mA

ICCL


VCC e Max

4.4

8.8

mA

0.1

mA

20

mA

b 0.36

mA

DM54

b 20

b 100

DM74

b 20

b 100

mA


CL e 15 pF

Parameter

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


4

13

6

18

ns

tPHL


3

11

5

18

ns


2

3




4




5

54LS08/DM54LS08/DM74LS08 Quad 2-Input AND Gates









SN54ALS09, SN74ALS09 QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS SDAS084B – APRIL 1982 – REVISED DECEMBER 1994

SN54ALS09 . . . J PACKAGE SN74ALS09 . . . D OR N PACKAGE (TOP VIEW)

Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

1A 1B 1Y 2A 2B 2Y GND

description These devices contain four independent 2-input positive-AND gates. They perform the Boolean functions Y = A • B or Y = A + B in positive logic. The open-collector outputs require pullup resistors to perform correctly. These outputs may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOH levels.

OUTPUT Y

H

H

H

L

X

L

X

L

L

1B 2A 2B 3A 3B 4A 4B

1

12

4

11

5

10

6

9

7

8

4

3 2 1 20 19 18

5

17

6

16

7

15

8

14 9 10 11 12 13

4A NC 4Y NC 3B


logic symbol† 1A

3

VCC 4B 4A 4Y 3B 3A 3Y

2Y GND NC 3Y 3A

B

13

1B 1A NC VCC 1Y NC 2A NC 2B

FUNCTION TABLE (each gate) A

14

2

SN54ALS09 . . . FK PACKAGE (TOP VIEW)

The SN54ALS09 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS09 is characterized for operation from 0°C to 70°C.

INPUTS

1

4B

•

logic diagram (positive logic) &

3

2 4

6

5

1Y

2Y

8

3Y

2A

3A 3B

12 13

1B

2B

9 10

1A

11

4Y

4A 4B

1 2

3

1Y

4 5

6

2Y

9 10

8

3Y

12 13

11

4Y

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.





1


absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions SN54ALS09

SN74ALS09

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.5

5

5.5

UNIT

VCC VIH

Supply voltage

VIL VOH


0.7

0.8

High-level output voltage

5.5

5.5

IOL TA


4

8

mA

70

°C


2


2

– 55

125

V V

0

V V

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER

SN54ALS09 TYP‡ MAX

TEST CONDITIONS

VIK

VCC = 4.5 V,

VOL

5V VCC = 4 4.5

II IIH

VCC = 5.5 V, VCC = 5.5 V,

IIL IOH

VCC = 5.5 V, VCC = 4.5 V,

ICCH ICCL

VCC = 5.5 V, VCC = 5.5 V,

MIN

II = –18 mA IOL = 4 mA

SN74ALS09 TYP‡ MAX

MIN

–1.5 0.25

IOL = 8 mA VI = 7 V VI = 2.7 V VI = 0.4 V VOH = 5.5 V VI = 4.5 V

–1.5

0.4

0.25

0.4

0.35

0.5

V V

0.1

0.1

20

20

µA

– 0.1

– 0.1

mA

0.1

VI = 0

UNIT

mA

0.1

mA

1.35

2.4

1.35

2.4

mA

2.2

4

2.2

4

mA

‡ All typical values are at VCC = 5 V, TA = 25°C.

switching characteristics (see Figure 1)

PARAMETER

FROM (INPUT)

TO (OUTPUT)

VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 2 kΩ, TA = MIN to MAX§ SN54ALS09

tPLH tPHL

A or B

Y

MIN

MAX

MIN

MAX

20

69

23

54

5

23

5

15

§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

2



UNIT

SN74ALS09

ns


PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2

VCC S1 RL R1

Test Point



RL

Test Point


CL (see Note A)

LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS


3.5 V

Timing Input

Test Point

LOAD CIRCUIT FOR 3-STATE OUTPUTS

3.5 V

High-Level Pulse

1.3 V

R2

1.3 V

1.3 V 0.3 V

0.3 V tsu Data Input

tw

th 3.5 V 1.3 V

3.5 V

Low-Level Pulse

1.3 V 0.3 V

1.3 V

0.3 V



3.5 V


1.3 V

1.3 V 0.3 V

tPZL Waveform 1 S1 Closed (see Note B)

tPLZ

[3.5 V

1.3 V

tPHZ tPZH Waveform 2 S1 Open (see Note B)

1.3 V

VOL 0.3 V VOH

1.3 V

0.3 V

[0 V

3.5 V 1.3 V

Input

1.3 V 0.3 V tPHL

tPLH

VOH

In-Phase Output

1.3 V

1.3 V VOL tPLH

tPHL

VOH

Out-of-Phase Output (see Note C)

1.3 V

1.3 V VOL



NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement.




3

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to , before placing orders, that information being relied on is current and complete. All products are sold subject to the and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE- DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


54LS10/DM54LS10/DM74LS10 Triple 3-Input NAND Gates General Description

Features

This device contains three independent gates each of which performs the logic NAND function.

Y



TL/F/6349 – 1


Function Table Y e ABC Inputs

Output

A

B

C

Y

X X L H

X L X H

L X X H

H H H L

H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level


TL/F/6349


54LS10/DM54LS10/DM74LS10 Triple 3-Input NAND Gates

June 1989




b 65§ C to a 150§ C


DM54LS10

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS10

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

4 b 55

125

0


Parameter

Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH





DM54

0.25

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V 0.4 V

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.36

mA

IOS


VCC e Max (Note 2)

ICCH


VCC e Max

0.6

1.2

mA

ICCL


VCC e Max

1.8

3.3

mA

0.1

DM54

b 20

b 100

DM74

b 20

b 100

mA

mA


Parameter

CL e 15 pF

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


3

10

4

15

ns

tPHL


3

10

4

15

ns


2

3




4




5

54LS10/DM54LS10/DM74LS10 Triple 3-Input NAND Gates









54LS11/DM54LS11/DM74LS11 Triple 3-Input AND Gates General Description

Features

This device contains three independent gates each of which performs the logic AND function.

Y

Alternate military/aerospace device (54LS11) is available. a National Semiconductor Sales Office/ Distributor for specifications.


TL/F/6350 – 1


Function Table Y e ABC Inputs

Output

A

B

C

Y

X X L H

X L X H

L X X H

L L L H



TL/F/6350


54LS11/DM54LS11/DM74LS11 Triple 3-Input AND Gates

June 1989




b 65§ C to a 150§ C


DM54LS11

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS11

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

2

2

V

4 b 55

125

0


Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH


VCC e Min, IOH e Max VIH e Min

DM54

2.5

3.4

DM74

2.7

3.4


VCC e Min, IOL e Max VIL e Max

DM54

0.25

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V 0.4 V

II


VCC e Max, VI e 7V

IIH


IIL



IOS


VCC e Max (Note 2)

ICCH


VCC e Max

1.8

3.6

mA

ICCL


VCC e Max

3.3

6.6

mA

0.1

mA

20

mA

b 0.36

mA

DM54

b 20

b 100

DM74

b 20

b 100

mA


Parameter

CL e 15 pF

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


4

13

6

18

ns

tPHL


3

11

5

18

ns


2

3




4




5

54LS11/DM54LS11/DM74LS11 Triple 3-Input AND Gates













54LS14/DM74LS14 Hex Inverters with Schmitt Trigger Inputs General Description This device contains six independent gates each of which performs the logic INVERT function. Each input has hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output.


TL/F/6353 – 1

Order Number 54LS14DMQB, 54LS14FMQB, 54LS14LMQB, DM74LS14M or DM74LS14N See NS Package Number E20A, J14A, M14A, N14A or W14B

Function Table YeA Input

Output

A

Y

L H

H L



TL/F/6353


54LS14/DM74LS14 Hex Inverters with Schmitt Trigger Inputs

June 1989



Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range

b 65§ C to a 150§ C


54LS14

Parameter

DM74LS14

Units

Min

Nom

Max

Min

Nom

Max

VCC

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VT a

Positive-Going Input Threshold Voltage (Note 1)

1.5

1.6

2.0

1.4

1.6

1.9

V

VTb

Negative-Going Input Threshold Voltage (Note 1)

0.6

0.8

1.1

0.5

0.8

1

V

HYS

Input Hysteresis (Note 1)

0.4

0.8

0.4

0.8

IOH


b 0.4

mA

IOL


8

mA

TA


70

§C

b 0.4

4 b 55

125

0

V


Parameter

Conditions

Min

Typ (Note 2)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH


VCC e Min, IOH e Max VIL e Max



54LS DM74

0.35

0.5

VCC e Min, IOL e 4 mA

DM74

0.25

0.4

VOL

54LS

2.5

3.4

DM74

2.7

3.4

IT a

Input Current at Positive-Going Threshold

VCC e 5V, VI e VT a

DM74

IT b

Input Current at Negative-Going Threshold

VCC e 5V, VI e VTb

DM74

II


VCC e Max, VI e 7V

DM74


54LS

0.25

V 0.4 V

b 0.14

mA

b 0.18

mA 0.1

mA

IIH



20

mA

IIL



b 0.4

mA

IOS


VCC e Max (Note 3)

ICCH


VCC e Max

8.6

16

mA

ICCL


VCC e Max

12

21

mA

54LS

b 20

b 100

DM74

b 20

b 100

Note 1: VCC e 5V. Note 2: All typicals are at VCC e 5V, TA e 25§ C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

2

mA


CL e 15 pF

Parameter

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


5

22

8

25

ns

tPHL


5

22

10

33

ns

3


Ceramic Leadless Chip Carrier (E) Order Number 54LS14LMQB NS Package Number E20A

14-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS14DMQB NS Package Number J14A

4




5

54LS14/DM74LS14 Hex Inverters with Schmitt Trigger Inputs


14-Lead Ceramic Flat Package (W) Order Number 54LS14FMQB NS Package Number W14B







SN54LS06, SN54LS16, SN74LS06, SN74LS16 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS020A – MAY 1990

• • • • •

Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Input Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays Package Options Include “Small Outline” Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

SN54LS06, SN54LS16 . . . J PACKAGE SN74LS06, SN74LS16 . . . D OR N PACKAGE (T0P VIEW)


1

14

2

13

3

12

4

11

5

10

6

9

7

8


description

These circuits are compatible with most TTL families. Inputs are diode-clamped to minimize transmission-effects, which simplifies design. Typical power dissipation is 175 mW and average propagation delay time is 8 ns.

1Y 1A NC VCC 6A

SN54LS06, SN54LS16 . . . FK PACKAGE (T0P VIEW)

2A NC 2Y NC 3A

4

3 2 1 20 19 18

5

17

6

16

7

15

8

14 9 10 11 12 13

6Y NC 5A NC 5Y

3Y GND NC 4Y 4A

These monolithic hex inverter buffers/drivers feature high-voltage open-collector outputs to interface with high-level circuits (such as MOS), or for driving high-current loads, and are also characterized for use as inverter buffers for driving TTL inputs. The ′LS06 has a rated output voltage of 30 V and the ′LS16 has a rated output voltage of 15 V. The maximum sink current for the SN54LS06 and SN54LS16 is 30 mA and the SN74LS06 and SN74LS16 is 40 mA.


The SN54LS06 and SN54LS16 are characterized over the full military temperature range of – 55°C to 125°C. The SN74LS06 and SN74LS16 are characterized for operation from 0°C to 70°C.

logic symbol†

logic diagram (positive logic)

1A 1 2A 3

2 1Y 4 2Y

1A

3A 5 4A 9

6 3Y 8 4Y

2A

5A 11 6A 13

10 5Y 12 6Y

3A

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, J, and N packages.

4A

5A

6A

1

2

1Y

3

4

2Y

5

6

9

8

11

10

13

12

3Y

4Y

5Y

6Y


UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303


1


schematic (each gate) VCC 2.5 kΩ

9 kΩ

1 kΩ

15 kΩ

Output

2.5 kΩ

Input

2 kΩ

2 kΩ GND

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Output voltage, VO (see Notes 1 and 2): SN54LS06, SN74LS06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V SN54LS16, SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Operating free-air temperature range: SN54LS06, SN54LS16 . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74LS06, SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. This is the maximum voltage that should be applied to any output when it is in the off state.

recommended operating conditions SN54LS06

SN74LS06

SN54LS16 VCC VIH

Supply voltage

VIL



VOH


IOL TA


UNIT

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.8

0.8

’LS06

30

30

’LS16

15

15

V

30

40

mA

70

°C


– 55

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

2

SN74LS16

MIN



125

0

V


electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS06 TEST CONDITIONS†

PARAMETER VIK

VCC = MIN,

II = – 12 mA

IOH

VCC = MIN,

VIL = 0.8 V

VOL

VCC = MIN,

VIH = 2 V

SN74LS06


’LS06, VOH = 30 V ’LS16, VOH = 15 V IOL = 16 mA IOL = 30 mA

SN74LS16 TYP‡ MAX

– 1.5

– 1.5

0.25

0.25

0.25

0.25

0.25

UNIT

MIN

0.4

0.25

V mA

0.4

0.7

V

IOL = 40 mA

0.7

II IIH


VI = 7 V VI = 2.4 V

1

1

20

20

µA

IIL ICCH

VCC =MAX, VCC = MAX

VI = 0.4 V

– 0.2

– 0.2

mA

18

18

mA

60

mA

ICCL VCC = MAX 60 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, and TA = 25°C.

mA

switching characteristics, VCC = 5 V, TA = 25°C (see Note 3) PARAMETER tPLH tPHL

FROM

TO

(INPUT)

(OUTPUT)

A

Y

TEST CONDITIONS RL = 110 Ω,

CL = 15 pF

MIN

TYP

MAX

7

15

10

20

UNIT ns

NOTE 3: Load circuit and voltage waveforms are shown in Section 1 of TTL Logic Data Book, 1988.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.



3



SN54LS07, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS021A, D3517, MAY 1990–REVISED AUGUST 1991

• • • • •

Converts TTL-Voltage Levels to MOS Levels

SN54LS07 . . . J PACKAGE SN74LS07, SN74LS17 . . . D OR N PACKAGE (T0P VIEW)

High Sink-Current Capability 1A 1Y 2A 2Y 3A 3Y GND

Input Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays Package Options Include “Small Outline” Packages, Ceramic Chip Carriers, and Standard and Ceramic 300-mil DIPs

1

14

2

13

3

12

4

11

5

10

6

9

7

8


SN54LS07 . . . FK PACKAGE (T0P VIEW)

These circuits are compatible with most TTL families. Inputs are diode-clamped to minimize transmission-line effects, which simplifies design. Typical power dissipation is 140 mW and average propagation delay time is 12 ns.

2A NC 2Y NC 3A

4

3 2 1 20 19 18

5

17

6

16

7

15

8

14 9 10 11 12 13

6Y NC 5A NC 5Y

3Y GND NC 4Y 4A

These monolithic hex buffers/drivers feature high-voltage open-collector outputs to interface with high-level circuits or for driving high-current loads. They are also characterized for use as buffers for driving TTL inputs. The ′LS07 has a rated output voltage of 30 V and the ′LS17 has a rated output voltage of 15 V. The maximum sink current is 30 mA for the SN54LS07 and 40 mA for the SN74LS07 and SN74LS17.

1Y 1A NC VCC 6A

description


The SN54LS07 is characterized over the full military temperature range of –55°C to 125°C. The SN74LS07 and SN74LS17 are characterized for operation from 0°C to 70°C.

logic symbol†

logic diagram (positive logic)

1A 1 2A 3

2 1Y 4 2Y

3A 5 4A 9

6 3Y 8 4Y

5A 11 6A 13

10 5Y 12 6Y

1A

2A

3A

4A

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, J, and N packages.

5A

6A

1

2

3

4

5

6

9

8

11

10

13

12

1Y

2Y

3Y

4Y

5Y

6Y





1

SN54LS07, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS schematic (each gate) VCC 1 kΩ

9 kΩ

5 kΩ

Output

Input

2 kΩ 2 kΩ

GND


absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Output voltage, VO (see Notes 1 and 2): SN54LS07, SN74LS07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V SN74LS17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Operating free-air temperature range: SN54LS07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN54LS07, SN74LS17 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. This is the maximum voltage that should be applied to any output when it is in the off state.

recommended operating conditions SN74LS07 SN54LS07 VCC VIH

Supply voltage

VIL



2


TA


MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

2

2 0.8

30

30

30 – 55


125

0

V V

0.8 ’LS17



UNIT

NOM

’LS07 VOH IOL

SN74LS17

MIN

V

15

V

40

mA

70

°C

SN54LS07, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

MIN VIK

VCC = MIN,

SN74LS07

SN54LS07

TEST CONDITIONS†

PARAMETER

TYP‡

II = – 12 mA

MAX

SN74LS17 TYP‡ MAX

UNIT

MIN

– 1.5

– 1.5

0.25

0.25

0.25

0.25

0.4

0.4

0.7

0.7

V

IOH

VCC = MIN,

VIH = 2 V

’LS07, VOH = 30 V ’LS17, VOH = 15 V

VOL

VCC = MIN,

VIL = 0.8 V

IOL = 16 mA IOL = MAX§

II IIH


VI = 7 V VI = 2.4 V

1

1

20

20

µA

IIL ICCH


VI = 0.4 V

– 0.2

– 0.2

mA

14

14

mA

45

mA

ICCL VCC = MAX 45 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § IOL = 30 mA for SN54 series parts and 40 mA for SN74 series parts.

mA V mA

switching characteristics, VCC = 5 V, TA = 25°C (see Note 3) PARAMETER tPLH tPHL

FROM

TO

(INPUT)

(OUTPUT)

A

Y

TEST CONDITIONS RL = 110 Ω,

CL = 15 pF

MIN

TYP

MAX

6

10

19

30

UNIT ns

NOTE 3: Load circuit and voltage waveforms are shown in Section 1 of TTL Logic Data Book, 1988.



3



54LS20/DM54LS20/DM74LS20 Dual 4-Input NAND Gates General Description

Features

This device contains two independent gates each of which performs the logic NAND function.

Y

Alternate Military/Aerospace device (54LS20) is available. a National Semiconductor Sales Office/ Distributor for specifications


TL/F/6355 – 1


Function Table Y e ABCD Inputs

Output

A

B

C

D

Y

X X X L H

X X L X H

X L X X H

L X X X H

H H H H L



TL/F/6355


54LS20/DM54LS20/DM74LS20 Dual 4-Input NAND Gates

June 1989




b 65§ C to a 150§ C


DM54LS20

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS20

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

2

2

V

4 b 55

125

0


Parameter

Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH





DM54

0.25

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V 0.4 V

II


VCC e Max, VI e 7V

IIH


IIL



IOS


VCC e Max (Note 2)

ICCH


VCC e Max

0.4

0.8

mA

ICCL


VCC e Max

1.2

2.2

mA

0.1

mA

20

mA

b 0.36

mA

DM54

b 20

b 100

DM74

b 20

b 100

mA


Parameter

CL e 15 pF

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


3

10

4

15

ns

tPHL


3

10

4

15

ns


2

3




4




5

54LS20/DM54LS20/DM74LS20 Dual 4-Input NAND Gates









54LS21/DM54LS21/DM74LS21 Dual 4-Input AND Gates General Description

Features

This device contains two independent gates each of which performs the logic AND function.

Y



TL/F/6356 – 1


Function Table Y e ABCD Inputs

Output

A

B

C

D

Y

X X X L H

X X L X H

X L X X H

L X X X H

L L L L H



TL/F/6356


54LS21/DM54LS21/DM74LS21 Dual 4-Input AND Gates

June 1989




b 65§ C to a 150§ C


DM54LS21

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS21

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

2

2

V

4 b 55

125

0


Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH


VCC e Min, IOH e Max, VIH e Min

DM54

2.5

3.4

DM74

2.7

3.4


VCC e Min, IOL e Max, VIL e Max

DM54

0.25

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V 0.4 V

II


VCC e Max, VI e 7V

IIH


IIL



IOS


VCC e Max (Note 2)

ICCH


VCC e Max

1.2

2.4

mA

ICCL


VCC e Max

2.2

4.4

mA

0.1

mA

20

mA

b 0.36

mA

DM54

b 20

b 100

DM74

b 20

b 100

mA


CL e 15 pF

Parameter

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


4

13

6

18

ns

tPHL


3

11

5

18

ns


2

3




4




5

54LS21/DM54LS21/DM74LS21 Dual 4-Input AND Gates













DM54LS27/DM74LS27 Triple 3-Input NOR Gates General Description This device contains three independent gates each of which performs the logic NOR function.


TL/F/6359 – 1

Order Number DM54LS27J, DM54LS27W, DM54LS27E, DM74LS27M or DM74LS27N See NS Package Number E20A, J14A, M14A, N14A or W14B

Function Table YeAaBaC Inputs

Output

A

B

C

Y

L X X H

L X H X

L H X X

H L L L



TL/F/6359


DM54LS27/DM74LS27 Triple 3-Input NOR Gates

May 1992

Absolute Maximum Ratings (Note) b 65§ C to a 150§ C Storage Temperature Range Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation.

If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS and 54LS DM74LS 0§ C to a 70§ C


DM54LS27

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS27

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

2

2

V

4 b 55

125

0


Parameter

Conditions

Typ (Note 1)

Min

Max

Units

b 1.5

V

VI

Input Clamp Voltage

VOH


VCC e Min, II e b18 mA VCC e Min, IOH e Max, VIL e Max



DM54 DM74

0.35

0.5


DM74

0.25

0.4

VOL

DM54

2.5

DM74

2.7

V 3.4 0.4 V

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.36

mA

IOS


VCC e Max (Note 2)

ICCH


VCC e Max

2

4

mA

ICCL


VCC e Max

3.4

6.8

mA

0.1

DM54

b 20

b 100

DM74

b 20

b 100

mA

mA

Switching Characteristics at VCC e 5V and TA e 25§ C DM54 Symbol

DM74 RL e 2 kX

Parameter CL e 15 pF

Units

CL e 15 pF

CL e 50 pF

Min

Max

Min

Max

Min

Max

tPLH


3

13

3

13

5

18

ns

tPHL


3

13

3

10

4

15

ns


2

3


Ceramic Leadless Chip Carrier Package (E) Order Number DM54LS27E NS Package Number E20A

14-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS27J NS Package Number J14A 4




5

DM54LS27/DM74LS27 Triple 3-Input NOR Gates


14-Lead Ceramic Flat Package (W) Order Number DM54LS27W NS Package Number W14B









54LS30/DM54LS30/DM74LS30 8-Input NAND Gate General Description

Features

This device contains a single gate which performs the logic NAND function.

Y



TL/F/6360 – 1


Function Table Y e ABCDEFGH Inputs

Output

A thru H

Y

All Inputs H One or More Input L

L H



TL/F/6360


54LS30/DM54LS30/DM74LS30 8-Input NAND Gate

June 1989




b 65§ C to a 150§ C


DM54LS30

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS30

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

4 b 55

125

0


Parameter

Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH





DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V

V

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.4

mA

IOS


VCC e Max (Note 2)

ICCH


VCC e Max

0.35

0.5

mA

ICCL


VCC e Max

0.6

1.1

mA

0.1

DM54

b 20

b 100

DM74

b 20

b 100

mA

mA


Parameter

CL e 15 pF

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


4

12

5

18

ns

tPHL


4

15

5

20

ns


2

3




4




5

54LS30/DM54LS30/DM74LS30 8-Input NAND Gate











54LS32/DM54LS32/DM74LS32 Quad 2-Input OR Gates General Description

Features

This device contains four independent gates each of which performs the logic OR function.

Y



TL/F/6361 – 1


Function Table YeAaB Inputs

Output

A

B

Y

L L H H

L H L H

L H H H



TL/F/6361


54LS32/DM54LS32/DM74LS32 Quad 2-Input OR Gates

May 1989

Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation.

If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS and 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range

b 65§ C to a 150§ C


DM54LS32

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS32

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

4 b 55

125

0

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL

Parameter

Conditions

Typ (Note 1)

Min

Max

Units

b 1.5

V

Input Clamp Voltage



VCC e Min, IOH e Max VIH e Min

DM54

2.5

3.4

DM74

2.7

3.4



DM54

0.25

DM74

0.35

0.5


DM74

0.25

0.4

V 0.4 V


VCC e Max, VI e 7V

IIH


IIL



IOS


VCC e Max (Note 2)

ICCH


VCC e Max

3.1

6.2

mA

ICCL


VCC e Max

4.9

9.8

mA

II

0.1

mA

20

mA

b 0.36

mA

DM54

b 20

b 100

DM74

b 20

b 100

mA


Parameter

CL e 15 pF

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


3

11

4

15

ns

tPHL


3

11

4

15

ns


2

3




4




5

54LS32/DM54LS32/DM74LS32 Quad 2-Input OR Gates

















SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49 SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS SDLS111 – MARCH 1974 – REVISED MARCH 1988





1


2






3


4






5


6






7


8






9


10






11


12






13

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to , before placing orders, that information being relied on is current and complete. All products are sold subject to the and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE- DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


SN54/74LS48 BCD TO 7-SEGMENT DECODER The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INVERT gates. The remaining NAND gate and three input buffers provide lamp test, blanking input/rippleblanking input for the LS48. The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on the state of the auxiliary inputs, decodes this data to drive other components. The relative positive logic output levels, as well as conditions required at the auxiliary inputs, are shown in the truth tables. The LS48 circuit incorporates automatic leading and / or trailing edge zero-blanking control (RBI and RBO). Lamp Test (LT) may be activated any time when the BI / RBO node is HIGH. Both devices contain an overriding blanking input (BI) which can be used to control the lamp intensity by varying the frequency and duty cycle of the BI input signal or to inhibit the outputs. • Lamp Intensity Modulation Capability (BI/RBO) • Internal Pull-Ups Eliminate Need for External Resistors • Input Clamp Diodes Eliminate High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16

f

g

a

b

c

d

e

15

14

13

12

11

10

9

BCD TO 7-SEGMENT DECODER LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 620-09 16 1

N SUFFIX PLASTIC CASE 648-08

16 1

D SUFFIX SOIC CASE 751B-03

16 1

1

2

3

4

5

B

C

LT BI / RBO RBI

6

7

8

D

A

GND

ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD

LOGIC DIAGRAM

Ceramic Plastic SOIC

a

LOGIC SYMBOL

A

7 1 2 6 3 5

b B INPUT C

SN54 / 74LS48

D

BLANKING INPUT OR RIPPLE-BLANKING OUTPUT

RIPPLE-BLANKING INPUT LAMP-TEST INPUT

A B C D LT RBI

c OUTPUT

a

e

13 12 11 10 9 15 14 4

f

g

FAST AND LS TTL DATA 5-1

b c d

e

BI/ f g RBO

d

VCC = PIN 16 GND = PIN 8

SN54/74LS48 PIN NAMES

LOADING (Note a) LOW

HIGH A, B, C, D RBI LT BI / RBO

0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 1.2 U.L. 0.5 U.L. Open-Collector

BCD Inputs Ripple-Blanking (Active Low) Input Lamp-Test (Active Low) Input Blanking Input or RippleBlanking Output (Active Low) Blanking (Active Low) Input

BI

0.25 U.L. 0.25 U.L. 0.25 U.L. 0.75 U.L. 2(1) U.L. 0.25 U.L. 3.75 (1.25) U.L. (48)

NOTES: a) Unit Load (U.L.) = 40 µA HIGH / 1.6 mA LOW b) Outut current measured at VOUT = 0.5 V Output LOW drive factor is SN54LS / 74LS48: 1.25 U.L. for Military (54), 3.75 U.L. for Commercial (74).

0

1

2

3

4

5

6

7

8

9

10

11 12

13

14

15

NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS

TRUTH TABLE SN54 / 74LS48 INPUTS

OUTPUTS

DECIMAL OR FUNCTION

LT

RBI

D

C

B A

0

H

H

L

L

L

1

H

X

L

L

L

2

H

X

L

L

H

3

H

X

L

4

H

X

5

H

X

6

H

7

BI / RBO

a

b

c

d

e

f

g

NOTE

L

H

H

H

H

H

H

H

L

1

H

H

L

H

H

L

L

L

L

1

L

H

H

H

L

H

H

L

H

L

H H

H

H

H

H

H

L

L

H

L

H

L

L

H

L

H

H

L

L

H

H

L

H

L

H

H

H

L

H

H

L

H

H

X

L

H

H

L

H

L

L

H

H

H

H

H

H

X

L

H

H H

H

H

H

H

L

L

L

L

8

H

X

H

L

L

L

H

H

H

H

H

H

H

H

NOTES: (1) BI/RBO is wired-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held at a HIGH level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking of a decimal 0 is not desired. X=input may be HIGH or LOW. (2) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level, regardless of the state of any other input condition. (3) When ripple-blanking input (RBI) and inputs A, B, C, and D are at LOW level, with the lamp test input at HIGH level, all segment outputs go to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition). (4) When the blanking input/ripple-blanking output (BI/RBO) is open or held at a HIGH level, and a LOW level is applied to lamp-test input, all segment outputs go to a LOW level.

9

H

X

H

L

L

H

H

H

H

H

L

L

H

H

10

H

X

H

L

H

L

H

L

L

L

H

H

L

H

11

H

X

H

L

H H

H

L

L

H

H

L

L

H

12

H

X

H

H

L

L

H

L

H

L

L

L

H

H

13

H

X

H

H

L

H

H

H

L

L

H

L

H

H

14

H

X

H

H

H

L

H

L

L

L

H

H

H

H

15

H

X

H

H

H H

H

L

L

L

L

L

L

L

BI

X

X

X

X

X

X

L

L

L

L

L

L

L

L

2

RBI

H

L

L

L

L

L

L

L

L

L

L

L

L

L

3

LT

L

X

X

X

X

X

H

H

H

H

H

H

H

H

4


SN54/74LS48 GUARANTEED OPERATING RANGES Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54 74

4.5 4.75

5.0 5.0

5.5 5.25

V

TA

Operating Ambient Temperature Range

54 74

– 55 0

25 25

125 70

°C

IOH

Output Current — High

a to g

54, 74

– 100

µA

IOH


BI / RBO

54, 74

– 50

µA

IOL

Output Current — Low

a to g

54 74

2.0 6.0

mA

IOL


BI / RBO BI / RBO

54 74

1.6 3.2

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol

P Parameter

Min

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

24 2.4

IO

Output Current a to g

– 1.3

VOL

Output LOW Voltage a to g

VOL

Output p LOW Voltage g BI / RBO

IIH

Input p HIGH Current (Except BI / RBO)

IIL

Typ

Max

U i Unit

T Test C Conditions di i

V

Guaranteed Input HIGH Voltage for All Inputs

V

Guaranteed Input p LOW Voltage g for All Inputs

V

VCC = MIN, IIN = – 18 mA

42 4.2

µA

VCC = MIN,, IOH = – 50 µA, µ , VIN = VIH or U.L. per Truth Table

– 2.0

mA

VCC = MIN, VO = 0.85 V Input Conditioner as for VOH

2.0 54

0.7

74

0.8 – 1.5

54, 74

0.4

V

IOL = 2.0 mA

74

0.5

V

IOL = 6.0 mA

54, 74

0.4

V

IOL = 1.6 mA

74

0.5

V

IOL = 3.2 mA

VCC = MIN,, VIH = 2.0 V VIL = VIL MAX VCC = MAX,, VIH = 2.0 V VIL = VIL MAX

20

µA

VCC = MAX, VIN = 2.7 V

0.1

mA


Input LOW Current (Except BI / RBO)

– 0.4

mA


IIL

Input LOW Current BI / RBO

– 1.2

mA


ICC

Power Supply Current

38

mA

VCC = MAX

IOS

Short Circuit Current BI / RBO (Note 1)

–2.0

mA

VCC = MAX

25 – 0.3

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C) Limits S b l Symbol

Max

U i Unit

tPHL

Propagation Delay Time, HIGH-to-LOW Level Output from A Input

P Parameter

100

ns

tPLH

Propagation Delay Time, LOW-to-HIGH Level Output from A Input

100

ns

tPHL

Propagation Delay Time, HIGH-to-LOW Level Output from RBI Input

100

ns

tPLH

Propagation Delay Time, LOW-to-HIGH Level Output from RBI Input

100

ns

Min

Typ


pF RL = 4.0 4 0 kΩ CL = 15 pF,

pF RL = 6.0 6 0 kΩ CL = 15 pF,


















DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. The data on the J

and K inputs is allowed to change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated. A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs.


TL/F/6372 – 1

Order Number DM54LS73AJ, DM54LS73AW, DM74LS73AM or DM74LS73AN See NS Package Number J14A, M14A, N14A or W14B

Function Table Inputs

Outputs

CLR

CLK

J

K

Q

Q

L H H H H H

X

v v v v

X L H L H X

X L L H H X

L Q0 H L

H Q0 L H

H

Toggle Q0

Q0


v e Negative going edge of pulse. Q0 e The output logic level before the indicated input conditions were established. Toggle e Each output changes to the complement of its previous level on each falling edge of the clock pulse.


TL/F/6372


DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

June 1989


If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS DM74LS 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range


DM54LS73A

Parameter

VCC

Supply Voltage

VIH


VIL


IOH

DM74LS73A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.7

0.8

V


b 0.4

b 0.4

mA

IOL


4

8

mA

fCLK

Clock Frequency (Note 2)

0

30

0

30

MHz

fCLK


0

25

0

25

MHz

tW

Pulse Width (Note 2)

Clock High

20

20

Preset Low

25

25

Clear Low

25

25

Clock High

25

25

Preset Low

30

30

Clear Low

30

30

tW


ns

ns

tSU

Setup Time (Notes 1 and 2)

20v

20v

ns

tSU


25v

25v

ns

tH

Hold Time (Notes 1 and 2)

0v

0v

ns

tH

Hold Time (Notes 1 and 3)

5v

5v

TA


b 55

Note 1: The symbol (

125

v) indicates the falling edge of the clock pulse is used for reference.

Note 2: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 3: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V.

2

0

ns 70

§C


Parameter

Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH


VCC e Min, IOH e Max VIL e Max, VIH e Min


VCC e Min, IOL e Max VIL e Max, VIH e Min

DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

VCC e Max VI e 7V

J, K

VOL

II

IIH

IIL

IOS

ICC




VCC e Max VI e 2.7V

VCC e Max VI e 0.4V


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

V

V

0.1

Clear

0.3

Clock

0.4

J, K

20

Clear

60

Clock

80

J, K

b 0.4

Clear

b 0.8

Clock

b 0.8

DM54

b 20

b 100

DM74

b 20

b 100

4

6

mA

mA

mA

mA mA

Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol

Parameter

RL e 2 kX

From (Input) To (Output)

CL e 15 pF Min

Max

CL e 50 pF Min

Units

Max

fMAX

Maximum Clock Frequency

tPHL


Clear to Q

20

28

ns

tPLH


Clear to Q

20

24

ns

tPLH


Clock to Q or Q

20

24

ns

tPHL


Clock to Q or Q

20

28

ns

30

25

MHz

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with from the outputs, where shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where VO e 2.25V and 2.125V for DM54 and DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment. Note 3: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock is grounded.

3


14-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS73AJ NS Package Number J14A

4


14-Lead Small Outline Molded Package (M) Order Number DM74LS73AM NS Package Number M14A

14-Lead Molded Dual-In-Line Package (N) Order Number DM74LS73AN NS Package Number N14A

5

DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs


14-Lead Ceramic Flat Package (W) Order Number DM54LS73AW NS Package Number W14B







54LS74/DM54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not

violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Features Y



TL/F/6373 – 1

Order Number 54LS74DMQB, 54LS74FMQB, 54LS74LMQB, DM54LS74AJ, DM54LS74AW, DM74LS74AM or DM74LS74AN See NS Package Number E20A, J14A, M14A, N14A or W14B


Outputs

PR

CLR

CLK

D

Q

Q

L H L H H H

H L L H H H

X X X

X X X H L X

H L H* H L Q0

L H H* L H Q0

u u L

H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level

u e Positive-going Transition * e This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs return to their inactive (high) level. Q0 e The output logic level of Q before the indicated input conditions were established.


TL/F/6373


54LS74/DM54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

June 1989



b 65§ C to a 150§ C

Recommended Operating Conditions Symbol VCC

Supply Voltage

VIH


VIL


IOH


IOL


fCLK


fCLK tW

tW

DM54LS74A

Parameter

DM74LS74A

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V

0.7

0.8

V

b 0.4

mA

4 25


0

20


18


V

b 0.4

0

Clock High

Units

Min

8

mA

0

25

MHz

0

20

MHz

18

Preset Low

15

15

Clear Low

15

15

Clock High

25

25

Preset Low

20

20

Clear Low

20

20

ns

ns

tSU


20u

20u

ns

tSU


25u

25u

ns

tH

Hold Time (Note 1 and 4)

0u

TA


b 55


0u 125

u) indicates the rising edge of the clock pulse is used for reference.

Note 2: CL e 15 pF, RL e 2 kX, TA e 25§ C, and VCC e 5V. Note 3: CL e 50 pF, RL e 2 kX, TA e 25§ C, and VCC e 5V. Note 4: TA e 25§ C and VCC e 5V.

2

0

ns 70

§C


Parameter

Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH





DM54

0.25

DM74

0.35

0.5


DM74

0.25

0.4

VCC e Max VI e 7V

Data

VOL

II

IIH



VCC e Max VI e 2.7V

V 0.4

0.1

Clock

0.1

Preset

0.2

Clear

0.2

Data

20

Clock

20

Clear

40

Preset IIL


VCC e Max VI e 0.4V

ICC


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

mA

mA

40

Data

b 0.4

Clock

b 0.4

Preset

b 0.8

Clear IOS

V

mA

b 0.8

DM54

b 20

b 100

DM74

b 20

b 100

4

8

mA mA

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with from the outputs, where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO e 2.25V and 2.125V for DM54 and DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment. Note 3: With all outputs open, ICC is measured with CLOCK grounded after setting the Q and Q outputs high in turn.


Parameter

RL e 2 kX


CL e 15 pF Min

Max

25

CL e 50 pF Min

Units

Max

fMAX


tPLH


Clock to Q or Q

25

35

ns

tPHL


Clock to Q or Q

30

35

ns

tPLH


Preset to Q

25

35

ns

tPHL


Preset to Q

30

35

ns

tPLH


Clear to Q

25

35

ns

tPHL


Clear to Q

30

35

ns

3

20

MHz



14-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS74DMQB or DM54LS74AJ NS Package Number J14A

4




5

54LS74/DM54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs


14-Lead Ceramic Flat Package (W) Order Number 54LS74FMQB or DM54LS74AW NS Package Number W14B













54LS83A/DM54LS83A/DM74LS83A 4-Bit Binary Adders with Fast Carry General Description

Features

These full adders perform the addition of two 4-bit binary numbers. The sum (R) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial lookahead performance at the economy and reduced package count of a ripple-carry implementation. The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.

Y Y

Y

Y Y

Full-carry look-ahead across the four bits Systems achieve partial look-ahead performance with the economy of ripple carry Typical add times Two 8-bit words 25 ns Two 16-bit words 45 ns Typical power dissipation per 4-bit adder 95 mW Alternate Military/Aerospace device (54LS83A) is available. a National Semiconductor Sales Office/ Distributor for specifications.


TL/F/6378 – 1

Order Number 54LS83QB, 54LS83AFMQB, DM54LS83AJ, DM54LS83AW, DM74LS83AWM or DM74LS83AN See NS Package Number J16A, M16B, N16E or W16A


TL/F/6378


54LS83A/DM54LS83A/DM74LS83A 4-Bit Binary Adders with Fast Carry

May 1989



b 65§ C to a 150§ C


DM54LS83A

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS83A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

4 b 55

125

0


Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH



DM54

2.5

3.4

DM74

2.7

3.4



DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4


VCC e Max VI e 7V

A or B

0.2

C0

0.1


VCC e Max VI e 2.7V

A or B

40

C0

20


VCC e Max VI e 0.4V

A or B

b 0.8

C0

b 0.4


VCC e Max (Note 2)

DM54

b 20

b 100

DM74

b 20

b 100

ICC1

Supply Current

VCC e Max (Note 3)

19

34

mA

ICC2

Supply Current

VCC e Max (Note 4)

22

39

mA

VOL

II

IIH

IIL

IOS

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC1 is measured with all outputs open, all B inputs low and all other inputs at 4.5V, or all inputs at 4.5V. Note 4: ICC2 is measured with all outputs open and all inputs grounded.

2

V

V

mA

mA

mA

mA


Parameter

RL e 2 kX


CL e 15 pF Min

Max

CL e 50 pF Min

Units

Max

tPLH


C0 to R1 or R2

24

28

ns

tPHL


C0 to R1 or R2

24

30

ns

tPLH


C0 to R3

24

28

ns

tPHL


C0 to R3

24

30

ns

tPLH


C0 to R4

24

28

ns

tPHL


C0 to R4

24

30

ns

tPLH


Ai, Bi to Ri

24

28

ns

tPHL


Ai, Bi to Ri

24

30

ns

tPLH


C0 to C4

17

24

ns

tPHL


C0 to C4

17

25

ns

tPLH


Ai, Bi to C4

17

24

ns

tPHL


Ai, Bi to C4

17

26

ns

Truth Table

TL/F/6378 – 3

H e High Level, L e Low Level

Note: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs R1 and R2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs R3, R4, and C4.

3

Logic Diagram

TL/F/6378 – 2

4

5


16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS83QB or DM54LS83AJ NS Package Number J16A

6


16-Lead Wide Small Outline Molded Package (M) Order Number DM74LS83AWM NS Package Number M16B

16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS83AN NS Package Number N16E

7

54LS83A/DM54LS83A/DM74LS83A 4-Bit Binary Adders with Fast Carry


16-Lead Ceramic Flat Package (W) Order Number 54LS83AFMQB or DM54LS83AW NS Package Number W16A







54LS85/DM54LS85/DM74LS85 4-Bit Magnitude Comparators General Description have a high-level voltage applied to the A e B input. The cascading path is implemented with only a two-gate-level delay to reduce overall comparison times for long words.

These 4-bit magnitude comparators perform comparison of straight binary or BCD codes. Three fully-decoded decisions about two, 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A l B, A k B, and A e B outputs of a stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must

Features Y Y Y

Typical power dissipation 52 mW Typical delay (4-bit words) 24 ns Alternate Military/Aerospace device (54LS85) is available. a National Semiconductor Sales Office/ Distributor for specifications.


Order Number 54LS85DMQB, 54LS85FMQB, 54LS85LMQB, DM54LS85J, DM54LS85W, DM74LS85M or DM74LS85N See NS Package Number E20A, J16A, M16A, N16E or W16A

TL/F/6379 – 1

Function Table Comparing Inputs

Cascading Inputs

Outputs

A3, B3

A2, B2

A1, B1

A0, B0

AlB

AkB

AeB

AlB

AkB

AeB

A3 l B3 A3 k B3

X X

X X X X

X X X X X X

X X X X X X X X H L L X H L

X X X X X X X X L H L X H L

X X X X X X X X L L H H L L

H L H L H L H L H L L L L H

L H L H L H L H L H L L L H

L L L L L L L L L L H H L L

A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3

e e e e e e e e e e e e

B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3

A2 l B2 A2 k B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2

A1 l B1 A1 k B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1

A0 l B0 A0 k B0 A0 e B0 A0 e B0 A0 e B0 A0 e B0 A0 e B0 A0 e B0

H e High Level, L e Low Level, X e Don’t Care C1995 National Semiconductor Corporation

TL/F/6379


54LS85/DM54LS85/DM74LS85 4-Bit Magnitude Comparators

June 1989



b 65§ C to a 150§ C


DM54LS85

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS85

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

2

2

V

4 b 55

125

0

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH

VOL

II

IIH

IIL

IOS

ICC

Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

Input Clamp Voltage




DM54

2.5

3.4

DM74

2.7

3.4



DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

VCC e Max VI e 7V

AkB




VCC e Max VI e 2.7V

VCC e Max VI e 0.4V


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

0.1

Others

0.3

AkB

20

AlB

20

Others

60

AkB

b 0.4

AlB

b 0.4

Others

b 1.2

DM54

b 20

b 100

DM74

b 20

b 100

10

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs open, A e B grounded and all other inputs at 4.5V.

V

0.1

AlB


2

V

20

mA

mA

mA

mA mA


Parameter

From Input

To Output

Number of Gate Levels

RL e 2 kX CL e 15 pF Min

tPLH

tPHL

Propagation Delay Time Low-to-High Level Output

Propagation Delay Time High-to-Low Level Output

Any A or B Data Input

Any A or B Data Input

Max

CL e 50 pF Min

Units

Max

A k B, AlB

3

36

42

AeB

4

40

40

A k B, AlB

3

30

40

AeB

4

30

40

ns

ns

tPLH


AkB or A e B

AlB

1

22

26

ns

tPHL


AkB or A e B

AlB

1

17

26

ns

tPLH


A eB

AeB

2

20

25

ns

tPHL


AeB

AeB

2

17

26

ns

tPLH


AlB or A e B

AkB

1

22

26

ns

tPHL


AlB or A e B

AkB

1

17

26

ns

3

Logic Diagram

TL/F/6379 – 2

4

5


Chip Carrier Package (E) Order Number 54LS85LMQB NS Package Number E20A


6



16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS85N NS Package Number N16E

7

54LS85/DM54LS85/DM74LS85 4-Bit Magnitude Comparators


16-Lead Ceramic Flat Package (W) Order Number 54LS85FMQB or DM54LS85W NS Package Number W16A







DM54LS86/DM74LS86 Quad 2-Input Exclusive-OR Gates General Description This device contains four independent gates each of which performs the logic exclusive-OR function.


TL/F/6380 – 1

Order Number DM54LS86J, DM54LS86W, DM74LS86M or DM74LS86N See NS Package Number J14A, M14A, N14A or W14B

Function Table YeA

Z

B e AB a AB

Inputs

Output

A

B

Y

L L H H

L H L H

L H H L



TL/F/6380


DM54LS86/DM74LS86 Quad 2-Input Exclusive-OR Gates

June 1989




DM54LS86

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS86

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

2

2

V

4 b 55

125

0

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL

II

Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

Input Clamp Voltage



VCC e Min, IOH e Max, VIL e Max, VIH e Min


VCC e Min, IOL e Max, VIL e Max, VIH e Min

DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

DM54

2.5

3.4

DM74

2.7

3.4

V

V


VCC e Max, VI e 7V

IIH


IIL



IOS


VCC e Max (Note 2)

ICCH


VCC e Max (Note 3)

6.1

10

mA

ICCL


VCC e Max (Note 4)

9

15

mA

0.2

b 100

DM74

b 20

b 100

Note 3: ICCH is measured with all outputs open, one input at each gate at 4.5V, and the other inputs grounded.

2

mA mA

b 20

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICCL is measured with all outputs open and all inputs grounded.

40 b 0.6

DM54


mA

mA


Parameter

CL e 15 pF

Conditions

Min tPLH


tPHL


tPLH


tPHL


Max

CL e 50 pF Min

Units

Max

Other Input Low

18

23

ns

17

21

ns

Other Input High

10

15

ns

12

15

ns

3


14-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS86J NS Package Number J14A

4




5

DM54LS86/DM74LS86 Quad 2-Input Exclusive-OR Gates









DM74LS90/DM74LS93 Decade and Binary Counters General Description Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the ’LS90 and divideby-eight for the ’LS93. All of these counters have a gated zero reset and the LS90 also has gated set-to-nine inputs for use in BCD nine’s complement applications. To use their maximum count length (decade or four bit binary), the B input is connected to the QA output. The input

count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the ’LS90 counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.

Features Y Y

Typical power dissipation 45 mW Count frequency 42 MHz

Connection Diagrams (Dual-In-Line Packages)

TL/F/6381 – 1

Order Number DM74LS90M or DM74LS90N See NS Package Number M14A or N14A


TL/F/6381

TL/F/6381 – 2



DM74LS90/DM74LS93 Decade and Binary Counters

June 1989


If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage (Reset) Input Voltage (A or B) Operating Free Air Temperature Range DM74LS

7V 7V 5.5V 0§ C to a 70§ C b 65§ C to a 150§ C

Storage Temperature Range

Recommended Operating Conditions Symbol VCC

Supply Voltage

VIH


VIL


IOH


IOL


fCLK


fCLK tW

tW

DM74LS90

Parameter

Clock Frequency (Note 2) Pulse Width (Note 1)


Units

Min

Nom

Max

4.75

5

5.25

V

2

V 0.8

V

b 0.4

mA

8

mA

A to QA

0

32

B to QB

0

16

A to QA

0

20

B to QB

0

10

A

15

B

30

Reset

15

A

25

B

50

Reset

25

tREL

Reset Release Time (Note 1)

25

tREL


35

TA


0

MHz MHz

ns

ns ns ns

§C

70


’LS90 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol

Parameter

Conditions

VI

Input Clamp Voltage


VOH



VOL


VCC e Min, IOL e Max VIL e Max, VIH e Min (Note 4)

Min

2.7


VCC e Max, VI e 7V VCC e Max VI e 5.5V

2

Max

Units

b 1.5

V

3.4

0.35

IOL e 4 mA, VCC e Min II

Typ (Note 1)

0.25

V

0.5

V

0.4

Reset

0.1

A

0.2

B

0.4

mA

’LS90 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) (Continued) Symbol IIH

IIL

Parameter

Conditions





IOS


VCC e Max (Note 2)

ICC

Supply Current

VCC e Max (Note 3)

Min

Typ (Note 1)

Max

Reset

Units

20

A

40

B

80

Reset

b 0.4

A

b 2.4

B

b 3.2 b 20

mA

mA

b 100

mA

15

mA

9

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded. Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.

’LS90 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol

Parameter

RL e 2 kX


CL e 15 pF Min

fMAX


Max

CL e 50 pF Min

A to QA

32

20

B to QB

16

10

Units

Max MHz

tPLH


A to QA

16

20

ns

tPHL


A to QA

18

24

ns

tPLH


A to QD

48

52

ns

tPHL


A to QD

50

60

ns

tPLH


B to QB

16

23

ns

tPHL


B to QB

21

30

ns

tPLH


B to QC

32

37

ns

tPHL


B to QC

35

44

ns

tPLH


B to QD

32

36

ns

tPHL


B to QD

35

44

ns

tPLH


SET-9 to QA, QD

30

35

ns

tPHL


SET-9 to QB, QC

40

48

ns

tPHL


SET-0 to Any Q

40

52

ns

3


DM74LS93

Parameter

VCC

Supply Voltage

VIH


VIL


Units

Min

Nom

Max

4.75

5

5.25

V

2

V 0.8

V mA mA

IOH


b 0.4

IOL


8

fCLK


fCLK


tW


tW


A to QA

0

32

B to QB

0

16

A to QA

0

20

B to QB

0

10

A

15

B

30

Reset

15

A

25

B

50

Reset

25

tREL


25

tREL


35

TA


0

MHz

ns

ns

ns ns 70

§C



Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH



VOL


VCC e Min, IOL e Max VIL e Max, VIH e Min (Note 4)


VCC e Max, VI e 7V

Reset

0.1

VCC e Max VI e 5.5V

A

0.2

B

0.4

VCC e Max VI e 2.7V

Reset

20

2.7

0.35

IOL e 4 mA, VCC e Min II

IIH


4

3.4

0.25

V

0.5

V

0.4

A

40

B

80

mA

mA

’LS93 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) (Continued) Symbol IIL

Parameter

Conditions



IOS


VCC e Max (Note 2)

ICC

Supply Current

VCC e Max (Note 3)

Min

Typ (Note 1)

Max

Reset

b 0.4

A

b 2.4

B

b 1.6 b 20

Units

mA

b 100

mA

15

mA

9

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded. Note 4: QA outputs are tested at IOL e max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.

’LS93 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)

Symbol

Parameter

RL e 2 kX


CL e 15 pF Min

fMAX


Max

CL e 50 pF Min

A to QA

32

20

B to QB

16

10

Units

Max MHz

tPLH


A to QA

16

20

ns

tPHL


A to QA

18

24

ns

tPLH


A to QD

70

85

ns

tPHL


A to QD

70

90

ns

tPLH


B to QB

16

23

ns

tPHL


B to QB

21

30

ns

tPLH


B to QC

32

37

ns

tPHL


B to QC

35

44

ns

tPLH


B to QD

51

60

ns

tPHL


B to QD

51

70

ns

tPHL


SET-0 to Any Q

40

52

ns

5

Function Tables LS90 BCD Count Sequence (See Note A)

LS90 Bi-Quinary (5-2) (See Note B)

Output

Count 0 1 2 3 4 5 6 7 8 9

QC

QB

QA

L L L L L L L L H H

L L L L H H H H L L

L L H H L L H H L L

L H L H L H L H L H

0 1 2 3 4 5 6 7 8 9

LS93 Count Sequence (See Note C)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

QA

QD

QC

QB

L L L L L H H H H H

L L L L H L L L L H

L L H H L L L H H L

L H L H L L H L H L

LS90 Reset/Count Truth Table Reset Inputs

Output

Count

Output

Count

QD

QD

QC

QB

QA

L L L L L L L L H H H H H H H H

L L L L H H H H L L L L H H H H

L L H H L L H H L L H H L L H H

L H L H L H L H L H L H L H L H

Output

R0(1)

R0(2)

R9(1)

R9(2)

QD

H H X X L L X

H H X L X X L

L X H X L X L

X L H L X L X

L L H

QC

QB

L L L L L L COUNT COUNT COUNT COUNT

QA L L H

LS93 Reset/Count Truth Table Reset Inputs

Output

R0(1)

R0(2)

QD

H L X

H X L

L

Note A: Output QA is connected to input B for BCD count. Note B: Output QD is connected to input A for bi-quinary count. Note C: Output QA is connected to input B. Note D: H e High Level, L e Low Level, X e Don’t Care.

6

QC

QB

L L COUNT COUNT

QA L

Logic Diagrams LS90

LS93

TL/F/6381 – 4

TL/F/6381 – 3

The J and K inputs shown without connection are for reference only and are functionally at a high level.

7

8


14-Lead Small Outline Molded Package (M) Order Number DM74LS90M or DM74LS93M NS Package Number M14A

9

DM74LS90/DM74LS93 Decade and Binary Counters


14-Lead Molded Dual-In-Line Package (N) Order Number DM74LS90N or DM74LS93N NS Package Number N14A



















DM74LS123 Dual Retriggerable One-Shot with Clear and Complementary Outputs Y

General Description

Y

The DM74LS123 is a dual retriggerable monostable multivibrator capable of generating output pulses from a few nanoseconds to extremely long duration up to 100% duty cycle. Each device has three inputs permitting the choice of either leading edge or trailing edge triggering. Pin (A) is an activelow transition trigger input and pin (B) is an active-high transition trigger input. The clear (CLR) input terminates the output pulse at a predetermined time independent of the timing components. The clear input also serves as a trigger input when it is pulsed with a low level pulse transition (ß). To obtain the best trouble free operation from this device please read the operating rules as well as the NSC one-shot application notes carefully and observe recommendations.

Y Y

Compensated for VCC and temperature variations Triggerable from CLEAR input DTL, TTL compatible Input clamp diodes

Functional Description The basic output pulse width is determined by selection of an external resistor (RX) and capacitor (CX). Once triggered, the basic pulse width may be extended by retriggering the gated active-low transition or active-high transition inputs or be reduced by use of the active-low or CLEAR input. Retriggering to 100% duty cycle is possible by application of an input pulse train whose cycle time is shorter than the output cycle time such that a continuous ‘‘HIGH’’ logic state is maintained at the ‘‘Q’’ output.

Features Y

Y

DC triggered from active-high transition or active-low transition inputs Retriggerable to 100% duty cycle

Connection Diagram

Function Table

Dual-In-Line Package

Inputs

Outputs

CLEAR

A

B

Q

Q

L X X H H

X H X L

X X L

v

u

L

L L L É É É

H H H ß ß ß

u H H

H e High Logic Level L e Low Logic Level X e Can Be Either Low or High

u e Positive Going Transition v e Negative Going Transition É e A Positive Pulse ß e A Negative Pulse

TL/F/6386 – 1

Order Number DM74LS123M or DM74LS123N See NS Package Number M16A or N16E


TL/F/6386


DM74LS123 Dual Retriggerable One-Shot with Clear and Complementary Outputs

March 1991


If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature

7V 7V 0§ C to a 70§ C b 65§ C to a 150§ C


Parameter

Min

Nom

Max

Units

4.75

5

5.25

V

0.8

V


b 0.4

mA


8

mA

VCC

Supply Voltage

VIH


VIL


IOH IOL tW


2

A or B High

REXT

External Timing Resistor

CEXT

External Timing Capacitance

CWIRE

Wiring Capacitance at REXT/CEXT Terminal

TA


Electrical Characteristics Symbol

Parameter

V

40

A or B Low

40

Clear Low

40

ns

5

260 No Restriction

0

kX mF

50

pF

70

§C

over recommended operating free air temperature range (unless otherwise noted) Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage

VOH


VCC e Min, II e b18 mA VCC e Min, IOH e Max VIL e Max, VIH e Min

VOL



0.35

0.5


0.25

0.4

2.7

3.4

V

V

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.4

mA

IOS


VCC e Max (Note 2)

b 100

mA

Supply Current

VCC e Max (Notes 3,4 and 5)

20

mA

ICC

0.1

b 20

12

mA

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: Quiescent ICC is measured (after clearing) with 2.4V applied to all clear and A inputs, B inputs grounded, all outputs open, CEXT e 0.02 mF, and REXT e 25 kX. Note 4: ICC is measured in the triggered state with 2.4V applied to all clear and B inputs, A inputs grounded, all outputs open, CEXT e 0.02 mF, and REXT e 25 kX. Note 5: With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V is applied to the clock. Note 6: TA e 25§ C and VCC e 5V.

2

Switching Characteristics at VCC e 5V and TA e 25§ C RL e 2 kX Symbol

Parameters


CL e 15pF CEXT e 0 pF, REXT e 5 kX Min

Max

CL e 15pF CEXT e 1000 pF, REXT e 10 KX Min

Units

Max

tPLH


A to Q

33

ns

tPLH


B to Q

44

ns

tPHL


A to Q

45

ns

tPHL


B to Q

56

ns

tPLH


Clear to Q

45

ns

tPHL


Clear to Q

27

ns

tWQ(Min)

Minimum Width of Pulse at Output Q

A or B to Q

200

ns

tW(out)

Output Pulse Width

A or B to Q

4

5

ms

Operating Rules 3. For CX ll 1000 pF the output pulse width (TW) is defined as follows: TW e KRX CX where [RX is in kX] [CX is in pF] [TW is in ns] K & 0.37

1. An external resistor (RX) and an external capacitor (CX) are required for proper operation. The value of CX may vary from 0 to any necessary value. For small time constants high-grade mica, glass, polypropylene, polycarbonate, or polystyrene material capacitors may be used. For large time constants use tantalum or special aluminum capacitors. If the timing capacitors have leakages approaching 100 nA or if stray capacitance from either terminal to ground is greater than 50 pF the timing equations may not represent the pulse width the device generates. 2. When an electrolytic capacitor is used for CX a switching diode is often required for standard TTL one-shots to prevent high inverse leakage current. This switching diode is not needed for the ’LS123 one-shot and should not be used. In general the use of the switching diode is not recommended with retriggerable operation. Furthermore, if a polarized timing capacitor is used on the ’LS123 the negative terminal of the capacitor should be connected to the ‘‘CEXT’’ pin of the device (Figure 1 ).

4. The multiplicative factor K is plotted as a function of CX below for design considerations:

TL/F/6386 – 2

FIGURE 2

TL/F/6386 – 8

FIGURE 1

3

Operating Rules (Continued) 5. For CX k 1000 pF see Figure 3 for TW vs CX family curves with RX as a parameter:

TL/F/6386 – 7

FIGURE 7 9. Under any operating condition CX and RX must be kept as close to the one-shot device pins as possible to minimize stray capacitance, to reduce noise pick-up, and to reduce I-R and Ldi/dt voltage developed along their connecting paths. If the lead length from CX to pins (6) and (7) or pins (14) and (15) is greater than 3 cm, for example, the output pulse width might be quite different from values predicted from the appropriate equations. A non-inductive and low capacitive path is necessary to ensure complete discharge of CX in each cycle of its operation so that the output pulse width will be accurate. 10. The CEXT pins of this device are internally connected to the internal ground. For optimum system performance they should be hard wired to the system’s return ground plane. 11. VCC and ground wiring should conform to good high-frequency standards and practices so that switching transients on the VCC and ground return leads do not cause interaction between one-shots. A 0.01 mF to 0.10 mF by capacitor (disk ceramic or monolithic type) from VCC to ground is necessary on each device. Furthermore, the by capacitor should be located as close to the VCC-pin as space permits.

TL/F/6386 – 3

FIGURE 3 6. To obtain variable pulse widths by remote trimming, the following circuit is recommended:

TL/F/6386 – 4

FIGURE 4 Note: ‘‘Rremote’’ should be as close to the device pin as possible.

7. The retriggerable pulse width is calculated as shown below: T e TW a tPLH e K c RX c CX a tPLH The retriggered pulse width is equal to the pulse width plus a delay time period (Figure 5).

For further detailed device characteristics and output performance please refer to the NSC one-shot application note AN-372.

TL/F/6386 – 5

FIGURE 5 8. Output pulse width variation versus VCC and temperatures: Figure 6 depicts the relationship between pulse width variation versus VCC, and Figure 7 depicts pulse width variation versus temperatures.

TL/F/6386 – 6

FIGURE 6

4


16-Lead Small Outline Molded Package Order Number DM74LS123M NS Package Number M16A

5

DM74LS123 Dual Retriggerable One-Shot with Clear and Complementary Outputs









54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATEÉ Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility

that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.

Features Y



TL/F/6387 – 1

Order Number 54LS125QB, 54LS125AFMQB, 54LS125ALMQB, DM54LS125AJ, DM54LS125AW, DM74LS125AM or DM74LS125AN See NS Package Number E20A, J14A, M14A, N14A or W14B

Function Table YeA Inputs

Output

A

C

Y

L H X

L L H

L H Hi-Z

H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level Hi-Z e TRI-STATE (Outputs are disabled)

TRI-STATEÉ is a ed trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation

TL/F/6387


54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers

June 1989



b 65§ C to a 150§ C


DM54LS125A

Parameter

DM74LS125A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

VCC

Supply Voltage

VIH


VIL


0.7

0.8

V

IOH


b1

b 2.6

mA

IOL


24

mA

TA


70

§C

2

2

V

12 b 55

125

V

0


Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH



VOL



DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

2.4

3.4

V

V

II


VCC e Max, VI e 7V

0.1

mA

IIH



20

mA

IIL



b 0.4

mA

IOZH

Off-State Output Current with High Level Output Voltage Applied

VCC e Max, VO e 2.4V VIH e Min, VIL e Max

20

mA

Off-State Output Current with Low Level Output Voltage Applied


b 20

mA


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

IOZL

IOS ICC

DM54

b 20

b 100

DM74

b 20

b 100

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with the data control (C) inputs at 4.5V and the data inputs grounded.

2

11

20

mA mA

Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) RL e 667X Symbol

Parameter

CL e 50 pF Min

Max

CL e 150 pF Min

Units

Max

tPLH


15

21

ns

tPHL


18

22

ns

tPZH

Output Enable Time to High Level Output

25

35

ns

tPZL

Output Enable Time to Low Level Output

25

40

ns

tPHZ

Output Disable Time from High Level Output (Note 1)

20

ns

tPLZ

Output Disable Time from Low Level Output (Note 1)

20

ns

Note 1: CL e 5pF.

3


Ceramic Leadless Chip Carrier Package (E) Order Number 54LS125ALMQB NS Package Number E20A

14-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS125QB or DM54LS125AJ NS Package Number J14A

4




5

54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers


14-Lead Ceramic Flat Package (W) Order Number 54LS125AFMQB or DM54LS125AW NS Package Number W14B







DM54LS132/DM74LS132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing, jitter free output.


TL/F/6389 – 1

Order Number DM54LS132J, DM54LS132W, DM74LS132M or DM74LS132N See NS Package Number J14A, M14A, N14A or W14B


Output

A

B

Y

L L H H

L H L H

H H H L



TL/F/6389


DM54LS132/DM74LS132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs

June 1989



Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS DM74LS 0§ C to a 70§ C Storage Temperature Range

b 65§ C to a 150§ C


DM54LS132

Parameter

DM74LS132

Units

Min

Nom

Max

Min

Nom

Max

VCC

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VT a

Positive-Going Input Threshold Voltage (Note 1)

1.4

1.6

1.9

1.4

1.6

1.9

V

VTb

Negative-Going Input Threshold Voltage (Note 1)

0.5

0.8

1

0.5

0.8

1

V

HYS

Input Hysteresis (Note 1)

0.4

0.8

0.4

0.8

IOH


b 0.4

mA

IOL


8

mA

TA


70

§C

b 0.4

4 b 55

125

0

V


Parameter

Conditions

Min

Typ (Note 2)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH


VCC e Min, IOH e Max, VI e VTb Min

DM54

2.5

3.4

DM74

2.7

3.4


VCC e Min, IOL e Max,

DM54

0.25

0.4

VI e VT a Max

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V

V

IT a

Input Current at Positive-Going Threshold

VCC e 5V, VI e VT a

IT b

Input Current at Negative-Going Threshold

VCC e 5V, VI e VTb

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.4

mA

IOS


VCC e Max (Note 3)

ICCH


VCC e Max

5.9

11

mA

ICCL


VCC e Max

8.2

14

mA

mA

b 0.18

mA 0.1

DM54

b 20

b 100

DM74

b 20

b 100

Note 1: VCC e 5V Note 2: All typicals are at VCC e 5V, TA e 25§ C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

2

b 0.14

mA

mA

Switching Characteristics at VCC 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) RL e 2 kX Symbol

Parameter

CL e 15 pF

CL e 50 pF

Units

Min

Max

Min

Max

tPLH


5

22

8

25

ns

tPHL


5

22

10

33

ns



14-Lead Small Outline Molded Package (M) Order Number DM74LS132M NS Package Number M14A 3

DM54LS132/DM74LS132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs














54LS138/DM54LS138/DM74LS138, 54LS139/DM54LS139/DM74LS139 Decoders/Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The LS139 comprises two separate two-line-to-four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance

Schottky diodes to suppress line-ringing and simplify system design.

Features Y

Y

Y

Y Y

Y

Y

Designed specifically for high speed: Memory decoders Data transmission systems LS138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception LS139 contains two fully independent 2-to-4-line decoders/demultiplexers Schottky clamped for high performance Typical propagation delay (3 levels of logic) LS138 21 ns LS139 21 ns Typical power dissipation LS138 32 mW LS139 34 mW Alternate Military/Aerospace devices (54LS138, 54LS139) are available. a National Semiconductor Sales Office/Distributor for specifications.

Connection Diagrams Dual-in-Line Package

Dual-in-Line Package

TL/F/6391 – 1

Order Number 54LS138DMQB, 54LS138FMQB, 54LS138LMQB, DM54LS138J, DM54LS138W, DM74LS138M or DM74LS138N See NS Package Number E20A, J16A, M16A, N16E or W16A C1995 National Semiconductor Corporation

TL/F/6391

TL/F/6391 – 2

Order Number 54LS139DMQB, 54LS139FMQB, 54LS139LMQB, DM54LS139J, DM54LS139W, DM74LS139M or DM74LS139N See NS Package Number E20A, J16A, M16A, N16E or W16A RRD-B30M105/Printed in U. S. A.

54LS138/DM54LS138/DM74LS138, 54LS139/DM54LS139/DM74LS139 Decoders/Demultiplexers

June 1989



b 65§ C to a 150§ C


DM54LS138

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS138

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V

0.7

0.8

V

b 0.4

b 0.4

mA

4 b 55

V

125

0

8

mA

70

§C

Max

Units

b 1.5

V


Parameter

Conditions

Min

Typ (Note 1)

VI

Input Clamp Voltage


VOH



DM54

2.5

3.4

DM74

2.7

3.4


VCC e Min, IOL e Max, VIL e Max, VIH e Min

DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V

V

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.36

mA

IOS


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

ICC

0.1

DM54

b 20

b 100

DM74

b 20

b 100

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs enabled and open.

2

6.3

10

mA

mA mA


Symbol

Parameter


RL e 2 kX

Levels of Delay

CL e 15 pF Min

Max

CL e 50 pF Min

Units

Max

tPLH


Select to Output

2

18

27

ns

tPHL


Select to Output

2

27

40

ns

tPLH


Select to Output

3

18

27

ns

tPHL


Select to Output

3

27

40

ns

tPLH


Enable to Output

2

18

27

ns

tPHL


Enable to Output

2

24

40

ns

tPLH


Enable to Output

3

18

27

ns

tPHL


Enable to Output

3

28

40

ns


DM54LS139

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS139

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

2

2

4 b 55

125

3

0

V


Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH



DM54

2.5

3.4

DM74

2.7

3.4



DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V

V

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.36

mA

IOS


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

ICC

0.1

DM54

b 20

b 100

DM74

b 20

b 100

6.8

11

mA

mA mA

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs enabled and open.


Symbol


Parameter


CL e 50 pF

Max

Min

Units

Max

tPLH


Select to Output

18

27

ns

tPHL


Select to Output

27

40

ns

tPLH


Enable to Output

18

27

ns

tPHL


Enable to Output

24

40

ns

Function Tables LS138 Inputs Enable

LS139 Inputs

Outputs

Select

Enable

Outputs

Select

G1 G2* C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7

G

B

A

Y0

Y1

Y2

Y3

X L H H H H H H H H

H L L L L

X L L H H

X L H L H

H L H H H

H H L H H

H H H L H

H H H H L

H X L L L L L L L L

X X L L L L H H H H

X X L L H H L L H H

X X L H L H L H L H

H H L H H H H H H H

H H H L H H H H H H

H H H H L H H H H H

H H H H H L H H H H

H H H H H H L H H H

H H H H H H H L H H

H H H H H H H H L H

H H H H H H H H H L

H e High Level, L e Low Level, X e Don’t Care

* G2 e G2A a G2B H e High Level, L e Low Level, X e Don’t Care

4

Logic Diagrams LS138

TL/F/6391 – 3

LS139

TL/F/6391 – 4

5


Ceramic Leadless Chip Carrier Package (E) Order Number 54LS138LMQB or 54LS139LMQB NS Package Number E20A

16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS138DMQB, 54LS139DMQB, DM54LS138J or DM54LS139J NS Package Number J16A

6


16-Lead Small Outline Molded Package (M) Order Number DM74LS138M or DM74LS139M NS Packge Number M16A

16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS138N or DM74LS139N NS Package Number N16E

7

54LS138/DM54LS138/DM74LS138, 54LS139/DM54LS139/DM74LS139 Decoders/Demultiplexers


16-Lead Ceramic Flat Package (W) Order Number 54LS138FMQB, 54LS139FMQB, DM54LS138W or DM54LS139W NS Package Number W16A



















DM54LS154/DM74LS154 4-Line to 16-Line Decoders/Demultiplexers General Description

Features

Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are low. The demultiplexing function is performed by using the 4 input lines to address the output line, ing data from one of the strobe inputs with the other strobe input low. When either strobe input is high, all outputs are high. These demultiplexers are ideally suited for implementing high-performance memory decoders. All inputs are buffered and input clamping diodes are provided to minimize transmission-line effects and thereby simplify system design.

Y

Y

Y Y Y

Y

Decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs Performs the demultiplexing function by distributing data from one input line to any one of 16 outputs Input clamping diodes simplify system design High fan-out, low-impedance, totem-pole outputs Typical propagation delay 3 levels of logic 23 ns Strobe 19 ns Typical power dissipation 45 mW

Connection and Logic Diagrams Dual-In-Line Package

TL/F/6394–1

Order Number DM54LS154J, DM74LS154WM or DM74LS154N See NS Package Number J24A, M24B or N24A

TL/F/6394 – 2


TL/F/6394


DM54LS154/DM74LS154 4-Line to 16-Line Decoders/Demultiplexers

May 1989

Absolute Maximum Ratings

(Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation.



DM54LS154

Parameter

DM74LS154

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

VCC

Supply Voltage

VIH


VIL


IOH


b 0.4

b 0.4

mA

IOL


4

8

mA

TA


70

§C


2

2

b 55

125

V

0

over recommended operating free air temperature range (unless otherwise noted)

Parameter

Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH





DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

VOL

V

V

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.4

mA

IOS


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

ICC

0.1

DM54

b 20

b 100

DM74

b 20

b 100

9

14

mA

mA mA

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs open and all inputs grounded.

Switching Characteristics Symbol

Parameter

at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) From (Input) To (Output)


Max

CL e 50 pF Min

Units

Max

tPLH


Data to Output

30

35

ns

tPHL


Data to Output

30

35

ns

tPLH


Strobe to Output

20

25

ns

tPHL


Strobe to Output

25

35

ns

2


Outputs

G1

G2

D

C

B

A

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

L L L L L L L L L L L L L L L L L H H

L L L L L L L L L L L L L L L L H L H

L L L L L L L L H H H H H H H H X X X

L L L L H H H H L L L L H H H H X X X

L L H H L L H H L L H H L L H H X X X

L H L H L H L H L H L H L H L H X X X

L H H H H H H H H H H H H H H H H H H

H L H H H H H H H H H H H H H H H H H

H H L H H H H H H H H H H H H H H H H

H H H L H H H H H H H H H H H H H H H

H H H H L H H H H H H H H H H H H H H

H H H H H L H H H H H H H H H H H H H

H H H H H H L H H H H H H H H H H H H

H H H H H H H L H H H H H H H H H H H

H H H H H H H H L H H H H H H H H H H

H H H H H H H H H L H H H H H H H H H

H H H H H H H H H H L H H H H H H H H

H H H H H H H H H H H L H H H H H H H

H H H H H H H H H H H H L H H H H H H

H H H H H H H H H H H H H L H H H H H

H H H H H H H H H H H H H H L H H H H

H H H H H H H H H H H H H H H L H H H


3

4



24-Lead Wide Small Outline Molded Package (M) Order Number DM74LS154WM NS Package Number M24B

5

DM54LS154/DM74LS154 4-Line to 16-Line Decoders/Demultiplexers













54LS157/DM54LS157/DM74LS157, 54LS158/DM54LS158/DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers General Description

Features

These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. The LS157 presents true data whereas the LS158 presents inverted data to minimize propagation delay time.

Y

Applications Y Y Y

Y

Y

Y

Y

Expand any data input point Multiplex dual data buses Generate four functions of two variables (one variable is common) Source programmable counters

Buffered inputs and outputs Typical Propagation Time LS157 9 ns LS158 7 ns Typical Power Dissipation LS157 49 mW LS158 24 mW Alternate Military/Aerospace device (54LS157, 54LS158) is available. a National Semiconductor Sales Office/Distributor for specifications.

Connection Diagrams Dual-In-Line Package


TL/F/6396 – 2

TL/F/6396 – 1




Output Y

Strobe

Select

A

B

LS157

LS158

H L L L L

X L L H H

X L H X X

X X X L H

L L H L H

H H L H L



TL/F/6396


54LS157/DM54LS157/DM74LS157, 54LS158/DM54LS158/DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers

June 1989



b 65§ C to a 150§ C


DM54LS157

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS157

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V

0.7

0.8

V

b 0.4

b 0.4

mA

4 b 55

V

125

0

8

mA

70

§C

Max

Units

b 1.5

V

’LS157 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH

VOL

II

IIH

IIL

IOS

ICC

Parameter

Conditions

Min

Typ (Note 1)

Input Clamp Voltage






DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4


VCC e Max VI e 7V

S or G

0.2

A or B

0.1


VCC e Max VI e 2.7V

S or G

40

A or B

20


VCC e Max VI e 0.4V

S or G

b 0.8

A or B

b 0.4


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

DM54

2.5

3.4

DM74

2.7

3.4

DM54

b 20

b 100

DM74

b 20

b 100

9.7

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with 4.5V applied to all inputs and all outputs open.

2

V

16

V

mA

mA

mA

mA mA

’LS157 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol

RL e 2 kX


Parameter

CL e 15 pF Min

CL e 50 pF

Max

Min

Units

Max

tPLH


Data to Y

14

18

ns

tPHL


Data to Y

14

23

ns

tPLH


Strobe to Y

20

24

ns

tPHL


Strobe to Y

21

30

ns

tPLH


Select to Y

23

28

ns

tPHL


Select to Y

27

32

ns


DM54LS158

Parameter

DM74LS158

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

VCC

Supply Voltage

VIH


VIL


IOH


b 0.4

b 0.4

mA

IOL


4

8

mA

TA


70

§C

Max

Units

b 1.5

V

2

2

b 55

125

V

0


Parameter

Conditions

Min

Typ (Note 1)

VI

Input Clamp Voltage


VOH



DM54

2.5

3.4

DM74

2.7

3.4



DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4


VCC e Max VI e 7V

S or G

0.2

A or B

0.1


VCC e Max VI e 2.7V

S or G

40

A or B

20


VCC e Max VI e 0.4V

S or G

b 0.8

A or B

b 0.4


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

VOL

II IIH IIL IOS ICC

DM54

b 20

b 100

DM74

b 20

b 100

4.8

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with 4.5V applied to all inputs and all outputs open.

3

V

8

V

mA

mA

mA

mA mA


Symbol

Parameter



Max

CL e 50 pF Min

Units

Max

tPLH


Data to Y

12

18

ns

tPHL


Data to Y

12

21

ns

tPLH


Strobe to Y

17

23

ns

tPHL


Strobe to Y

18

28

ns

tPLH


Select to Y

20

24

ns

tPHL


Select to Y

24

36

ns


LS158

TL/F/6396 – 4

TL/F/6396–3

4

5


Ceramic Leadless Chip Carrier Package (E) Order Number 54LS157LMQB or 54LS158LMQB NS Package Number E20A

16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS157DMQB, 54LS158DMQB, DM54LS157J or DM54LS158J NS Package Number J16A

6




7

54LS157/DM54LS157/DM74LS157, 54LS158/DM54LS158/DM74LS158 Quad 2-Line to 1-Line Data Selectors/Multiplexers











SN54/74LS160A SN54/74LS161A SN54/74LS162A SN54/74LS163A

BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous counters. They are edge-triggered, synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and other applications. The LS160A and LS162A count modulo 10 (BCD). The LS161A and LS163A count modulo 16 (binary.) The LS160A and LS161A have an asynchronous Master Reset (Clear) input that overrides, and is independent of, the clock and all other control inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge. BCD (Modulo 10)

Binary (Modulo 16)

Asynchronous Reset

LS160A

LS161A

Synchronous Reset

LS162A

LS163A

• • • • • •

BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 620-09 16

Synchronous Counting and Loading Two Count Enable Inputs for High Speed Synchronous Expansion Terminal Count Fully Decoded Edge-Triggered Operation Typical Count Rate of 35 MHz ESD > 3500 Volts

1

16 1

CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16

TC

Q0

Q1

Q2

Q3

CET

PE

15

14

13

12

11

10

9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

2

3 P0

4 P1

5 P2

6 P3

1

ORDERING INFORMATION

Parallel Enable (Active LOW) Input Parallel Inputs Count Enable Parallel Input Count Enable Trickle Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Synchronous Reset (Active LOW) Input Parallel Outputs (Note b) Terminal Count Output (Note b)

1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 10 U.L. 10 U.L.

LOW 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 5 (2.5) U.L. 5 (2.5) U.L.

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.

Ceramic Plastic SOIC

LOGIC SYMBOL

LOADING (Note a) HIGH

PE P0 – P3 CEP CET MR SR Q0 – Q3 TC

SN54LSXXXJ SN74LSXXXN SN74LSXXXD

8 7 CEP GND

PIN NAMES

D SUFFIX SOIC CASE 751B-03

16

*MR for LS160A and LS161A *SR for LS162A and LS163A

1 *R

N SUFFIX PLASTIC CASE 648-08

9

7

3

4

5

6

PE P0 P1 P2 P3 CEP

10

CET

2

TC

*R Q0 Q1 Q2 Q3

1 14 13 12 11 VCC = PIN 16 GND = PIN 8 *MR for LS160A and LS161A *SR for LS162A and LS163A


15

SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A

STATE DIAGRAM LS160A • LS162A

LS161A • LS163A LOGIC EQUATIONS

0

4

0

15

5

15

5

14

6

14

6

13

7

13

7

8

12

12

1

11

2

10

3

9

1

2

11

3

10

9

4

8

Count Enable = CEP • CET • PE TC for LS160A & LS162A = CET • Q0 • Q1 • Q2 • Q3 TC for LS161A & LS163A = CET • Q0 • Q1 • Q2 • Q3 Preset = PE • + (rising clock edge) Reset = MR (LS160A & LS161A) Reset = SR • + (rising clock edge) Reset = (LS162A & LS163A)

NOTE: The LS160A and LS162A can be preset to any state, but will not count beyond 9. If preset to state 10, 11, 12, 13, 14, or 15, it will return to its normal sequence within two clock pulses.

FUNCTIONAL DESCRIPTION The LS160A / 161A / 162A / 163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature. The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs. All changes of the Q outputs (except due to the asynchronous Master Reset in the LS160A and LS161A) occur as a result of, and synchronous with, the LOW to HIGH transition of the Clock input (). As long as the set-up time requirements are met, there are no special timing or activity constraints on any of the mode control or data inputs. Three control inputs — Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) — select the mode of operation as shown in the tables below. The Count Mode is enabled when the CEP, CET, and PE inputs are HIGH. When the PE is LOW, the counters will synchronously load the data from the parallel inputs into the flip-flops on the LOW to HIGH transition of the clock. Either the CEP or CET can be used to inhibit the count sequence. With the PE held HIGH, a LOW on either the CEP or CET inputs at least one set-up time prior to the LOW to HIGH clock transition will cause the existing output states to be retained. The AND feature of the two Count Enable inputs (CET • CEP) allows synchronous cascading without external gating and without delay accumulation over any practical number of bits or digits. The Terminal Count (TC) output is HIGH when the Count Enable Trickle (CET) input is HIGH while the counter is in its maximum count state (HLLH for the BCD counters, HHHH for

the Binary counters). Note that TC is fully decoded and will, therefore, be HIGH only for one count state. The LS160A and LS162A count modulo 10 following a binary coded decimal (BCD) sequence. They generate a TC output when the CET input is HIGH while the counter is in state 9 (HLLH). From this state they increment to state 0 (LLLL). If loaded with a code in excess of 9 they return to their legitimate sequence within two counts, as explained in the state diagram. States 10 through 15 do not generate a TC output. The LS161A and LS163A count modulo 16 following a binary sequence. They generate a TC when the CET input is HIGH while the counter is in state 15 (HHHH). From this state they increment to state 0 (LLLL). The Master Reset (MR) of the LS160A and LS161A is asynchronous. When the MR is LOW, it overrides all other input conditions and sets the outputs LOW. The MR pin should never be left open. If not used, the MR pin should be tied through a resistor to VCC, or to a gate output which is permanently set to a HIGH logic level. The active LOW Synchronous Reset (SR) input of the LS162A and LS163A acts as an edge-triggered control input, overriding CET, CEP and PE, and resetting the four counter flip-flops on the LOW to HIGH transition of the clock. This simplifies the design from race-free logic controlled reset circuits, e.g., to reset the counter synchronously after reaching a predetermined value.

MODE SELECT TABLE *SR

PE

CET

CEP

Action on the Rising Clock Edge (

L H H H H

X L H H H

X X H L X

X X H X L

RESET (Clear) LOAD (Pn → Qn) COUNT (Increment) NO CHANGE (Hold) NO CHANGE (Hold)


) *For the LS162A and *LS163A only. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A GUARANTEED OPERATING RANGES Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54 74

4.5 4.75

5.0 5.0

5.5 5.25

V

TA

Operating Ambient Temperature Range

54 74

– 55 0

25 25

125 70

°C

IOH


54, 74

– 0.4

mA

IOL


54 74

4.0 8.0

mA

LS160A and LS161A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol

P Parameter

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK


VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Min

Typ

Max

U i Unit

2.0 54

0.7

74

0.8 – 0.65

– 1.5


V


V


V


54

2.5

3.5

V

74

2.7

3.5

V

VCC = MIN,, IOH = MAX,, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table

54, 74

0.25

0.4

V

IOL = 4.0 mA

74

0.35

0.5

V

IOL = 8.0 mA

Input HIGH Current MR, Data, CEP, Clock PE, CET

20 40

µA


MR, Data, CEP, Clock PE, CET

0.1 0.2

mA


– 0.4 – 0.8

mA


– 100

mA

VCC = MAX

31 32

mA

VCC = MAX

IIL

Input LOW Current MR, Data, CEP, Clock PE, CET

IOS

Short Circuit Current (Note 1)

ICC

Power Supply Current Total, Output HIGH Total, Output LOW

– 20




LS162A and LS163A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol

P Parameter

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK


VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Min

Typ

Max

U i Unit

2.0 54

0.7

74

0.8 – 0.65

– 1.5


V


V


V


54

2.5

3.5

V

74

2.7

3.5

V

VCC = MIN,, IOH = MAX,, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table

54, 74

0.25

0.4

V

IOL = 4.0 mA

74

0.35

0.5

V

IOL = 8.0 mA

Input HIGH Current Data, CEP, Clock PE, CET, SR

20 40

µA


Data, CEP, Clock PE, CET, SR

0.1 0.2

mA


– 0.4 – 0.8

mA


– 100

mA

VCC = MAX

31 32

mA

VCC = MAX

IIL

Input LOW Current Data, CEP, Clock, PE, SR CET

IOS

Short Circuit Current (Note 1)

ICC

Power Supply Current Total, Output HIGH Total, Output LOW

– 20


AC CHARACTERISTICS (TA = 25°C) Limits S b l Symbol

P Parameter

Min

Typ

25

32

Max

U i Unit

fMAX


tPLH tPHL

Propagation Delay Clock to TC

20 18

35 35

ns

tPLH tPHL

Propagation Delay Clock to Q

13 18

24 27

ns

tPLH tPHL

Propagation Delay CET to TC

9.0 9.0

14 14

ns

tPHL

MR or SR to Q

20

28

ns



MHz

VCC = 5.0 50V CL = 15 pF


AC SETUP REQUIREMENTS (TA = 25°C) Limits S b l Symbol

P Parameter

Min

Typ

Max

U i Unit

tW

Clock Pulse Width Low

25

ns

tW

MR or SR Pulse Width

20

ns

ts

Setup Time, other*

20

ns

ts

Setup Time PE or SR

25

ns

th

Hold Time, data

3

ns

th

Hold Time, other

0

ns

trec

Recovery Time MR to

15

ns


VCC = 5.0 50V

*CEP, CET or DATA

DEFINITION OF SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs.

nition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.

HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recog-

AC WAVEFORMS

tW(H)

1.3 V tPHL

Q

1.3 V

tW(L)

MR 1.3 V tPLH

1.3 V

tW trec

OTHER CONDITIONS: PE = MR (SR) = H CEP = CET = H

1.3 V

1.3 V

Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3

Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width

tPHL

OTHER CONDITIONS: PE = L P0 = P1 = P2 = P3 = H

1.3 V

Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time


SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A AC WAVEFORMS (continued) COUNT ENABLE TRICKLE INPUT TO TERMINAL COUNT OUTPUT DELAYS The positive TC pulse occurs when the outputs are in the (Q0 • Q1 • Q2 • Q3) state for the LS160 and LS162 and the (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163.

1.3 V

1.3 V

CET

tPHL

tPLH

1.3 V

1.3 V

TC

Figure 3

OTHER CONDITIONS: = PE = CEP = MR = H

CLOCK TO TERMINAL COUNT DELAYS

1.3 V

1.3 V

1.3 V

tPLH

The positive TC pulse is coincident with the output state (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163 and (Q0 • Q1 • Q2 • Q3) for the LS161 and LS163.

TC

1.3 V

Figure 4

1.3 V

OTHER CONDITIONS: PE = CEP = CET = MR = H

1.3 V

SETUP TIME (ts) AND HOLD TIME (th) FOR PARALLEL DATA INPUTS

ts(H) P0 • P1 • P2 • P3

The shaded areas indicate when the input is permitted to change for predictable output performance.

tPHL

1.3 V

th(H) = 0 1.3 V

ts(L) 1.3 V

th(L) = 0 1.3 V

Q0 • Q1 • Q2 • Q3 OTHER CONDITIONS: PE = L, MR = H

Figure 5

SETUP TIME (ts) AND HOLD TIME (th) FOR COUNT ENABLE (CEP) AND (CET) AND PARALLEL ENABLE (PE) INPUTS The shaded areas indicate when the input is permitted to change for predictable output performance.

ts(L) SR or PE

1.3 V

1.3 V

th (L) = 0

ts(H)

1.3 V

CEP

1.3 V

PARALLEL LOAD (See Fig. 5)

ts(H)

th(H) = 0

COUNT MODE (See Fig. 7)

Q RESPONSE TO PE

ts(H)

COUNT OR LOAD

Q RESPONSE TO SR

th(H) = 0 1.3 V

CET 1.3 V RESET

1.3 V

1.3 V

ts(L)

th(L) = 0 1.3 V ts(L)

th(H) = 0 1.3 V COUNT

1.3 V

1.3 V HOLD

Q OTHER CONDITIONS: PE = H, MR = H

Figure 6

Figure 7


th(L) = 0 1.3 V HOLD

54LS164/DM54LS164/DM74LS164 8-Bit Serial In/Parallel Out Shift s General Description

Features

These 8-bit shift s feature gated serial inputs and an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to the low level at the next clock pulse, thus providing complete control over incoming data. A high logic level on either input enables the other input, which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the low-to-high level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects.

Y

Connection Diagram

Function Table

Y Y Y Y Y

Gated (enable/disable) serial inputs Fully buffered clock and serial inputs Asynchronous clear Typical clock frequency 36 MHz Typical power dissipation 80 mW Alternate Military/Aerospace device (54LS164) is available. a National Semiconductor Sales Office/ Distributor for specifications.


Inputs

Outputs

Clear

Clock

A

B

QA

QB

...

QH

L H H H H

X L

X X H L X

X X H X L

L QA0 H L L

L QB0 QAn QAn QAn

... ... ... ... ...

L QH0 QGn QGn QGn

u u u

H e High Level (steady state), L e Low Level (steady state) X e Don’t Care (any input, including transitions)

u e Transition from low to high level QA0, QB0, QH0 e The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn e The level of QA or QG before the most recent the clock; indicates a one-bit shift.

u transition of

TL/F/6398 – 1


Logic Diagram

TL/F/6398 – 2


TL/F/6398


54LS164/DM54LS164/DM74LS164 8-Bit Serial In/Parallel Out Shift s

June 1989

Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ tables will define the conditions for actual device operation.


b 65§ C to a 150§ C


DM54LS164

Parameter

DM74LS164

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V mA

VCC

Supply Voltage

VIH


VIL


IOH


b 0.4

b 0.4

IOL


4

8

mA

fCLK


0

25

MHz

tW


Clock

20

20

Clear

20

20

2

2

25

V

0

ns

tSU

Data Setup Time (Note 4)

17

17

ns

tH

Data Hold Time (Note 4)

5

5

ns

tREL

Clear Release Time (Note 4)

30

30

TA


b 55

125

ns

0

70

§C


Parameter

VI

Input Clamp Voltage

VOH


VOL


Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions VCC e Min, II e b18 mA VCC e Min, IOH e Max

Max

Units

b 1.5

V V

VIL e Max, VIH e Min VCC e Min, IOL e Max VIL e Max, VIH e Min

DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

V

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.4

mA

IOS


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

ICC

0.1

DM54

b 20

b 100

DM74

b 20

b 100

16

27

mA

mA mA

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs open, the SERIAL input grounded, the CLOCK input at 2.4V, and a momentary ground, then 4.5V, applied to the CLEAR input. Note 4: TA e 25§ C and VCC e 5V.

2

Switching Characteristics Symbol

Parameter

at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) From (Input) To (Output)


Max

CL e 50 pF Min

Units

Max

fMAX


tPLH


Clock to Output

25

MHz 27

30

ns

tPHL


Clock to Output

32

40

ns

tPHL


Clear to Output

36

45

ns

Timing Diagram

TL/F/6398 – 3

3




4




5

54LS164/DM54LS164/DM74LS164 8-Bit Serial In/Parallel Out Shift s













54LS174/DM54LS174/DM74LS174, 54LS175/DM54LS175/DM74LS175 Hex/Quad D Flip-Flops with Clear General Description

Features

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad (175) versions feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

Y Y Y Y Y

Y Y Y

LS174 contains six flip-flops with single-rail outputs LS175 contains four flip-flops with double-rail outputs Buffered clock and direct clear inputs Individual data input to each flip-flop Applications include: Buffer/storage s Shift s Pattern generators Typical clock frequency 40 MHz Typical power dissipation per flip-flop 14 mW Alternate Military/Aerospace device (54LS174, 54LS175) is available. a National Semiconductor Sales Office/Distributor for specifications.



TL/F/6404 – 1


TL/F/6404 – 2

Order Number 54LS175DMQB, 54LS175FMQB, 54LS175LMQB, DM54LS175J DM54LS175W, DM74LS175M or DM74LS175N See NS Package Number E20A, J16A, M16A, N16E or W16A

Function Table (Each Flip-Flop) Inputs

Outputs

Clear

Clock

D

Q

Q²

L H H H

X

u u

X H L X

L H L Q0

H L H Q0

L


TL/F/6404

H e High Level (steady state) L e Low Level (steady state) X e Don’t Care

u e Transition from low to high level Q0 e The level of Q before the indicated steady-state input conditions were established. ² e LS175 only


54LS174/DM54LS174/DM74LS174, 54LS175/DM54LS175/DM74LS175 Hex/Quad D Flip-Flops with Clear

June 1989



b 65§ C to a 150§ C


DM54LS174

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


fCLK


fCLK tW

DM74LS174

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.7

0.8

V

b 0.4

b 0.4

mA

4

8

mA

0

30

MHz

0

25

MHz

0

30


0

25


Clock

20

20

Clear

20

20

ns

tSU


20

20

ns

tH


0

0

ns

tREL


25

25

TA


b 55

125

ns

0

70

§C

Max

Units

b 1.5

V


Parameter

Min

Typ (Note 3)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

VOH





DM54

0.25

DM74

0.35

0.5


DM74

0.25

0.4

VOL

II


IIH



IIL


VCC e Max VI e 0.4V

IOS ICC

VCC e Max, VI e 7V

Clock


VCC e Max (Note 4)

Supply Current

VCC e Max (Note 5)

V 0.4

0.1

mA

20

mA

b 0.4

Clear

b 0.4

Data

b 0.36

DM54

b 20

b 100

DM74

b 20

b 100

16

26

Note 1: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 2: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 3: All typicals are at VCC e 5V, TA e 25§ C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock. Note 6: TA e 25§ C and VCC e 5V.

2

V

mA

mA mA


Symbol

RL e 2 kX


Parameter

CL e 15 pF Min

CL e 50 pF

Max

Min

30

Units

Max

fMAX


25

tPLH


Clock to Output

MHz

30

32

ns

tPHL


Clock to Output

30

36

ns

tPHL


Clear to Output

35

42

ns


DM54LS175

Parameter

VCC

Supply Voltage

VIH


VIL


IOH

DM74LS175

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.7

0.8

V


b 0.4

b 0.4

mA

IOL


4

8

mA

fCLK


0

30

0

30

MHz

fCLK


0

25

0

25

MHz

tW


Clock

20

20

Clear

20

20

20

20

ns ns

tSU


tH


0

0

tREL


25

25

TA


b 55

125

Note 1: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 2: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V. Note 3: TA e 25§ C and VCC e 5V.

3

0

ns

ns 70

§C


Parameter

Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH





DM54

0.25

DM74

0.35

0.5


DM74

0.25

0.4

VOL

II


VCC e Max, VI e 7V

IIH




VCC e Max VI e 0.4V

IIL

IOS

ICC

Clock


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

V 0.4 V

0.1

mA

20

mA

b 0.4

Clear

b 0.4

Data

b 0.36

DM54

b 20

b 100

DM74

b 20

b 100

11

18

mA

mA mA


Symbol

Parameter

RL e 2 kX


CL e 15 pF Min

Max

30

CL e 50 pF Min

Units

Max

fMAX


tPLH


Clock to Q or Q

25

MHz

30

32

ns

tPHL


Clock to Q or Q

30

36

ns

tPLH


Clear to Q

25

29

ns

tPHL


Clear to Q

35

42

ns

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock input.

4


LS175

TL/F/6404 – 4

TL/F/6404 – 3

5


Ceramic Leadless Chip Carrier (E) Order Number 54LS174LMQB or 54LS175LMQB NS Package Number E20A

16-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS174DMQB, 54LS175DMQB, DM54LS174J or DM54LS175J NS Package Number J16A

6




7

54LS174/DM54LS174/DM74LS174, 54LS175/DM54LS175/DM74LS175 Hex/Quad D Flip-Flops with Clear













54LS193/DM54LS193/DM74LS193 Synchronous 4-Bit Up/Down Binary Counters with Dual Clock General Description This circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change together when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is held high. The counter is fully programmable; that is, each output may be preset to either level by entering the desired data at the inputs while the load input is low. The output will change independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A clear input has been provided which, when taken to a high level, forces all outputs to the low level; independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements of clock drivers, etc., required for long words.

These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up and down counting functions. The borrow output produces a pulse equal in width to the count down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count down input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count down and count up inputs respectively of the succeeding counter.

Features Y Y Y Y Y

Fully independent clear input Synchronous operation Cascading circuitry provided internally Individual preset each flip-flop Alternate Military/Aerospace device (54LS193) is available. a National Semiconductor Sales Office/ Distributor for specifications.


TL/F/6406 – 1



TL/F/6406


54LS193/DM54LS193/DM74LS193 Synchronous 4-Bit Up/Down Counters with Dual Clock

June 1989



b 65§ C to a 150§ C


DM54LS193

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


fCLK


DM74LS193

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V V

0.7

0.8

V

b 0.4

b 0.4

mA

4 0

25 20

8

mA

0

25

MHz

0

20

MHz


0

tW

Pulse Width of Any Input (Note 6)

20

20

ns

tSU


20

20

ns

tH


0

0

ns

tREL

Release Time (Note 6)

TA



40

40

b 55

125

ns

0

70

over recommended operating free air temperature range (unless otherwise noted)

Parameter

Conditions

Min

Typ (Note 3)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH





DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

VOL

§C

DM54

2.5

3.4

DM74

2.7

3.4

V

V

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.4

mA

IOS


VCC e Max (Note 4)

Supply Current

VCC e Max (Note 5)

ICC

0.1

DM54

b 20

b 100

DM74

b 20

b 100

Note 1: CL e 15 pF, RL e 2 kX, IA e 25§ C and VCC e 5V. Note 2: CL e 50 pF, RL e 2 kX, IA e 25§ C and VCC e 5V. Note 3: All typicals are at VCC e 5V, TA e 25§ C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: ICC is measured with all outputs open, CLEAR and LOAD inputs grounded, and all other inputs at 4.5V. Note 6: TA e 25§ C and VCC e 5V.

2

19

34

mA

mA mA

Switching Characteristics

at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) RL e 2 kX

Symbol

Parameter


CL e 15 pF Min

Max

25

CL e 50 pF Min

Units

Max

fMAX


tPLH


Count Up to Carry

26

30

ns

tPHL


Count Up to Carry

24

36

ns

tPLH


Count Down to Borrow

24

29

ns

tPHL


Count Down to Borrow

24

32

ns

tPLH


Either Count to Any Q

38

45

ns

tPHL


Either Count to Any Q

47

54

ns

tPLH


Load to Any Q

40

41

ns

tPHL


Load to Any Q

40

47

ns

tPHL


Clear to Any Q

35

44

ns

3

20

MHz

Logic Diagram

TL/F/6406 – 2

4

Timing Diagrams Typical Clear, Load, and Count Sequences

TL/F/6406 – 3

Note A: Clear overrides load, data, and count inputs. Note B: When counting up, count-down input must be high; when counting down, count-up input must be high.

5




6




7

54LS193/DM54LS193/DM74LS193 Synchronous 4-Bit Up/Down Counters with Dual Clock









DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs Y

General Description

Y

The DM74LS221 is a dual monostable multivibrator with Schmitt-trigger input. Each device has three inputs permitting the choice of either leading-edge or trailing-edge triggering. Pin (A) is an active-low trigger transition input and pin (B) is an active-high transition Schmitt-trigger input that allows jitter free triggering for inputs with transition rates as slow as 1 volt/second. This provides the input with excellent noise immunity. Additionally an internal latching circuit at the input stage also provides a high immunity to VCC noise. The clear (CLR) input can terminate the output pulse at a predetermined time independent of the timing components. This (CLR) input also serves as a trigger input when it is pulsed with a low level pulse transition (ß). To obtain the best and trouble free operation from this device please read operating rules as well as the NSC one-shot application notes carefully and observe recommendations.

Features Y Y

Y

Y Y Y Y

Pin-out identical to ’LS123 (Note 1) Output pulse width range from 30 ns to 70 seconds Hysteresis provided at (B) input for added noise immunity Direct reset terminates output pulse Triggerable from CLEAR input DTL, TTL compatible Input clamp diodes

Note 1: The pin-out is identical to ’LS123 but, functionally it is not; refer to Operating Rules Ý10 in this datasheet.

Functional Description The basic output pulse width is determined by selection of an external resistor (RX) and capacitor (CX). Once triggered, the basic pulse width is independent of further input transitions and is a function of the timing components, or it may be reduced or terminated by use of the active low CLEAR input. Stable output pulse width ranging from 30 ns to 70 seconds is readily obtainable.

A dual, highly stable one-shot Compensated for VCC and temperature variations

Connection Diagram

Function Table


Inputs

Outputs

CLEAR

A

B

Q

Q

L X X H H

X H X L

X X L

v

u

L

L L L É É É

H H H ß ß ß

*

u H H

H e High Logic Level L e Low Logic Level X e Can Be Either Low or High

u e Positive Going Transition v e Negative Going Transition É e A Positive Pulse ß e A Negative Pulse

TL/F/6409 – 1

*This mode of triggering requires first the B input be set from a low to high level while the CLEAR input is maintained at logic low level. Then with the B input at logic high level, the CLEAR input whose positive transition from low to high will trigger an output pulse.


TL/F/6409 – 2


TL/F/6409


DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs

February 1992


If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Operating Free Air Temperature Range DM74LS Storage Temperature Range

7V 7V 0§ C to a 70§ C b 65§ C to a 150§ C


DM74LS221

Parameter

Units

Min

Nom

Max

4.75

5

5.25

V

1

2

V

VCC

Supply Voltage

VT a

Positive-Going Input Threshold Voltage at the A Input (VCC e Min)

VTb

Negative-Going Input Threshold Voltage at the A Input (VCC e Min)

VT a

Positive-Going Input Threshold Voltage at the B Input (VCC e Min)

VTb

Negative-Going Input Threshold Voltage at the B Input (VCC e Min)

IOH


b 0.4

mA

IOL


8

mA

tW


0.8

1 1

0.8

Data

40

Clear

40

V 2

0.9

V V

ns

tREL


dV dt

Rate of Rise or Fall of Schmitt Input (B) (Note 1)

15 1

V s

dV dt

Rate of Rise or Fall of Logic Input (A) (Note 1)

1

V ms

REXT

External Timing Resistor (Note 1)

1.4

100

kX

0

1000

mF

CEXT

External Timing Capacitance (Note 1)

DC

Duty Cycle (Note 1)

TA

ns

RT e 2 kX

50

RT e REXT (Max)

60


0

70

%

§C

Note 1: TA e 25§ C and VCC e 5V.


Parameter

Conditions

VI

Input Clamp Voltage


VOH



VOL



II


Min

2.7

Typ (Note 1)

Max

Units

b 1.5

V

3.4 0.35

V 0.5

VCC e Min, IOL e 4 mA

0.4

VCC e Max, VI e 7V

0.1

2

V

mA

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) (Continued) Symbol

Parameter

Conditions

IIH



IIL


VCC e Max VI e 0.4V

IOS


VCC e Max (Note 2)

ICC

Supply Current

VCC e Max

Min

Typ (Note 1)

Max

Units

20

mA

A1, A2

b 0.4

B

b 0.8

Clear

b 0.8 b 20

b 100

Quiescent

4.7

11

Triggered

19

27

mA

mA mA


Switching Characteristics at VCC e 5V and TA e 25§ C Parameter


tPLH


A1, A2 to Q

tPLH


B to Q

tPHL


tPHL

Symbol

Max

Units

70

ns

55

ns

A1, A2 to Q

80

ns


B to Q

65

ns

tPLH


Clear to Q

65

ns

tPHL


Clear to Q

55

ns

tW(out)

Output Pulse Width Using Zero Timing Capacitance

A1, A2 to Q, Q

CEXT e 0 REXT e 2 kX RL e 2 kX CL e 15 pF

20

70

ns

Output Pulse Width Using External Timing Resistor

A1, A2 to Q, Q

CEXT e 100 pF REXT e 10 kX RL e 2 kX CL e 15 pF

600

750

ns

CEXT e 1 mF REXT e 10 kX RL e 2 kX CL e 15 pF

6

7.5

ms

CEXT e 80 pF REXT e 2 kX RL e 2 kX CL e 15 pF

70

150

ns

tW(out)

Conditions

Min

CEXT e 80 pF REXT e 2 kX CL e 15 pF RL e 2 kX

3

Operating Rules 5. For CX k 1000 pF see Figure 3 for TW vs CX family curves with RX as a parameter:

1. An external resistor (RX) and an external capacitor (CX) are required for proper operation. The value of CX may vary from 0 to approximately 1000 mF. For small time constants high-grade mica, glass, polypropylene, polycarbonate, or polystyrene material capacitor may be used. For large time constants use tantalum or special aluminum capacitors. If timing capacitor has leakages approaching 100 nA or if stray capacitance from either terminal to ground is greater than 50 pF the timing equations may not represent the pulse width the device generates. 2. When an electrolytic capacitor is used for CX a switching diode is often required for standard TTL one-shots to prevent high inverse leakage current. This switching diode is not needed for the ’LS221 one-shot and should not be used. Furthermore, if a polarized timing capacitor is used on the ’LS221, the positive side of the capacitor should be connected to the ‘‘CEXT’’ pin (Figure 1 ) .

TL/F/6409 – 4

FIGURE 3 6. To obtain variable pulse widths by remote trimming, the following circuit is recommended:

TL/F/6409 – 5

Note: ‘‘Rremote’’ should be as close to the one-shot as possible.

FIGURE 4 TL/F/6409 – 8

7. Output pulse width versus VCC and temperatures: Figure 5 depicts the relationship between pulse width variation versus VCC. Figure 6 depicts pulse width variation versus temperatures.

FIGURE 1 3. For CX ll 1000 pF, the output pulse width (TW) is defined as follows: TW e KRX CX where [RX is in kX] [CX is in pF] [TW is in ns] K & Ln2 e 0.70 4. The multiplicative factor K is plotted as a function of CX below for design considerations:

TL/F/6409 – 6

FIGURE 5

TL/F/6409 – 3

FIGURE 2

TL/F/6409 – 7

FIGURE 6

4

Operating Rules (Continued) 8. Duty cycle is defined as TW/T c 100 in percentage, if it goes above 50% the output pulse width will become shorter. If the duty cycle varies between low and high values, this causes output pulse width to vary, or jitter (a function of the REXT only). To reduce jitter , REXT should be as large as possible, for example, with REXT e 100k jitter is not appreciable until the duty cycle approaches 90%. 9. Under any operating condition CX and RX must be kept as close to the one-shot device pins as possible to minimize stray capacitance, to reduce noise pick-up, and to reduce I-R and Ldi/dt voltage developed along their connecting paths. If the lead length from CX to pins (6) and (7) or pins (14) and (15) is greater than 3 cm, for example, the output pulse width might be quite different from values predicted from the appropriate equations. A noninductive and low capacitive path is necessary to ensure complete discharge of CX in each cycle of its operation so that the output pulse width will be accurate.

10. Although the ’LS221’s pin-out is identical to the ’LS123 it should be ed that they are not functionally identical. The ’LS123 is a retriggerable device such that the output is dependent upon the input transitions when its output ‘‘Q’’ is at the ‘‘High’’ state. Furthermore, it is recommended for the ’LS123 to externally ground the CEXT pin for improved system performance. However, this pin on the ’LS221 is not an internal connection to the device ground. Hence, if substitution of an ’LS221 onto an ’LS123 design layout where the CEXT pin is wired to the ground, the device will not function. 11. VCC and ground wiring should conform to good highfrequency standards and practices so that switching transients on the VCC and ground return leads do not cause interaction between one-shots. A 0.01 mF to 0.10 mF by capacitor (disk ceramic or monolithic type) from VCC to ground is necessary on each device. Furthermore, the by capacitor should be located as close to the VCC-pin as space permits. For further detailed device characteristics and output performance, please refer to the NSC one-shot application note AN-372.



5

DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs









DM54LS240/DM74LS240, DM54LS241/DM74LS241 Octal TRI-STATEÉ Buffers/Line Drivers/Line Receivers These buffers/line drivers are designed to improve both the performance and PC board density of TRI-STATE buffers/ drivers employed as memory-address drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring 400 mV of hysteresis at each low current PNP data line input, they provide improved noise rejection and high fanout outputs and can be used to drive terminated lines down to 133X.

Features Y Y Y

Typical IOL (sink current) 54LS 12 mA 74LS 24 mA Typical IOH (source current) b 12 mA 54LS b 15 mA 74LS Typical propagation delay times Inverting 10.5 ns Noninverting 12 ns Typical enable/disable time 18 ns Typical power dissipation (enabled) Inverting 130 mW Noninverting 135 mW

Y

General Description

Y

Y

Y

TRI-STATE outputs drive bus lines directly PNP inputs reduce DC loading on bus lines Hysteresis at data inputs improves noise margins

Y



TL/F/6411 – 1

TL/F/6411 – 2

Order Number DM54LS241J, DM54LS241W, DM54LS241E, DM74LS241WM or DM74LS241N See NS Package Number E20A, J20A, M20B, N20A or W20A

Order Number DM54LS240J, DM54LS240W, DM54LS240E, DM74LS240WM or DM74LS240N See NS Package Number E20A, J20A, M20B, N20A or W20A

Function Tables LS240

LS241

Inputs

Output

Inputs

Outputs

G

A

Y

G

G

1A

2A

1Y

L L H

L H X

H L Z

X X X H H L

L L H X X X

L H X X X X

X X X L H X

L H Z

2Y

L H Z

L e Low Logic Level H e High Logic Level X e Either Low or High Logic Level Z e High Impedance


TL/F/6411


DM54LS240/DM74LS240, DM54LS241/DM74LS241 Octal TRI-STATE Buffers/Line Drivers/Line Receivers

April 1992


If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS, 54LS DM74LS 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range


DM54LS240, 241

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS240, 241

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V

2

V

0.7

0.8

V

b 12

b 15

mA

24

mA

70

§C

12 b 55

125

0


Parameter

Conditions

Min

VI

Input Clamp Voltage


HYS

Hysteresis (VT a b VTb) Data Inputs Only

VCC e Min

VOH


VCC e Min, VIH e Min VIL e Max, IOH e b1 mA

DM74


DM54/DM74

VCC e Min, VIH e Min VIL e 0.5V, IOH e Max

DM54/DM74

VOL

IOZH IOZL


Typ Max Units (Note 1) b 1.5

0.2

VCC e Min VIL e Max VIH e Min

IOL e 12 mA IOL e Max

Off-State Output Current, VCC e Max High Level Voltage Applied VIL e Max VIH e Min Off-State Output Current,

V

0.4

V

3.4

V

2.7 2.4 2

DM74

0.4

DM54

0.4

DM74

0.5

V

VO e 2.7V

20

mA

VO e 0.4V

b 20

mA

0.1

mA

Low Level Voltage Applied II

Input Current at Maximum Input Voltage

VCC e Max, VI e 7V (DM74) VI e 10V (DM54)

IIH



20

mA

IIL



b 0.2

mA

IOS

Short Circuit Output Current VCC e Max (Note 2)

b 225

mA

ICC

Supply Current

b 40

VCC e Max, Outputs Open

Outputs High Outputs Low

LS240, LS241

23

LS240

26

44

LS241

27

46

Outputs Disabled LS240

29

50

LS241

32

54


2

13

mA

Switching Characteristics at VCC e 5V and TA e 25§ C Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ tPLH tPHL tPZL tPZH

Parameter

Conditions

DM54LS

DM74LS

Max

Max


CL e 45 pF RL e 667X

LS240

18

14

LS241

18

18



LS240

18

18

LS241

18

18

Output Enable Time to Low Level


LS240

30

30

LS241

30

30

Output Enable Time to High Level


LS240

23

23

LS241

23

23

Output Disable Time from Low Level

CL e 5 pF RL e 667X

LS240

25

25

LS241

25

25

Output Disable Time from High Level

CL e 5 pF RL e 667X

LS240

18

18

LS241

18

18



LS240

18

LS241

21



LS240

22

LS241

22



LS240

33

LS241

33



LS240

26

LS241

26

Note: 54LS Output load is CL e 50 pF for tPLH, tPHL, tPZL and tPZH.

3

Units

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns


20-Lead Wide Small Outline Molded Package (M) Order Number DM74LS240WM or DM74LS241WM NS Package Number M20B

20-Lead Molded Dual-In-Line Package (N) Order Number DM74LS240N or DM74LS241N NS Package Number N20A

5

DM54LS240/DM74LS240, DM54LS241/DM74LS241 Octal TRI-STATE Buffers/Line Drivers/Line Receivers


20-Lead Ceramic Flat Package (W) Order Number DM54LS240W or DM54LS241W NS Package Number W20A







54LS244/DM74LS244 Octal TRI-STATEÉ Buffers/Line Drivers/Line Receivers Y

General Description These buffers/line drivers are designed to improve both the performance and PC board density of TRI-STATE buffers/ drivers employed as memory-address drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring 400 mV of hysteresis at each low current PNP data line input, they provide improved noise rejection and high fanout outputs and can be used to drive terminated lines down to 133X.

Y Y

Y

Y

Features Y

Y

Y

TRI-STATE outputs drive bus lines directly PNP inputs reduce DC loading on bus lines Hysteresis at data inputs improves noise margins

Typical IOL (sink current) 54LS 12 mA 74LS 24 mA Typical IOH (source current) b 12 mA 54LS b 15 mA 74LS Typical propagation delay times Inverting 10.5 ns Noninverting 12 ns Typical enable/disable time 18 ns Typical power dissipation (enabled) Inverting 130 mW Noninverting 135 mW


TL/F/8442 – 1

Order Number 54LS244DMQB, 54LS244FMQB, 54LS244LMQB, DM74LS244WM or DM74LS244N See NS Package Number E20A, J20A, M20B, N20A or W20A


Output

G

A

Y

L L H

L H X

L H Z

L e Low Logic Level H e High Logic Level X e Either Low or High Logic Level Z e High Impedance


TL/F/8442


54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers

August 1989


If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C 54LS DM74LS 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range


54LS244

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS244

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V

2

V

0.7

0.8

V

b 12

b 15

mA

24

mA

70

§C

12 b 55

125

0


Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


HYS

Hysteresis (VT a b VTb) Data Inputs Only

VCC e Min

VOH



DM74


54LS/DM74


54LS/DM74


IOL e 12 mA

54LS/DM74

0.4

IOL e Max

DM74

0.5

V

VO e 2.7V

20

mA

VO e 0.4V

b 20

mA

0.1

mA

VOL


IOZH

Off-State Output Current, High Level Voltage Applied

IOZL

Off-State Output Current, Low Level Voltage Applied

II


VCC e Max

VI e 7V (DM74) VI e 10V (54LS)

IIH


VCC e Max

VI e 2.7V


VCC e Max

VI e 0.4V

IIL IOS ICC

Short Circuit Output Current Supply Current

VCC e Max VIL e Max VIH e Min

0.2

VCC e Max (Note 2) VCC e Max, Outputs Open

0.4

V

3.4

V

2.7 2.4 2

b 0.5

54LS

b 50

DM74

b 40

20

mA

b 200

mA

b 225

mA

Outputs High

13

23

Outputs Low

27

46

Outputs Disabled

32

54


2

mA

Switching Characteristics at VCC e 5V, TA e 25§ C (see Section 1 for Test Waveforms and Output Load) Parameter

Conditions

54LS Max

DM74LS Max

Units

tPLH

Symbol



18

18

ns

tPHL



18

18

ns

tPZL



30

30

ns

tPZH



23

23

ns

tPLZ


CL e 5 pF RL e 667X

25

25

ns

tPHZ


CL e 5 pF RL e 667X

18

18

ns

tPLH



21

ns

tPHL



22

ns

tPZL



33

ns

tPZH



26

ns

Note: 54LS Output Load is CL e 50 pF for tPLH, tPHL, tPZL and tPZH.

3



20-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS244DMQB NS Package Number J20A 4




5

54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers


20-Lead Ceramic Flat Package (W) Order Number 54LS244FMQB NS Package Number W20A







54LS245/DM54LS245/DM74LS245 TRI-STATEÉ Octal Bus Transceiver General Description These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated.

Features Y

Y

Y Y Y Y Y

Y

Y

Bi-Directional bus transceiver in a high-density 20-pin package TRI-STATE outputs drive bus lines directly

PNP inputs reduce DC loading on bus lines Hysteresis at bus inputs improve noise margins Typical propagation delay times, port-to-port 8 ns Typical enable/disable times 17 ns IOL (sink current) 54LS 12 mA 74LS 24 mA IOH (source current) b 12 mA 54LS b 15 mA 74LS Alternate Military/Aerospace device (54LS245) is available. a National Semiconductor Sales Office/ Distributor for specifications.


TL/F/6413 – 1

Order Number 54LS245DMQB, 54LS245FMQB, 54LS245LMQB, DM54LS245J, DM54LS245W, DM74LS245WM or DM74LS245N See NS Package Number E20A, J20A, M20B, N20A or W20A

Function Table Enable G

Direction Control DIR

L L H

L H X

Operation

B data to A bus A data to B bus Isolation

H e High Level, L e Low Level, X e Irrelevant TRI-STATEÉ is a ed trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation

TL/F/6413


54LS245/DM54LS245/DM74LS245 TRI-STATE Octal Bus Transceiver

June 1989



Supply Voltage 7V Input Voltage DIR or G 7V A or B 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS and 54LS DM74LS 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range


DM54LS245

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS245

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V

2

V

0.7

0.8

V

b 12

b 15

mA

24

mA

70

§C

12 b 55

125

0


Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


HYS

Hysteresis (VT a b VTb)

VCC e Min

VOH



DM74

VCC e Min, VIL e Min VIL e Max, IOH e b3 mA

DM54/DM74


DM54/DM74


IOL e 12 mA

DM74

0.4

IOL e Max

DM54

0.4

DM74

0.5

VCC e Max VIL e Max VIH e Min

VO e 2.7V

20

mA

VO e 0.4V

b 200

mA

VOL


IOZH

Off-State Output Current, High Level Voltage Applied

IOZL

Off-State Output Current, Low Level Voltage Applied

II


VCC e Max

0.2

0.4

V

3.4

V

2.7 2.4 2

A or B

VI e 5.5V

0.1

DIR or G

VI e 7V

0.1

V

mA

IIH



20

mA

IIL



b 0.2

mA

IOS


VCC e Max (Note 2)

b 225

mA

ICC

Supply Current

Outputs High

b 40

VCC e Max

48

70

Outputs Low

62

90

Outputs at Hi-Z

64

95

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, not to exceed one second duration

2

mA

Switching Characteristics VCC e 5V, TA e 25§ C (See Section 1 for Test Waveforms and Output Load) DM54/74 Symbol

Parameter

Conditions

LS245 Min

tPLH

Propagation Delay Time, Low-to-High-Level Output

tPHL

Propagation Delay Time, High-to-Low-Level Output

tPZL


tPZH


tPLZ


tPHZ


tPLH

Propagation Delay Time, Low-to-High-Level Output

tPHL

Propagation Delay Time, High-to-Low-Level Output

tPZL


tPZH



CL e 5 pF RL e 667X

3


Units Max 12

ns

12

ns

40

ns

40

ns

25

ns

25

ns

16

ns

17

ns

45

ns

45

ns



20-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS245DMQB or DM54LS245J NS Package Number J20A 4


20-Lead Small Outline Molded Package (M) Order Number DM74LS245WM NS Package Number M20B


5

54LS245/DM54LS245/DM74LS245 TRI-STATE Octal Bus Transceiver









DM54LS259/DM74LS259 8-Bit Addressable Latches General Description

Features

These 8-bit addressable latches are designed for general purpose storage applications in digital systems. Specific uses include working s, serial-holding s, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function table. In the addressable-latch mode, data at the datain terminal is written into the addressed latch. The addressed latch will follow the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output will follow the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs.

Y

Connection Diagram

Function Table

Y Y Y Y Y Y Y

Y

Y

8-Bit parallel-out storage performs serial-to-parallel conversion with storage Asynchronous parallel clear Active high decoder Enable/disable input simplifies expansion Direct replacement for Fairchild 9334 Expandable for N-bit applications Four distinct functional modes Typical propagation delay times: Enable-to-output 18 ns Data-to-output 16 ns Address-to-output 21 ns Clear-to-output 17 ns Fan-out IOL (sink current) 54LS259 4 mA 74LS259 8 mA IOH (source current) b0.4 mA Typical ICC 22 mA

Inputs


Clear

E

Output of Addressed Latch

H H L L

L H L H

D Qi0 D L

Each Other Output

Function

Qi0 Qi0 L L

Addressable Latch Memory 8-Line Demultiplexer Clear

Latch Selection Table Select Inputs

TL/F/6418 – 1

Order Number DM54LS259E, DM54LS259J, DM54LS259W, DM74LS259M, DM74LS259WM or DM74LS259N See NS Package Number E20A, J16A, M16A, M16B, N16E or W16A


TL/F/6418

C

B

A

Latch Addressed

L L L L H H H H

L L H H L L H H

L H L H L H L H

0 1 2 3 4 5 6 7

H e High Level, L e Low Level D e the Level of the Data Input Qi0 e the Level of Qi (i e 0, 1, . . . 7, as Appropriate) before the Indicated Steady-State Input Conditions Were Established.


DM54LS259/DM74LS259 8-Bit Addressable Latches

May 1992


If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54 DM74LS 0§ C to a 70§ C Storage Temperature Range

b 65§ C to a 150§ C


DM54LS259

Parameter

DM74LS259

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

VCC

Supply Voltage

VIH


VIL


IOH


b 0.4

b 0.4

mA

IOL


4

8

mA

tW


Enable

17

15

Clear

17

15

Setup Time (Notes 1, 2, 3 & 7)

Data

20u

15u

Select

15v

15v

Hold Time (Notes 1, 2 & 7)

Data

5u

2.5u

Select

0u

2.5u

tSU tH TA

2


2

b 55

125

V

ns ns ns

0

70

§C


Parameter

Conditions

Min

Typ (Note 4)

Max

Units

b 1.5

V

VI

Input Clamp Voltage

VOH





DM54 DM74

0.35

0.5


DM74

0.25

0.4


VCC e Max, VI e 7V VI e 10V

DM74

IIH


IIL

VOL

II

IOS ICC

DM54

2.5

DM74

2.7

V 3.4 0.4 V

0.1

mA


20

mA



b 0.4

Enable


b 0.8


VCC e Max (Note 5)

Supply Current

VCC e Max (Note 6)

Note 1: The symbols (

DM54

DM54

b 20

b 100

DM74

b 20

b 100

22

36

mA

mA mA

v, u) indicate the edge of the clock pulse used for reference: u for rising edge, v for falling edge.

Note 2: Setup and hold times are with reference to the enable input. Note 3: The select-to-enable setup time is the time before the High-to-Low enable transition that the select must be stable so that the correct latch is selected and the others not affected. Note 4: All typicals are at VCC e 5V, TA e 25§ C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 6: ICC is measured with all inputs at 4.5V, and all outputs open. Note 7: TA e 25§ C and VCC e 5V.

2

Switching Characteristics at VCC e 5V and TA e 25§ C DM54LS

DM74LS

CL e 15 pF

CL e 50 pF RL e 2 kX

Parameter


tPLH


Enable to Output

27

38

ns

tPHL


Enable to Output

24

32

ns

tPLH


Data to Output

30

35

ns

tPHL


Data to Output

20

30

ns

tPLH


Select to Output

30

41

ns

tPHL


Select to Output

29

38

ns

tPHL


Clear to Output

18

36

ns

Symbol

Min


Ceramic Leadless Chip Carrier (E) Order Number DM54LS259E NS Package Number E20A

3

Max

Min

Units

Max



16-Lead Molded Package Small Outline (SO) Order Number DM74LS259M NS Package Number M16A

4




5

DM54LS259/DM74LS259 8-Bit Addressable Latches


16-Lead Ceramic Flat Package (W) Order Number DM54LS259W NS Package Number W16A







DM54LS260/DM74LS260 Dual 5-Input NOR Gate General Description This device contains two individual five input gates, each of which perform the logic NOR function.


TL/F/9824 – 1

Order Number DM54LS260J, DM54LS260W, DN54LS260E, DM74LS260M or DM74LS260N See NS Package Number E20A, J14A, M14A, N14A or W14B

Truth Table AaBaCaDaEeY Inputs


TL/F/9824

Outputs

A

B

C

D

E

Y

L X X X X H

L X X X H X

L X X H X X

L X H X X X

L H X X X X

H L L L L L


DM54LS260/DM74LS260 Dual 5-Input NOR Gate

April 1992



Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS DM74LS 0§ C to a 70§ C b 65§ C to a 150§ C

Storage Temperature Range


DM54LS260

Parameter

DM74LS260

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.7

0.8

V

VCC

Supply Voltage

VIH


VIL


IOH


b 0.4

b 0.4

mA

IOL


4

8

mA

70

§C

TA


2

2

b 55

125

V

0


Parameter

Conditions

Typ (Note 1)

Min

Max

Units

b 1.5

V

VI

Input Clamp Voltage

VCC e Min, II e b 18 mA

VOH



DM54

2.5

DM74

2.7



DM54

0.4

DM74

0.5


DM74

0.4


VCC e Max, VI e 7V VI e 10V

DM54

IIH



IIL



VOL

II

IOS

ICCH ICCL

V

V

0.1

mA

20

mA

DM54

b 0.40

DM74

b 0.36

DM54

b 20

b 100

DM74

b 20

b 100

mA


VCC e Max (Note 2)


VCC e Max, VIN e GND

4.0

mA


VCC e Max, VIN e Open

5.5

mA


Switching Characteristics VCC e a 5V, TA e a 25§ C Symbol

RL e 2 kX, CL e 15 pF

Parameter

Min

Units

Max

tPLH


10

ns

tPHL


12

ns

2

mA

3




4




5

DM54LS260/DM74LS260 Dual 5-Input NOR Gate









DM54LS273/DM74LS273 8-Bit with Clear General Description

Features

The ’LS273 is a high speed 8-bit , consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20pin package featuring 0.3 inch row spacing.

Y Y Y Y

Edge-triggered 8-bit high speed Parallel in and out Common clock and master reset


TL/F/9825 – 1

Order Number DM54LS273E, DM54LS273J, DM54LS273W, DM74LS273M or DM74LS273N See NS Package Number E20A, J20A, M20B, N20A or W20A Pin Names D0–D7 MR Q0–Q7


TL/F/9825

Description Clock Pulse Input (Active Rising Edge) Data Inputs Asynchronous Master Reset Input (Active LOW) Flip-Flop Outputs


DM54LS273/DM74LS273 8-Bit with Clear

April 1992




DM54LS273

Parameter

DM74LS273

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


ts(H) ts(L)

Setup Time HIGH or LOW Dn to

15 15

15 15

ns

th(H) th(L)

Hold Time HIGH or LOW Dn to

5 5

5 5

ns

tw(H) tw(L)

Pulse Width HIGH or LOW

20 20

20 20

ns

tw(L)

MR Pulse Width LOW

20

20

ns

trec

Recovery Time MR to

15

15

ns

2

2

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

4 b 55

V

125

0

Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol

Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH



DM54

2.5

DM74

2.7



DM74

0.35

0.5


DM74

0.25

0.4

VOL

V 3.4

DM54

0.4 V

II


VCC e Max, VI e 7V VI e 10V (DM54)

IIH



20

mA

IIL



b 0.4

mA

IOS


VCC e Max (Note 2)

Supply Current

VCC e Max

ICC

0.1

DM54

b 20

b 100

DM74

b 20

b 100

27


2

mA

mA mA

Switching Characteristics VCC e a 5.0V, TA e a 25§ C CL e 15 pF Symbol

Parameter

DM74LS

DM54LS

Units

RL e 2 kX Min

Max

Min

30

Max

fmax


30

tPLH tPHL

Propagation Delay to Qn

24 24

24 24

ns

tPLH

Propagation Delay MR to Qn

27

27

ns

Functional Description

MHz

Truth Table

The ’LS273 is an 8-bit parallel with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, independent of the other inputs. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-toHIGH transition of the clock input.

MR

Inputs

Dn

Outputs Qn

L H H

X L L

X H L

L H L

H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial

Logic Symbol

TL/F/9825 – 2

VCC e Pin 20 GND e Pin 10

Logic Diagram

TL/F/9825 – 3

3




4


20-Lead Wide Small Outline Molded Package (M) Order Number DM74LS273M NS Package Number M20B


5

DM54LS273/DM74LS273 8-Bit with Clear


20-Lead Ceramic Flat Package (W) Order Number DM54LS273W NS Package Number W20A







54LS279/DM54LS279/DM74LS279 Quad S-R Latches General Description The ’LS279 consists of four individual and independent SetReset Latches with active low inputs. Two of the four latches have an additonal S input ANDed with the primary S input. A low on any S input while the R input is high will be stored in the latch and appear on the corresponding Q output as a high. A low on the R input while the S input is high will clear the Q output to a low. Simultaneous transistion of the R and S inputs from low to high will cause the Q output

to be indeterminate. Both inputs are voltage level triggered and are not affected by transition time of the input data.

Features Y



TL/F/6420 – 1

Order Number 54LS279DMQB, 54LS279FMQB, 54LS279LMQB, DM54LS279J, DM74LS279M or DM74LS279N See NS Package Number E20A, J16A, M16A, N16E or W16A


Output

S(1)

R

Q

L L H H

L H L H

H* H L Q0

H e High Level L e Low Level Q0 e The Level of Q before the indicated input conditions were established. *This output level is pseudo stable; that is, it may not persist when the S and R inputs return to their inactive (high) level. Note 1: For latches with double S inputs: H e both S inputs high L e one or both S inputs low


TL/F/6420


54LS279/DM54LS279/DM74LS279 Quad S-R Latches

May 1989



b 65§ C to a 150§ C


DM54LS279

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS279

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

4 b 55

V

125

0


Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH


VCC e Min, IOH e Max

DM54

2.5

3.5

VIL e Max, VIH e Min

DM74

2.7

3.5


DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4

VOL


V

V

II


VCC e Max, VI e 7V

0.1

mA

IIH



20

mA

IIL



b 0.4

mA

IOS


VCC e Max (Note 2)

Supply Current

VCC e Max (Note 3)

ICC

DM54

b 20

b 100

DM74

b 20

b 100

3.8

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all R inputs grounded, all S inputs at 4.5V and all outputs open.

2

7

mA mA


Parameter

RL e 2 kX


CL e 15 pF Min

Max

CL e 50 pF Min

Units

Max

tPLH


S to Q

22

25

ns

tPHL


S to Q

15

23

ns

tPHL


R to Q

27

33

ns

3




4




5

54LS279/DM54LS279/DM74LS279 Quad S-R Latches









54LS283/DM54LS283/DM74LS283 4-Bit Binary Adders with Fast Carry General Description

Features

These full adders perform the addition of two 4-bit binary numbers. The sum (R) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial lookahead performance at the economy and reduced package count of a ripple-carry implementation. The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.

Y Y

Y

Y Y

Full-carry look-ahead across the four bits Systems achieve partial look-ahead performance with the economy of ripple carry Typical add times Two 8-bit words 25 ns Two 16-bit words 45 ns Typical power dissipation per 4-bit adder 95 mW Alternate Military/Aerospace device (54LS283) is available. a National Semiconductor Sales Office/ Distributor for specifications.


TL/F/6421 – 1



TL/F/6421


54LS283/DM54LS283/DM74LS283 4-Bit Binary Adders with Fast Carry

June 1989



b 65§ C to a 150§ C


DM54LS283

Parameter

VCC

Supply Voltage

VIH


VIL


IOH


IOL


TA


DM74LS283

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V

0.7

0.8

V

b 0.4

b 0.4

mA

8

mA

70

§C

4 b 55

V

125

0


Parameter

Min

Typ (Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH





DM54

0.25

0.4

DM74

0.35

0.5


DM74

0.25

0.4


VCC e Max VI e 7V

A, B

0.2

C0

0.1


VCC e Max VI e 2.7V

A, B

40

C0

20


VCC e Max VI e 0.4V


VCC e Max (Note 2)

ICC1

Supply Current

VCC e Max (Note 3)

19

34

mA

ICC2

Supply Current

VCC e Max (Note 4)

22

39

mA

VOL

II

IIH

IIL

IOS

A, B

b 0.8

C0

b 0.4

DM54

b 20

b 100

DM74

b 20

b 100

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC1 is measured with all outputs open, all B inputs low and all other inputs at 4.5V, or all inputs at 4.5V. Note 4: ICC2 is measured with all outputs open and all inputs grounded.

2

V

V

mA

mA

mA

mA


Parameter

RL e 2 kX


CL e 15 pF Min

Max

CL e 50 pF Min

Units

Max

tPLH


C0 to R1, R2

24

28

ns

tPHL


C0 to R1, R2

24

30

ns

tPLH


C0 to R3

24

28

ns

tPHL


C0 to R3

24

30

ns

tPLH


C0 to R4

24

28

ns

tPHL


C0 to R4

24

30

ns

tPLH


Ai or Bi to Ri

24

28

ns

tPHL


Ai or Bi to Ri

24

30

ns

tPLH


C0 to C4

17

24

ns

tPHL


C0 to C4

17

25

ns

tPLH


Ai or Bi to C4

17

24

ns

tPHL


Ai or Bi to C4

17

26

ns

Function Table

TL/F/6421 – 3

H e High Level, L e Low Level Note: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs R1 and R2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs R3, R4, and C4.

3

Logic Diagram LS283

TL/F/6421 – 2

4

5




6




7

54LS283/DM54LS283/DM74LS283 4-Bit Binary Adders with Fast Carry









DM54LS373/DM74LS373, DM54LS374/DM74LS374 TRI-STATEÉ Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description

Features

These 8-bit s feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these s with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer s, I/O ports, bidirectional bus drivers, and working s. (Continued)

Y

Y Y Y Y

Choice of 8 latches or 8 D-type flip-flops in a single package TRI-STATE bus-driving outputs Full parallel-access for loading Buffered control inputs P-N-P inputs reduce D-C loading on data lines

Connection Diagrams Dual-In-Line Packages ’LS373

Order Number DM54LS373J, DM54LS373W, DM74LS373N or DM74LS373WM See NS Package Number J20A, M20B, N20A or W20A

TL/F/6431 – 1

’LS374

Order Number DM54LS374J, DM54LS374W, DM74LS374WM or DM74LS374N See NS Package Number J20A, M20B, N20A or W20A

TL/F/6431 – 2 TRI-STATEÉ is a ed trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation

TL/F/6431


DM54LS373/DM74LS373, DM54LS374/DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

May 1992

General Description (Continued) A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are off.

The eight latches of the DM54/74LS373 are transparent Dtype latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs. When the enable is taken low the output will be latched at the level of the data that was set up. The eight flip-flops of the DM54/74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.

Function Tables DM54/74LS373

DM54/74LS374

Output Control

Enable G

D

Output

Output Control

L L L H

H H L X

H L X X

H L Q0 Z

L L L H

Clock

D

Output

u u

H L X X

H L Q0 Z

L X

H e High Level (Steady State), L e Low Level (Steady State), X e Don’t Care e Transition from low-to-high level, Z e High Impedance State Q0 e The level of the output before steady-state input conditions were established.

u

Logic Diagrams DM54/74LS373 Transparent Latches

DM54/74LS374 Positive-Edge-Triggered Flip-Flops

TL/F/6431–3

TL/F/6431 – 4

2

Absolute Maximum Ratings (See Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation.

If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Storage Temperature Range

7V 7V

b 65§ C to a 150§ C Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS DM74LS 0§ C to a 70§ C


DM54LS373

Parameter

DM74LS373

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

VCC

Supply Voltage

VIH

High Level Input Votage

VIL


0.7

0.8

V

IOH


b1

b 2.6

mA

IOL


24

mA

tW


2

2

12

Enable High

15

15

Enable Low

15

15

tSU

Data Setup Time (Notes 1 & 2)

5v

5v

tH

Data Hold Time (Notes 1 & 2)

20v

20v

TA



b 55

125

V V

ns ns ns

0

70

§C

v) indicates the falling edge of the clock pulse is used for reference.

Note 2: TA e 25§ C and VCC e 5V.


Parameter

Conditions

VI

Input Clamp Voltage


VOH


VCC e Min IOH e Max VIL e Max VIH e Min

VOL


Min

DM54

Typ (Note 1)

2.4

3.4

2.4

3.1

Max

Units

b 1.5

V V

DM74

VCC e Min IOL e Max VIL e Max VIH e Min

DM54 DM74

IOL e 12 mA VCC e Min

0.25

0.4

0.35

0.5

DM74

V

0.4

II


VCC e Max, VI e 7V

IIH



20

mA

IIL



b 0.4

mA

IOZH



20

mA



b 20

mA


VCC e Max (Note 2)

Supply Current

VCC e Max, OC e 4.5V, Dn, Enable e GND

IOZL

IOS ICC

3

0.1

DM54

b 20

b 100

DM74

b 50

b 225

24

40

mA

mA mA

‘LS373 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)

Symbol


Parameter

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

RL e 667X CL e 45 pF Min

CL e 150 pF

Max

Min

Units

Max


Data to Q

18

26

ns


Data to Q

18

27

ns


Enable to Q

30

38

ns


Enable to Q

30

36

ns


Output Control to Any Q

28

36

ns



36

50

ns



20

ns



25

ns

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: CL e 5 pF.


DM54LS374

Parameter

DM74LS374

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

VCC

Supply Voltage

VIH


VIL


0.7

0.8

V

IOH


b1

b 2.6

mA

IOL


24

mA

tW


2

2

12 Clock High

15

15

Clock Low

15

15

tSU

Data Setup Time (Notes 1 & 4)

20u

20u

tH

Data Hold Time (Notes 1 & 4)

1u

1u

TA


b 55

u

Note 1: The symbol ( ) indicates the rising edge of the clock pulse is used for reference. Note 4: TA e 25§ C and VCC e 5V.

4

125

0

V

ns ns ns 70

§C


Parameter

Conditions

Min

Typ (Note 1)

Max

Units

b 1.5

V

VI

Input Clamp Voltage


VOH


VCC e Min IOH e Max VIL e Max VIH e Min

DM54

2.4

3.4

DM74

2.4

3.1

VCC e Min IOL e Max VIL e Max VIH e Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL e 12 mA VCC e Min

DM74

VOL

II


V

V 0.25

0.4


VCC e Max, VI e 7V

IIH


20

mA

IIL



b 0.4

mA

IOZH



20

mA



b 20

mA


VCC e Max (Note 2)

Supply Current

VCC e Max, Dn e GND, OC e 4.5V

IOZL

IOS ICC

0.1

DM54

b 50

b 225

DM74

b 50

b 225

27

mA

mA

45

mA

’LS374 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) RL e 667X Symbol

Parameter

CL e 45 pF Min

Max

35

CL e 150 pF Min

Units

Max

fMAX


tPLH


20 28

32

ns

tPHL


28

38

ns

tPZH


28

44

ns

tPZL


28

44

ns

tPHZ


20

ns

tPLZ


25

ns

Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: CL e 5 pF.

5

MHz


20-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS373J or DM54LS374J NS Package Number J20A

6


20-Lead Wide Small Outline Molded Package (M) Order Number DM74LS373WM or DM74LS374WM NS Package Number M20B

20-Lead Molded Dual-In-Line Package (N) Order Number DM74LS373N and DM74LS374N NS Package Number N20A

7

DM54LS373/DM74LS373, DM54LS374/DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops


20-Lead Ceramic Flat Package (W) Order Number DM54LS373W or DM54LS374W NS Package Number W20A















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