Digital Waveform Generation - Symons - Cambridge 2013 474ro

Digital Waveform Generation This concise overview of digital signal generation will introduce you to powerful, flexible and practical digital waveform generation techniques. These techniques, based largely on phase accumulation and phase–amplitude mapping, will enable you to generate sinusoidal and arbitrary waveforms in real-time with independently controlled waveshape, frequency, phase offset and amplitude, and to design and optimise bespoke digital waveform generation systems from scratch. The book includes a review of key definitions, a brief explanatory introduction to classical analogue waveform generation and its basic conceptual and mathematical foundations, coverage of recursion, DDS, IDFT and dynamic waveshape and spectrum control, and a chapter dedicated to detailed examples of hardware design, accompanied by able Mathcad models created to help you explore ‘what if?’ design scenarios. It is essential reading for practitioners in the digital signal processing community, and for students who want to understand and apply digital waveform synthesis techniques. Pete Symons is a professional engineer with over 30 years’ experience in the design of digital and analogue signal processing systems, and is Chief Engineer at Avalon Sciences Ltd. He has held numerous positions in industry, including Chief Engineer for the Special Projects Research Group at Thales UK, and Group Leader of the Electronics Research Group at the Atomic Weapons Establishment, UK. He is a Chartered Engineer, and a Fellow of the IET.

‘Symons writes with irable precision and attention to detail in describing techniques for arbitrary waveform generation based upon Direct Digital Synthesis principles. Newcomers to the topic and seasoned practitioners alike will benefit from the extensive tutorial content ing the theoretical foundations, synthesis algorithms and processing architectures employed in the implementation of these powerful and flexible techniques. A notable feature is the inclusion of simulated performance results for several arbitrary waveform phase–amplitude mapping algorithms, illustrating the dependence of the amplitude spectrum and other performance metrics on a range of design and control parameters.’ Mike Meade, Open University ‘This is a very readable signal processing book – comprehensive in scope, and thorough in presentation. Clear explanations, detailed illustrations, and practical implementation guidance make it a welcomed addition to the literature of modern-day digital waveform generation.’ Rick Lyons, Besser Associates

Digital Waveform Generation PETE SYMONS

University Printing House, Cambridge CB2 8BS, United Kingdom Published in the United States of America by Cambridge University Press, New York Cambridge University Press is part of the University of Cambridge. It furthers the University’s mission by disseminating knowledge in the pursuit of education, learning and research at the highest international levels of excellence. www.cambridge.org Information on this title: www.cambridge.org/9781107020979 © Cambridge University Press 2014 This publication is in copyright. Subject to statutory exception and to the provisions of relevant collective licensing agreements, no reproduction of any part may take place without the written permission of Cambridge University Press. First published 2014 Printed in the United Kingdom by Clays, St Ives plc A catalogue record for this publication is available from the British Library. Library of Congress Catag-in-Publication data Symons, Pete, Dr. Digital waveform generation / Pete Symons Includes bibliographical references and index. ISBN 978-1-107-020979 (Hardback) 1. Signal processing–Digital techniques. 2. Electric waves. 3. Oscillators, Electric. TK5102.9.S96 2014 621.38150 33–dc23 2013007041 ISBN 978-1-107-020979 Hardback Additional resources for this publication at www.cambridge.org/symons Cambridge University Press has no responsibility for the persistence or accuracy of URLs for external or third-party internet websites referred to in this publication, and does not guarantee that any content on such websites is, or will remain, accurate or appropriate.

I. Title.

Contents

Preface Acknowledgements Glossary of 1

Introduction to waveform generation 1.1

1.2

1.3

1.4

Preliminaries 1.1.1 Outline chapter content 1.1.2 Digital signal processing 1.1.3 Periodic and aperiodic waveforms 1.1.4 Introducing the sine wave – properties and parameters 1.1.5 Instantaneous phase and frequency 1.1.6 From phase to amplitude – the waveform function 1.1.7 Signal definition – waveform or spectrum? 1.1.8 Signal specification – time or frequency domain? 1.1.9 A brief history of digital waveform generation A taxonomy of electronic waveform generation 1.2.1 Background 1.2.2 Analogue waveform generation 1.2.3 Hybrid waveform generation 1.2.4 Digital waveform generation 1.2.5 Arbitrary waveform generation Analogue waveform generation 1.3.1 Analogue waveform generation in test instrumentation 1.3.2 The Wien bridge oscillator 1.3.3 The state variable oscillator 1.3.4 The voltage-controlled switched integration oscillator 1.3.5 The charge-balancing voltage to frequency convertor 1.3.6 The shortcomings of analogue waveform generation Applications of arbitrary waveform generation 1.4.1 Test and diagnostic applications 1.4.2 Signal emulation applications 1.4.3 Bespoke embedded applications 1.4.4 RF up-conversion applications

page xi xvi xvii 1 3 3 5 6 9 10 12 14 15 17 19 19 19 23 24 25 31 31 32 34 36 38 38 41 41 42 43 43

vi

Contents

1.4.5 Unique DDS AWG attributes 1.4.6 A simple example – testing a PLL Summary References

45 45 47 48

The foundations of digital waveform generation

49

2.1

49 49 52 54 54 55 55 56 57 58 59 59 60 62 63 64 64 67 68 70 73 74 75 76 78 79 79 81 83 83 85 85 86 88 89 89

1.5 1.6 2

2.2

2.3

2.4

2.5

2.6

2.7 2.8

Mathematical preliminaries 2.1.1 Continuous- and discrete-time signals 2.1.2 The phase–frequency relationship of a discrete-time sinusoid 2.1.3 Analogue reconstruction and alias image rejection 2.1.4 Quantisation and digital to analogue conversion A fundamental concept – sampling a tabulated signal 2.2.1 Tabulating a signal – introducing the wavetable 2.2.2 Regenerating a tabulated signal 2.2.3 A sample rate conversion view 2.2.4 Frequency control resolution and wavetable length Tabulating a waveform function 2.3.1 The wavetable revisited 2.3.2 Tabulating the sine function 2.3.3 Time domain arbitrary waveform specification 2.3.4 Frequency domain arbitrary waveform specification The foundations of direct digital synthesis (DDS) 2.4.1 Phase accumulation frequency synthesis 2.4.2 Phase–amplitude mapping 2.4.3 Phase continuity 2.4.4 Phase–amplitude mapping and fractional addressing 2.4.5 The aliasing problem Control parameters and their characteristics 2.5.1 Desirable control characteristics 2.5.2 Frequency control 2.5.3 Phase offset control 2.5.4 Amplitude control 2.5.5 Waveshape control 2.5.6 Spectrum control Performance metrics 2.6.1 Phase truncation noise 2.6.2 The amplitude error spectrum 2.6.3 Waveshape error 2.6.4 Phase noise 2.6.5 Arithmetic processing requirements Summary References

Contents

3

Recursive sine wave oscillators 3.1 3.2 3.3 3.4 3.5 3.6

3.7 3.8 4

90 91 93 99 101 101 102 102 104 106 107 108

DDS sine wave generation

109

4.1

109 110 112 114 122 124 125 127 128 128 129 132 134 134 135 138 144 148 152

4.2

4.3

4.4 4.5 5

Mathematical preliminaries The direct-form The coupled-form The modified coupled-form The waveguide-form Implementation considerations 3.6.1 Initial conditions 3.6.2 Arithmetic quantisation effects 3.6.3 Frequency control Summary References

vii

Phase accumulation, truncation and arithmetic processing 4.1.1 Ideal sinusoidal DDS 4.1.2 Optimal phase–amplitude mapping 4.1.3 Phase truncation and fractional wavetable addressing 4.1.4 Linear phase interpolation 4.1.5 Static and dynamic phase offset 4.1.6 Quadrature sine wave generation 4.1.7 Introducing phase domain processing Theoretical analysis of DDS phase truncation errors 4.2.1 The DDS error model 4.2.2 Phase truncation errors 4.2.3 Wavetable sample quantisation errors Sinusoidal phase–amplitude mapping 4.3.1 SNR and oversampling 4.3.2 Phase truncated wavetable indexing 4.3.3 Phase dithered wavetable indexing and noise shaping 4.3.4 Linear phase interpolated wavetable indexing 4.3.5 Trigonometric identity phase interpolation 4.3.6 Sinusoidal wavetable compression 4.3.7 Direct computation phase–amplitude mapping – the CORDIC algorithm Summary References

155 159 161

DDS arbitrary waveform generation

162

5.1

162 163 165

From sinusoidal to arbitrary waveforms 5.1.1 Phase truncation and the need for interpolation 5.1.2 Introducing Lagrange polynomial interpolation

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Contents

5.2

5.3

5.4

5.5

5.6

5.7 5.8 6

5.1.3 The harmonic aliasing problem 5.1.4 Time domain specification of an arbitrary waveform 5.1.5 Frequency domain specification of an arbitrary waveform 5.1.6 Defining DDS AWG simulation parameters 5.1.7 Optimal phase–amplitude mapping Interpolated phase–amplitude mapping 5.2.1 Phase truncated wavetable indexing 5.2.2 Phase dithered wavetable indexing 5.2.3 Linear phase interpolated wavetable indexing 5.2.4 Lagrange polynomial phase interpolated wavetable indexing Analogue waveshaping 5.3.1 The phase accumulator as a digital frequency synthesiser 5.3.2 Analogue waveshaping principles and some fundamental problems 5.3.3 Triangle waveform shaping DDS clock generation 5.4.1 Hard-limited sinusoidal DDS 5.4.2 Reconstruction filter bandwidth Variable sample frequency AWG 5.5.1 Basic architecture and implementation limitations 5.5.2 Harmonic aliasing and reconstruction filter considerations Computer music and audio test applications of DDS AWG 5.6.1 Harmonics and partials 5.6.2 Frequency control, musical pitch and tuning 5.6.3 Audio measurement – harmonic and intermodulation distortion Summary References

Dynamic waveshape and spectrum control 6.1

6.2

6.3

Paged wavetable memory – piecewise stepped waveshaping 6.1.1 Page indexing a group of wavetables 6.1.2 Specifying a group of wavetables 6.1.3 Paged wavetable interpolation – piecewise continuous waveshaping 6.1.4 Frequency domain behaviour Linear combination of multiple wavetables 6.2.1 Single phase accumulator case – harmonic signal synthesis 6.2.2 The IDFT as a limiting case 6.2.3 Multiple phase accumulator case – band- signal synthesis Modulation 6.3.1 Frequency, phase and amplitude modulation 6.3.2 FSK and PSK modulation 6.3.3 Frequency sweep and chirp generation

170 172 178 181 184 186 186 187 192 195 203 205 207 211 213 214 216 217 217 218 219 220 221 222 225 227 228 229 229 231 233 235 236 237 239 241 242 243 244 246

Contents

6.4 6.5 7

247 248

Phase domain processing – DDS and the IDFT

249

7.1

249 250 252 254 256 257 258 258 260 261 262 263 263 264 265

7.2

7.3

7.4 7.5 8

Summary References

ix

Fundamental concepts 7.1.1 The inverse discrete Fourier transform (IDFT) 7.1.2 Weighted phase sequence summation 7.1.3 Dynamic spectrum control and the metaparameter 7.1.4 Aliasing control and the mitigation of Gibbs phenomenon 7.1.5 Time division multiplexing (TDM) Contiguous harmonic phase generation and the IDFT 7.2.1 Harmonic phase accumulation 7.2.2 Harmonic phase offset 7.2.3 Amplitude accumulation Non-contiguous harmonic phase generation 7.3.1 Phase multiplication 7.3.2 Modulo integer multiplication Summary References

Hardware implementation architectures

266

8.1

267 267 268 272 273 274 275 277 280 283 284 286 289 289 289 293 296 296 299 302 302

8.2 8.3

8.4

8.5

Processing techniques and design considerations 8.1.1 Pipelined and parallel processing 8.1.2 Sample and block pipelining 8.1.3 Time division multiplexing 8.1.4 Arithmetic and modulo accumulation 8.1.5 High speed binary addition 8.1.6 Wavetable memory architectures 8.1.7 Vector memory Partitioned phase accumulation Sinusoidal phase–amplitude mapping 8.3.1 Linear phase interpolation 8.3.2 Trigonometric identity phase interpolation Interpolated vector memory 8.4.1 Linear interpolation architecture 8.4.2 Cubic interpolation architecture 8.4.3 Interpolated vector memory design considerations 8.4.4 A paged wavetable interpolation memory Waveform generation by direct computation 8.5.1 A contiguous harmonic IDFT waveform synthesiser 8.5.2 An arbitrary harmonic IDFT waveform synthesiser 8.5.3 A band- spectrum waveform synthesiser

x

Contents

8.6 8.7 9

Summary References

304 306

Digital to analogue conversion

307

9.1

311 313 315 315 317 317 318 319 319 321 321 322 323 325 327 328 330 330 332 335 336 337 338 340

9.2

9.3

9.4

9.5 9.6 Index

Error mechanisms 9.1.1 Offset error 9.1.2 Gain error 9.1.3 Settling time 9.1.4 Transition or ‘glitch’ errors 9.1.5 Linearity errors 9.1.6 DAC quantisation noise DAC dynamic specification considerations 9.2.1 Harmonic and intermodulation distortion 9.2.2 Spurious-free dynamic range (SFDR) 9.2.3 Signal-to-noise ratio (SNR) The reconstruction filter 9.3.1 Frequency and phase response 9.3.2 Filter implementation – ive or active? 9.3.3 Signal distortion pitfalls – maintaining SFDR 9.3.4 Reconstruction filter design considerations – hints and tips Supplementary analogue design considerations 9.4.1 The DAC reference voltage and output amplifier 9.4.2 Switched attenuation and output level control 9.4.3 DC offset and output dynamic range considerations 9.4.4 The output drive amplifier 9.4.5 Square and pulse waveforms Summary References

341

Preface

Most electronic design engineers, irrespective of being the ‘analogue’ or ‘digital’ variety, are occasionally faced with the task of deg an oscillatory signal generator with particular implementation constraints, control and performance requirements. These requirements might include extremely low distortion, unusual ‘application specific’ waveshape, wide frequency tuning range, low temperature drift, and so on. Historically, such a task will have been tackled with a wholly analogue design, possibly augmented by digital control, where extremely high levels of performance are evident in some cases. If we take high-end audio test instrumentation as an example, the now legendary Hewlett Packard HP8903B and Audio Precision AP1 audio test sets both use digitally controlled analogue state variable oscillators to generate extremely low distortion sine waves. The state variable analogue oscillator is effectively an analogue computer model designed to compute solutions of a second-order differential equation. A specific class of solution (under certain parametric conditions) is a continuous sinusoidal oscillation. These generators are outstanding examples of what can be achieved with innovative analogue design. However, the world is becoming increasingly digital and very high levels of digital processing power can be implemented at relatively low cost. Various ‘all digital’ waveform generation techniques are therefore now practicable; and when all of their advantages are weighed up against the disadvantages (yes, digital processing is not necessarily a panacea to guarantee ideal performance), they nearly always represent the best solution. This approach is reinforced, if not driven, by the ever-improving performance of commercial digital to analogue conversion (DAC) devices as measured by their spurious-free dynamic range (i.e. distortion) and bandwidth. It is not unreasonable to state that the integrated DAC is the foremost enabling technology for nearly all applications of digital waveform generation. Exceptions to this observation apply to purely digital signals, which exist as a discrete-time sequence of binary numbers representing the signal waveform samples. Electronic signals are often described as waveforms, indicating the time domain image observed when the signal is measured with an oscilloscope. A signal produced by an electronic signal generator may be defined as a periodic (or aperiodic), timevarying voltage or current. The corresponding shape function can be described (or approximated to some level of accuracy) by a causal mathematical function. This definition suggests a generation method where the underlying mathematical function which describes the waveform is effectively computed in real time by analogue or digital means. The simplest and most widely used waveform is the sine wave, whose

xii

Preface

corresponding mathematical function may be computed by various well-known analogue methods, digital recursive algorithms and so-called ‘direct digital synthesis’ (DDS). Classical non-sinusoidal, so-called ‘function’ waveforms include the sawtooth, triangle, square and pulse waveforms; each having a simple piecewise-linear discontinuous mathematical description. These waveforms can also be generated using an analogue computer model so as to have a waveshape which changes according to a waveshape modulation parameter. For example, a pulse waveform whose duty-cycle (i.e. the ratio of the waveform’s ‘on’ time to the total waveform period) changes according to the value of some parameter, although the waveform’s frequency remains constant. These waveforms suffice for many applications, but increasingly signals with -defined waveshape (or spectrum) are required in complex electronic systems as test stimuli, excitation, control or modulation signals. We generalise signals with defined waveshape as arbitrary waveforms and this book is primarily concerned with investigating digital techniques for their generation. Further examples of arbitrary waveform application include:

communication system carrier modulation; transducer excitation signal generation; medical and related imaging signal emulation; signal emulation in complex test instrumentation; radar return signal simulation; electronic warfare adaptive signal generation; control system diagnostic excitation; multi-tone audio system testing; computer music synthesis.

Many books have been written on signal generation by purely analogue means, such as phase shift and state variable oscillators or analogue computer function generators. Indeed, the first electronic signal generators, whether laboratory instrumentation or bespoke, were completely analogue systems, and only much later augmented by various forms of digital control. Over time, these techniques evolved to allow the generation of so-called ‘function waveforms’ (e.g. triangle, sawtooth and pulse) in addition to the ubiquitous sine wave. Indeed, some novel designs were capable of generating rudimentary arbitrary waveforms by purely analogue means according to a piecewiselinear shape specification. The HP3314A is one example of such a commercial laboratory signal generator. However, analogue techniques have always been beset by the same fundamental problems – thermal instability, the need for periodic recalibration, lack of control flexibility and limited waveform shape or corresponding spectrum specification. Before the emergence of DSP techniques, non-sinusoidal waveforms were generated by analogue computation models such as the voltage controlled function generator. Subsequently, digital control of key parameters was realised by using a digital to analogue convertor (DAC) to translate from the digital to analogue domain, allowing computer control of the signal generation process. Today, digital signal generation is a cornerstone function in many modern analogue and DSP systems. Novel DSP

Preface

xiii

techniques enable the generation of essentially any waveform shape, and provide independent control of waveshape, frequency, phase offset and amplitude. These techniques have evolved from the well-established methods of phase accumulation and phase–amplitude mapping, which have hitherto been widely applied to the generation of sine wave signals through DDS. Recursive digital techniques have also been applied to sine wave synthesis, but while having distinct advantages in some applications, they lack the flexibility of the phase accumulation approach. They are, however, well suited to many application areas due to their simplicity and low computational cost. This book investigates signal generation techniques based on phase accumulation and phase–amplitude mapping. These ‘all-digital’ techniques enable the generation of sinusoidal and arbitrary waveforms with -programmable waveshape, frequency, phase offset and amplitude. These powerful, yet flexible, techniques synthesise waveforms whose shape (and hence corresponding spectrum) can be defined according to a time or frequency domain specification. Furthermore, with appropriate phase–amplitude mapping, the synthesised waveshape can be varied according to a control parameter in real time. Multiple waveform generators are easily synchronised, and with programmable phase offsets generate polyphase waveforms or quadrature IQ sine wave constellations. The true utility of arbitrary waveform generation can be appreciated when we consider that a waveform’s instantaneous amplitude may correspond to any parameter in a digital or analogue system, whether as a test or control signal. For example, to control the set point of a servo mechanism, the instantaneous amplitude or phase of a carrier signal or the forcing function is applied to evaluate a control system’s response. Motivation for this book has come in part from observations of the currently available signal generation literature. Many excellent works have been written on the digital generation of sinusoidal signals using DDS and related techniques. However, there is a notable deficiency in the area of non-sinusoidal or arbitrary waveform generation using purely digital techniques. Several published texts have dealt with waveform generation in the field of computer music, and these can be considered as special cases of the techniques described here. This book endeavours to address the gap by providing a treatise on both sinusoidal and arbitrary waveform generation that incorporates tutorial and hardware implementation descriptions at the functional block level. It is this latter material which is intended to assist the engineer or system architect who has the task of deg a bespoke waveform generator for a specific application. Synthesis algorithms are presented as signal-flow block descriptions and are deliberately abstracted from specific hardware or software implementation technologies (e.g. FPGA or DSP code). However, generic throughput enhancement techniques such as arithmetic pipelining and parallel memory architectures are discussed. Accordingly, it is assumed that practitioners who are suitably ‘skilled in the art’ can implement and optimise these signal flow descriptions in a hardware or software technology appropriate to their application. It is reasonable to suggest that many of the suggested hardware architectures, and the underlying synthesis techniques which they implement, are ‘solutions looking for a problem’. Hopefully, this book will enable the reader to find these techniques a good home, or at the very least, provide food for thought.

xiv

Preface

We begin with a review of key definitions, historical context, classical analogue waveform generation and the conceptual and mathematical foundations pertinent to digitally generating electronic signals. The text then presents a detailed review of sine wave synthesis algorithms beginning with recursion and finally progressing to sinusoidal direct digital synthesis (DDS). This lays the essential foundations required for an understanding of phase accumulating arbitrary waveform generation – the focus of this book. The figure below illustrates the flow and interconnection between chapters. To supplement the written material and to assist the reader in ‘what happens if’ design simulation, Mathcad models are available that compute qualitative performance metrics for various configurations of the techniques presented. Mathcad models are also used to generate the graphical plot figures used throughout the book to assist communication of key ideas. These models are available for free from www.cambridge.org/ symons, and from the author’s website www.petesymons.com/dwg.

Preface

xv

Acknowledgements

I would wish to send my heartfelt thanks to Karen, my long-suffering wife, without whose love and encouragement this book would certainly not have been written; to Chris, Ben and Jenny for making me so proud; to my oldest friend Mike McNabb for providing useful on writing style and always making me laugh; and finally, Hannah Eustace for her detailed critiques of several draft chapters from a non-technical perspective. I dedicate this book to the memory of my father, Bob Symons, who both started and fuelled my love of electronics as a young boy who was always taking the back off the television set to see how it worked; and Bob Denson – my ‘Uncle Bob’ – simply the nicest and most decent person I have ever known.

Glossary of

( are grouped as used in the analysis.) A B b C D εa(n) t f τ f0 fo f(t) fs T βR

y(t) or x(t) X( f ) θ ϕ(t) ϕw(t) 〈a〉b (a, b) M I F ϕ(n)

waveform amplitude scaling factor. post-DAC low- reconstruction filter 3 dB bandwidth. number of amplitude sample bits. waveform crest factor – ratio of waveform peak to RMS amplitude. waveform duty-cycle – ratio of waveform ‘on’ time to period. amplitude error sequence. continuous-time variable. waveform or signal frequency in hertz. waveform period equivalent to the reciprocal of waveform frequency in hertz. fundamental frequency, typically of a harmonic series. waveform generator output frequency. continuous-time instantaneous frequency in hertz. sampling frequency (or rate) in hertz. sample period (or interval) equivalent to the reciprocal of sampling frequency in hertz. the oversampling ratio between the processing sample frequency fs and an equivalent sample frequency corresponding to twice the bandwidth of the post-DAC reconstruction filter B. continuous-time waveform amplitude signal. continuous complex amplitude spectrum. waveform phase offset (typically in radians). continuous-time instantaneous phase. wrapped continuous-time instantaneous phase. ‘a modulo b‘ – the remainder after repeated subtraction of b from a until (ab) < b. greatest common divisor between a and b. phase accumulator word length – 2M possible phase states. phase accumulator integer component word length. phase accumulator fraction component word length. instantaneous discrete-time phase sequence.

xviii

Glossary of

ϕI(n) ϕF (n) α(n) φ φ(n) Λ ϑ(n) Ak θk Hk Nh Ns S[a] W[a] L PN (x) P p(n) PP (n) γ(n)

integer component of discrete-time instantaneous phase within a fractional phase representation. fraction component of discrete-time instantaneous phase within a fractional phase representation. rational fraction interpretation of ϕF(n). phase increment. discrete-time phase increment sequence. number of sinusoidal DDS amplitude spectrum spurs. discrete-time phase dither sequence. kth element of the IDFT harmonic amplitude vector. kth element of the IDFT harmonic phase offset vector. kth element of an arbitrary waveform band-limiting amplitude response. number of harmonics in a harmonic waveform specification. number of samples in a particular computation. ath element of a sinusoidal wavetable. ath element of an arbitrary waveform wavetable. wavetable length in samples. Nth-order Lagrange interpolation polynomial. number of bits in a wavetable page address – 2P wavetables. wavetable page address sequence. P-bit integer wavetable page index sequence component. F 0 -bit fraction wavetable page index sequence component.

1

Introduction to waveform generation

Systematic generation of periodic signals with electronically controlled frequency, phase, amplitude and waveform shape (or waveshape) is ubiquitous in nearly every electronic system. The sinusoidal local oscillator in a super-heterodyne radio receiver is a simple example of a signal source whose controllable frequency tunes the receiver. Another example is a step input waveform (e.g. a square wave) that allows us to measure the step response of a closed-loop control system (e.g. rise time, fall time, overshoot and settling time) under controlled excitation conditions. A more complex ‘staircase’ input waveform allows us to measure step response at particular points over the system’s dynamic range and is useful for investigating non-linear behaviour. The progressive migration towards ‘software defined’1 systems across all application domains is driving the development of high performance bespoke digital signal generation technology that is embeddable within a host system. This embedding can take the form of a software code or a ‘programmable logic’ (e.g. FPGA) implementation depending on speed, with both implementations satisfying the software definable criterion. Today, applications as diverse as instrumentation, communications, radar, electronic warfare, sonar and medical imaging systems require embedded, digitally controlled signal sources, often with challenging performance and control requirements. Furthermore, many of these applications now require signal sources that generate non-sinusoidal waveforms that are specified according to a precisely defined waveshape or spectrum function that is peculiar to the application. Moreover, in addition to conventional frequency, phase and amplitude control, these signal sources can have vastly increased utility by providing parametric and thereby dynamic control of waveshape or corresponding spectrum. As we will see, there are several digital waveform generation techniques that provide this functionality. After reviewing introductory theoretical material and some established analogue approaches, this book focuses on purely digital techniques for generating waveforms with programmable frequency, phase, amplitude and most importantly waveshape. The specification and dynamic control of waveshape (and hence the corresponding spectrum) are relatively new topics in the published literature where hitherto the emphasis has largely been on sine wave generation. We call such programmable waveforms arbitrary waveforms. The utility of a waveform with an 1

We take ‘software defined’ to describe a system which is configurable through any locally stored digital data (e.g. software program code, FPGA firmware or memory-based lookup tables).

2


arbitrary waveshape or spectrum is apparent when we consider that the instantaneous amplitude of that waveform can be engineered to control or emulate any parameter in a digital or analogue system. Some typical examples include: set the physical position or velocity profile of a servo mechanism; set the operating point of any parametric control system (e.g. the current through a laser diode or the temperature of an oven); emulate a parametric sensor output or other ‘real-world’ signal for test or diagnostic debug purposes; modulate the instantaneous amplitude, frequency or phase of a carrier signal; provide an input forcing function to measure the time or frequency response of a linear or non-linear system. Nearly all of the arbitrary and sinusoidal waveform generation techniques presented in this book are based on the established technique of fixed sample rate phase accumulation frequency synthesis. Here a phase increment parameter controls output frequency, and a lookup table ‘phase–amplitude mapping function’ generates the amplitude waveform. This powerful technique provides intrinsically linear and independent control of frequency, phase and amplitude. It provides near instantaneous, phase-continuous frequency transitions and almost unbounded frequency control resolution. With advanced, innovative phase–amplitude mapping we can achieve dynamic control of waveshape and hence corresponding spectrum in real time. An alternative approach to controlling waveform frequency is outlined that is based upon a variable sample rate approach, but only as an adjunct to fixed sample rate phase accumulation. Generation of sine waveforms using phase accumulation and phase–amplitude mapping is well reported in the literature [1] where it is variously known as direct digital synthesis (DDS), direct digital frequency synthesis (DDFS) or the numerically controlled oscillator (NCO). In this book we adopt the DDS acronym. After reviewing sinusoidal DDS as a special case of a general paradigm, we proceed to develop a generalised DDS form that synthesises arbitrary waveforms (including sine waves) according to a time or frequency domain specification. In this book, we denote this as DDS arbitrary waveform generation or DDS AWG. For completeness, we include a cursory review of recursive sinusoidal oscillators as they offer a computationally efficient method for digitally generating sine waveforms, albeit with some performance limitations that we compare across several algorithms. The underlying theory and conceptual development of recursive oscillators also serves as an introduction to sinusoidal DDS. We endeavour to combine a general reference text and a designer’s guide that will help appropriately skilled engineers to design bespoke digital waveform generator implementations in technologies appropriate to their application. The reader is assumed to have an undergraduate-level understanding of basic signal processing theory. Waveform synthesis algorithms are presented as a signal-flow of arithmetic and computational block descriptions deliberately abstracted from specific implementation technologies (e.g. FPGA, ASIC or DSP code). Accordingly, it is assumed that design professionals ‘skilled in the art’ can implement and optimise these descriptions in a

1.1 Preliminaries

3

hardware or software technology appropriate to their application. Established digital hardware processing techniques that enhance throughput such as sample and block level pipelining, parallel processing and time-division multiplexing are discussed in the specific context of fast, high performance DDS AWG implementations. However, design and optimisation guidance for FPGA, ASIC or DSP software implementation is beyond the scope of this book. To supplement the written material and to assist the reader in exploring ‘what happens if’ design scenarios, we use Mathcad models to simulate the behaviour of qualitative performance metrics with variation of key design and control parameters. Mathcad models generate many of the graphical figures that are used throughout the book to assist communication of key concepts and behaviours. We use Mathcad because of its popularity, relatively low cost and the ease with which mathematical formulations can be quickly scripted, simulated and visualised in a mathematically stylistic way. These models are available for free from a website that s this book: www.petesymons.com/dwg.

1.1

Preliminaries We begin this section by outlining the chapter content of this book. We proceed to discuss the definition of a waveform and use the sine waveform to explore and develop the key elementary mathematical properties that underpin later discussion on generation techniques. We clarify other descriptive associated with electronic waveforms, such as signal and spectrum both in general and in the context of this book. Finally, we briefly summarise the historical development of digital waveform generation to help set the presented material in context.

1.1.1

Outline chapter content Chapter 1 begins by discussing the definition, important properties and key parameters of a waveform before proceeding to briefly review the historical development of digital waveform generation. We present a taxonomical grouping of electronic waveform generation techniques and discuss each of the three main subclasses concluding with an outline of the state of the art in digital arbitrary waveform generation. To provide a comparative backdrop to digital waveform generation, we review several established analogue waveform generation methods and summarise their strengths and weaknesses. Finally, we discuss some of the key application areas for bespoke standalone and embedded digital arbitrary waveform generators. Chapter 2 begins by presenting an outline of several important mathematical concepts that underpin later material. We introduce the fundamental concept of tabulating a sampled waveform in a lookup table – a concept which underpins the wavetable (a term we borrow from computer music parlance) discussed further in Chapter 4. We discuss the most important control parameters and their ideal properties, before defining qualitative performance metrics that are pertinent to all of the techniques

4


presented in the book. We use Mathcad models to quantify these metrics under various design and control parameter conditions throughout this book. In Chapter 3 we introduce the first digital waveform generation technique – the recursive sine wave oscillator – and show how this leads to a generic recursive oscillator description. We proceed to investigate several recursive oscillator structures each having a unique attribute according to a particular performance metric. We discuss implementation considerations common to all recursive oscillators and finally compare their relative properties. Chapter 4 introduces DDS sine wave generation, beginning with a discussion of phase accumulating frequency synthesis. We investigate several sinusoidal phase–amplitude mapping techniques using computer simulation of the qualitative performance metrics introduced in Chapter 2 to compare their relative performance. The wavetable is introduced together with the related concepts of phase truncation, fractional addressing and interpolated wavetable lookup. Finally, some alternative sinusoidal phase–amplitude mapping techniques are discussed. Chapter 5 generalises the material introduced in Chapter 4 and investigates DDS arbitrary waveform generation or DDS AWG. We consider methods for filling the wavetable according to different waveform specification techniques, and a fundamental aliasing error mechanism that arises when we ‘sample’ the wavetable by indexing it with a phase accumulator. Phase truncation errors are exacerbated with multi-harmonic waveforms typical of DDS AWG. One method for reducing the magnitude of these errors is the use of phase interpolation according to a fractional phase representation. We present an introductory interpolation tutorial before investigating several interpolated phase–amplitude mapping algorithms with computer simulation of their qualitative performance metrics that were introduced in Chapter 2. We discuss phase accumulating frequency synthesis with ‘analogue waveshaping’ and DDS digital clock generation. This chapter concludes with a discussion of some specific design considerations peculiar to computer music and audio applications. Chapter 6 explores several methods for dynamic ‘parameterised’ control of waveshape. We proceed to develop dynamically controlled harmonic and non-harmonic waveform generation techniques; the latter enabling the generation of band- spectra. One of the techniques investigated is equivalent to the inverse discrete Fourier transform (IDFT), and allows real-time control of the synthesised signal’s harmonic spectrum. Chapter 7 develops the concept of phase domain processing that is introduced in Chapter 4 to efficiently compute the inverse discrete Fourier transform (IDFT) as a DDS phase–amplitude mapping algorithm. This allows the generation of periodic waveforms with independently controllable harmonic amplitude and phase. Techniques for generating waveforms based upon contiguous and non-contiguous (i.e. arbitrary) harmonic series are introduced ahead of further development in Chapter 8. Chapter 8 investigates design considerations for real-time hardware implementation of the techniques presented in earlier chapters including arithmetic pipelining and parallel processing. The chapter presents several design examples, including a novel vector memory suitable for the implementation of phase and wavetable interpolation.

1.1 Preliminaries

5

The chapter concludes with some design examples of the contiguous and noncontiguous IDFT waveform generators based upon phase domain processing that are introduced in Chapter 7. Chapter 9 investigates the design considerations surrounding digital to analogue conversion, focusing on performance metrics and specifications that are peculiar to digital waveform generation applications. We conclude by investigating the post-DAC low- reconstruction filter and output signal conditioning.

1.1.2

Digital signal processing The science of all electronic signal processing is primarily concerned with representation, analysis and generation of only two types of signal: analogue or continuous-time signals and digital or discrete-time signals. From a mathematical perspective, a continuous-time signal is one whose independent time variable is continuous (i.e. ‘well-behaved’ and free from discontinuity). Conversely, a discrete-time signal is one whose independent time variable is quantised (i.e. only defined in discrete, regularly spaced steps called the sampling interval or sample period). Accordingly, the signal’s instantaneous amplitude value is only defined at discrete instants of time. The discretetime signal therefore comprises a sequence of impulse functions whose amplitude is equivalent to that of the underlying continuous-time signal at that time instant. Elsewhere, from an analytical perspective, a discrete-time signal is zero-valued. In this book we define a digital signal as a discrete-time signal that is also quantised in amplitude according to a particular number representation (i.e. number of bits). Similarly, digital control of a parameter implies that the parameter can be changed only at discrete-time intervals. Digital generation of a signal therefore implies the discretetime execution of an algorithm at fixed sample intervals that processes amplitude quantised internal data values and control parameters. Historically, purely analogue signal generation techniques that operated in continuous time were prevalent; but with the progressive advances in digital hardware, digital techniques have become well established and now define the state of the art. The emergence and development of digital signal processing (DSP)2 which we define as the representation and processing of discrete-time, amplitude-quantised signals, has revolutionised the field of electronic signal generation as well as many others. Today, the availability of high speed DSP and related technologies (e.g. semiconductor memory) combined with advanced design software, enables the implementation of bespoke, highly complex signal generation systems that are software defined. Important examples of these ‘enabling technologies’ include:

2

There is a subtle, but important distinction between digital signal processing and digital signal processor, both of which use the DSP acronym. The former relates to the analytical discipline of processing quantised information in discrete-time, whereas the latter describes the hardware in which this processing takes place. In this book, we use ‘DSP’ to represent both definitions and it is assumed the diligent reader will determine context depending on the prevailing discussion.

6


software-programmable digital signal processors and microprocessors; ‘DSP optimised’ field-programmable gate arrays (FPGA); fast, high density semiconductor memory; analogue to digital convertors (ADC); digital to analogue convertors (DAC).

The ADC and DAC, whose development in performance and level of integration has paralleled that of digital hardware, provide fundamental signal processing operations. In the digital signal generation field which concerns us here, the DAC provides a crucial operation in moving from the discrete- to continuous-time domain. We should that although signals may be generated using purely digital techniques, they are often used or processed further in the analogue domain. In conjunction with a process known as reconstruction filtering, the DAC allows us to move from the discrete-time, amplitude-quantised (i.e. digital) domain to the continuous-time (i.e. analogue) domain. This is clearly a fundamental (and occasionally overlooked) operation in digital signal generation systems that are required to produce an analogue output with well-defined performance characteristics. We may digitally synthesise a signal with noise and distortion comparable with the amplitude quantisation level, only to find catastrophic degradation when converted to an analogue signal by poor design or specification of the DAC and its associated analogue signal processing.

1.1.3

Periodic and aperiodic waveforms Electronic signals are often described as waveforms, describing the wave-like variation of voltage with time that is observed when the signal is measured with an oscilloscope. The measured voltage waveform may correspond to a ‘true’ voltage signal or some other parameter (e.g. current or power) by a proxy measurement (e.g. a current probe which produces an output voltage signal proportional to the current flowing through the device). By definition, a waveform is the time domain view of an electronic signal, where we are explicitly concerned with how the signal’s instantaneous amplitude varies over time. We describe this variation as waveshape. A typical waveform produced by an electronic signal generator may be defined as a time-varying, periodic voltage whose waveshape function can be described (or approximated to some level of accuracy) by a mathematical function whose parameters control frequency, phase, amplitude and waveshape. This function can take on many forms – the sine function, an amplitude and phase weighted Fourier series or a piecewise-linear function that specifies the waveform shape as a collection of linear segments over one cycle of the waveform (e.g. a triangle or sawtooth wave). In of its time domain behaviour, a waveform can be described as either periodic or aperiodic. A periodic waveform repeats over time at a fixed interval called the period and the number of waveform cycles observed in one second is called the frequency. A waveform that is periodic over some time interval has an instantaneous frequency defined on that time interval as the reciprocal of the period. Aperiodic

1.1 Preliminaries

7

waveforms do not exhibit this property and by definition show no cyclic or repetitive behaviour over any time interval. The mathematical condition for periodicity can be stated quite simply. If a signal whose instantaneous amplitude is denoted by y(t) for all t, where t is the independent time variable, then y(t) is periodic if yðtÞ ¼ yðt þ τÞ for all t,

ð1:1Þ

where τ is defined as the period of the signal. To help illustrate these concepts, Figure 1.1 provides some examples of periodic and aperiodic waveforms as plots of instantaneous amplitude y(t) against time t. Figures 1.1a to e illustrate some classic periodic ‘function’ waveforms – the sine wave, triangle wave, sawtooth wave, half-wave rectified sine wave and full-wave rectified sine wave, respectively. Figure 1.1f illustrates a real-world example of a human ECG waveform indicating normal cardiac function. This is essentially a periodic waveform and a good example of a complex waveform that can be synthesised at a given frequency (i.e. simulated heart rate) using the DDS AWG techniques to be described. Using DDS AWG it is possible to conceive of a cardiac waveshape that changes with frequency, perhaps to emulate a particular anomalous medical condition for training or equipment verification purposes. Figures 1.1g through 1.1l illustrate several aperiodic waveforms. Clearly, some of these waveforms exhibit some underlying periodic behaviour, but do not satisfy the periodicity criterion expressed in Eq. (1.1). Figure 1.1g shows an aperiodic waveform composed of a sinusoid with occasional 180 phase inversions. If these phase inversions are randomly distributed (as may apply if they correspond to binary data encoding) then this type of waveform is aperiodic for all time. Figure 1.1h is a sinusoid with some additive white noise. When integrated cycle by cycle over a sufficiently long period the mean signal approaches a pure sinusoid and is therefore periodic, but the ‘cycle to cycle’ waveform is strictly aperiodic due to the localised noise variance. Figure 1.1i shows a periodic sinusoid, but with exponentially decaying amplitude typical of the impulse response of an under-damped second-order system. These last three examples illustrate that although a signal may be strictly aperiodic (in an analytical sense) it can have underlying periodic behaviour – in these examples a sinusoid signal that is modified by binary phase modulation, additive noise or an exponential amplitude envelope. Figure 1.1j shows a pure white noise signal which is aperiodic and has a random amplitude distribution. Figure 1.1k shows an exponentially asymptotic curve with a small additive signal comprising a sum of sinusoids with non-harmonic frequencies. Figure 1.1l shows a waveform segment comprising the sum of four sinusoids with nonharmonic frequencies. Such a waveform is strictly periodic with a period equal to the least common multiple of the constituent sinusoid periods. However, as the composite period can be extremely large when more than two sinusoids with rational frequencies are added, we can say that such waveforms are ‘quasi-aperiodic’. We note at this point, that some DDS AWG techniques (as discussed in Chapter 6, for example) are based on

8


Periodic waveforms y(t)

y(t)

y(t)

t

t

(a)

t

(b)

y(t)

(c)

y(t)

y(t)

t

t

(d)

t

(e)

(f)

Aperiodic waveforms y(t)

y(t)

y(t)

t

t

(g)

t

(h)

y(t)

(i) y(t)

y(t)

t

(j)

t

(k)

t

(l)

Figure 1.1 Some simple examples of periodic and aperiodic waveforms.

the weighted summation of sine waves with non-harmonic frequencies and can therefore easily generate such quasi-aperiodic waveforms. From a waveform generator perspective, periodic waveforms exist for as long as the generator is switched on and running. Truly aperiodic waveforms are by definition non-repetitive and should strictly be considered as ‘single-shot’ signals initiated by some trigger event and therefore existing for a predefined time. Aperiodic waveforms, such as Figure 1.1i, become periodic if they are repeated over some interval. Quasi-periodic waveforms are ‘locally periodic’ waveforms that are arranged to exhibit infrequent transient anomalies that emulate some real-world signal behaviour (e.g. a short-duration transient ‘spike’ or ‘drop out’). An example of a quasi-periodic waveform is a sine wave where 1 in every 10 000 cycles exhibits the pre-defined

1.1 Preliminaries

9

transient anomaly. Generation of such quasi-periodic waveforms is straightforward using DDS AWG where we dynamically change the phase–amplitude mapping function according to a waveshape control parameter.

1.1.4

Introducing the sine wave – properties and parameters A fundamentally important periodic waveform is the sine wave. Many physical systems that exhibit resonant or oscillatory behaviour do so with a nominally sinusoidal motion. A classic example is the mass-spring oscillator, which oscillates with an exponentially decaying sinusoid following an impulsive disturbance. In electronic instrumentation, swept frequency sinusoids are used to measure the frequency and phase response of linear systems. Similarly, high purity fixed frequency sinusoids are used to characterise the distortion behaviour of quasi-linear electronic systems (e.g. amplifiers or analogue to digital convertors). In these applications, spectral purity, frequency and amplitude stability are essential attributes. A sinusoidal oscillation whose instantaneous amplitude at time t we denote by y(t) is defined by the cosine function, thus: yðtÞ ¼ Acosð2π ft þ θÞ,

ð1:2Þ

where A denotes the oscillation amplitude, f denotes the cyclic frequency in hertz3 (or the number of waveform cycles per second) and θ denotes the initial phase or phase offset in radians relative to t ¼ 0. Applying the periodicity criterion expressed in Eq. (1.1) to y(t), we obtain the expression A cos (2π ft þ θ) ¼ A cos (2πf (t þ τ) þ θ). Since the angular period of a cosine (or sine) function is 2π radians, this equality holds for all t if 2π fτ ¼ 2π or f ¼ 1/τ, thereby proving the reciprocal relationship between sinusoid period and frequency. The phase offset determines the time locations of the sinusoid maxima and minima relative to t ¼ 0 and can be equated to a time shift applied to y(t). To see this, let y(t) be delayed in time by one quarter of a period or τ/4. We then have y(t τ/4) ¼ A cos(2πf (t τ/4) þ θ ) ¼ Acos(2πft π /2 þ θ ) since f ¼ 1/τ. This is equivalent to the original sinusoid y(t) but with an additional phase offset of π/2 radians. We also observe that since the sine and cosine functions are periodic with angular period 2π radians, a phase offset of θ 2kπ, where k is an integer, is indistinguishable from a phase offset of θ. We therefore constrain the phase offset to the interval θ 2 [0, 2π) radians. Figure 1.2 illustrates the cosine waveform and its parameters. Phase offset is exemplified by showing a second dashed sinusoid waveform having a phase offset of θ ¼ π/2 radians relative to the cosine waveform. The amplitude parameter A is a scaling factor which determines how large the cosine waveform will be. Since the cosine function oscillates between þ1 and 1, y(t) 3

The standard unit of frequency is the hertz (equivalent to sec-1) and was formally established in 1930 by the International Electrotechnical Commission (IEC) in honour of Heinrich Hertz for his pioneering work on radio waves.

10


Figure 1.2 A sinusoidal waveform and its parameters.

oscillates between þA and A. There are three amplitude measurements which concern us here – peak pffiffiffiamplitude A, peak-to-peak amplitude, App ¼ 2A and the RMS amplitude, which is A= 2 for the cosine or sine waveform and used when calculating the electrical power of a sinusoidal voltage waveform dissipated in a resistive load. The mean value of the cosine or sine waveform taken over an integer number of cycles is precisely zero (assuming zero DC offset). The waveform crest factor is defined pffiffiffias the ratio of peak amplitude to RMS amplitude and for the cosine or sine wave is 2. A waveform’s crest factor is important when attempting to measure its RMS amplitude, for example, with an electronic AC voltmeter. Many RMS measuring AC voltmeters have an accuracy derating factor which is a function of the signal crest factor being measured. Knowledge of the worst signal case waveform crest factor is important when specifying the headroom relative to RMS before the onset of clipping in both analogue and digital processing chains. In the context of digital waveform generation, crest factor is important since the signal to noise ratio (SNR) performance metric is defined relative to the RMS signal amplitude. Waveforms with a high crest factor have a reduced RMS amplitude to avoid peak clipping with a given amplitude dynamic range (i.e. number of DAC bits). Therefore, for a given noise amplitude, high crest factor waveforms have lower SNR. These amplitude measurements are not just peculiar to sinusoids, they are applicable to all periodic waveforms and it is instructive to outline their interrelationship for other simple periodic waveforms. Figure 1.3 tabulates the mean and RMS amplitudes and crest factors of several simple waveforms as a function of normalised peak amplitude.

1.1.5

Instantaneous phase and frequency The argument of the cosine function in Eq. (1.2) is called the instantaneous phase ϕ(t), and for a constant frequency sinusoid is given by:

11

1.1 Preliminaries

Waveform

Mean amplitude

RMS amplitude

Crest factor

Crest factor (dB)

0

A 2

2

3

A 2

2

3

A 2

2

6

0

A 3

3

4.8

0

A 3

3

4.8

0

A

1

0

t T

T t

20 log

A

2A A

p A

A

p

A

A

A

A

t T

ætö Aç ÷ èT ø

A

T t

Figure 1.3 Amplitude and crest factor definitions for some common waveforms.

ϕðtÞ ¼ ð2π f t þ θÞ:

ð1:3Þ

We may now express y(t) as a function of ϕ(t) and obtain y(t) ¼ cos(ϕ(t)). The instantaneous frequency f(t) is defined as the derivative of the instantaneous phase with respect to time and given by: 1 d f ðtÞ ¼ ðϕðtÞÞ: ð1:4Þ 2π dt When frequency is constant, as in Eq. (1.2), this expression yields the trivial case f (t) ¼ f as we would expect. Equation (1.4) indicates that the instantaneous phase can be expressed as the integral with respect to time of the instantaneous frequency, thus: ðt ϕðtÞ ¼ 2π f ðτÞ dτ þ ϕð0Þ, ð1:5Þ 0

12


f

f (t ) = 2pft df = 2pf dt

fw (t ) = f (t ) 2p t =0

1 f

2p

t

Figure 1.4 Constant frequency unwrapped phase function ϕðtÞ and its 2π modulus ϕw ðtÞ.

where ϕ(0) is the initial phase at t ¼ 0 and so ϕ(0) ¼ θ. For the constant frequency case where f(t) is a constant, Eq. (1.5) reduces to Eq. (1.3). The definitions of instantaneous phase and frequency are essential to the development of discrete-time phase accumulation frequency synthesis which underpins DDS. We develop these concepts further in Chapters 2 and 4. The instantaneous phase function of a sine wave is bounded on the interval [0, 2π). This is known as the wrapped phase ϕw(t) with ϕw(t) 2 [0, 2π) and is consistent with the trigonometric identity cos(x) cos(x 2kπ), where k is any integer. The unwrapped phase is a continuous unbounded function of t with ϕ(t) ¼ 2πft þ θ. Figure 1.4 illustrates both wrapped and unwrapped phase functions of time. We observe that the wrapped phase ϕw(t) is equivalent to the unwrapped phase modulo 2π. The modulo function ‘a modulo b’ or ‘a mod b’, which we denote as 〈a〉b, is defined as the remainder after the repeated subtraction of b from a until (a – b) < b. It is the ‘reverse engineering’ of this process that underpins phase accumulating frequency synthesis. Let us imagine an unbounded (i.e. unwrapped) phase function kt which is a nonoscillatory ramp function of constant slope for all t. If we now compute the modulo 2π representation, we observe a periodic sawtooth phase oscillation of amplitude 2π and frequency k/2π Hz. If k ¼ 2πf, the frequency of this sawtooth is simply f Hz. The important point to observe here is that our oscillating sawtooth is a phase function of time and requires further processing if we wish to generate some other waveform (e.g. a sine wave). If we now consider the sine function as simply a phase-to-amplitude conversion or mapping operation, we reveal the foundations for the systematic generation of arbitrary waveforms using digital techniques.

1.1.6

From phase to amplitude – the waveform function Defining our sinusoid waveform function as the cosine of an instantaneous phase function is an important representation since it encourages us to think of instantaneous phase and amplitude calculations as distinct and independent operations. We can develop this a little further and consider a general periodic waveform function g(x) where x is an independent phase variable and g(x) is periodic on the interval [0, 2π).

1.1 Preliminaries

13

2

y(t)

1

0

-1

-2

0

1

2

3

t (sec) Figure 1.5 A four harmonic approximation to the sawtooth waveform. An ideal sawtooth function is shown for comparison (dashed line); it requires an infinite harmonic series to represent it due to the periodic discontinuities.

We may then represent a corresponding time-varying oscillatory waveform as y(t) ¼ g(ϕ(t)), where ϕ(t) is a phase function of time whose slope determines the oscillation frequency. In our earlier sinusoid example, we would therefore have g(x) : x ! cos(x), x 2 [0, 2π). The constant frequency instantaneous phase function will always be of the form ϕ(t) ¼ (2πft þ θ), which is an unbounded ‘non-oscillatory’ ramp function of constant slope 2πf. It is the periodic behaviour of the cosine function over a 2π phase argument that causes the corresponding oscillation in cos(ϕ(t)) at frequency f and phase offset θ. The important point here is that this representation allows any periodic waveform to be specified by defining a corresponding periodic waveform function g(x), with phase argument x. To see this, let us consider the first four harmonic of a Fourier series which approximates a sawtooth waveform. The instantaneous amplitude y(t) is given by 1 1 1 yðtÞ ¼ sinð2π f t Þ þ sinð2πð2f Þt Þ þ sinð2πð3 f Þt Þ þ sinð2πð4 f ÞtÞ: 2 3 4

ð1:6Þ

The waveform represented by Eq. (1.6) is plotted in Figure 1.5 for a frequency of 1 Hz and clearly shows the approximate4 sawtooth waveshape. (For comparison, an ideal sawtooth waveform is also shown superimposed.) We can reformulate Eq. (1.6) as a function of a phase argument x where x ¼ 2πft, and f is the fundamental frequency.5 We then obtain:

4

5

The approximation to an ‘ideal’ sawtooth waveshape is improved as we add more harmonic to the Fourier series. The fundamental frequency is the ‘base frequency’ of a harmonically related series of sinusoids. For a fundamental frequency of f, this would comprise harmonic sinusoids of frequency 2f, 3f, 4f, etc.

14


1 1 1 gðxÞ ¼ sinðxÞ þ sinð2xÞ þ sinð3xÞ þ sinð4xÞ: 2 3 4

ð1:7Þ

Equation (1.7) is a four harmonic sawtooth waveform approximation function that accepts a phase input and produces a corresponding amplitude output – it can be thought of as a ‘phase to amplitude conversion’ function. If we substitute the phase variable x in Eq. (1.7) with the instantaneous phase function ϕ(t) we again obtain a waveform expression as a function of time, thus: 1 1 1 yðtÞ ¼ gðϕðtÞÞ ¼ sinðϕðtÞÞ þ sinð2ϕðtÞÞ þ sinð3ϕðtÞÞ þ sinð4ϕðtÞÞ, 2 3 4

ð1:8Þ

and observe that Eqs. (1.8) and (1.6) are equivalent since ϕ(t) ¼ 2π ft. The important observation here is that the Fourier series g(x) can approximate any periodic function over a suitable interval (e.g. [0, 2π)). Increasing the number of in the series improves the approximation. In the digital domain we can simplify the phase–amplitude mapping operation by tabulating the g(x) waveform function over a range of phase values as a lookup table or so-called wavetable of ‘phase–amplitude’ data points, with the table address representing normalised phase over (usually) one cycle. The wavetable concept is a cornerstone technique for efficiently implementing the phase–amplitude mapping operation in DDS arbitrary waveform generation. We investigate and develop the wavetable concept further in Chapter 4.

1.1.7

Signal definition – waveform or spectrum? Before we investigate specific waveform generation methods, it is important to clarify some of the used throughout this book to describe electronic signals. We use the waveform, signal or spectrum interchangeably depending on the prevailing context. We use ‘waveform’ to describe a time domain view of an electronic signal and ‘spectrum’ to describe the corresponding frequency domain view. We use ‘signal’ as a general description of any fixed or time-varying electronic information. The method used to specify a generated signal depends upon which domain it is required to be precisely defined in – time or frequency. It is also possible to conceive of other domains in which a signal should be precisely defined. For example, a quasi-quadrature signal comprising two sine waves might require exact definition in phase. However, for now we shall concern ourselves with signal specification in the time or frequency domain. The Fourier transform provides a two-way mathematical relationship between the continuous-time and frequency domains as illustrated in Figure 1.6. Using the Fourier transform we may represent any periodic, continuous-time waveform x(t) as a continuous spectrum of complex numbers X( f ) whose magnitude and phase represent the amplitude and phase of the constituent frequency components (e.g. a sequence of harmonic sinusoids). We may therefore think of the Fourier transform as an analysis operation. Conversely, a complex spectrum may be transformed into a corresponding periodic time domain waveform using the inverse Fourier transform which can be thought of as a synthesis operation.

15

1.1 Preliminaries

Fourier Transform ¥

X(f ) =

ò x(t )e

- 2pjft

dt

-¥

x(t)

Frequency Domain

Time Domain t

X(f )

f0

2 f0

3 f0

t f0 = 1 t

4 f0

f Inverse Fourier Transform x(t ) =

¥

ò X ( f )e

2pjft

df

-¥

Figure 1.6 Fourier transformation between the continuous-time and frequency domains.

The Fourier transform may also be expressed in a discrete form (the discrete Fourier transform or DFT) which we consider in Chapter 2, where both time and frequency variables are discrete quantities. This form is essential to the specification and real-time generation of arbitrary waveforms in the frequency domain. The Fourier transform helps to show that time and frequency domain representations are equally important when describing and specifying electronic signals. For example, the stimulus to measure the transient response of a control system is best specified according to a waveform shape function, that is, a time domain specification. Conversely, a signal required to emulate a complex harmonic or intermodulation distortion spectrum is best specified according to the amplitude of its constituent frequency components (e.g. harmonic amplitude parameters in the case of a harmonic distortion spectrum).

1.1.8

Signal specification – time or frequency domain? Electronic signals may be specified in the time or frequency domains. A time domain specification is primarily concerned with waveshape, whereas a frequency domain specification is concerned with spectrum. There are several methods for specifying an arbitrary waveform in the time domain that concern us here. They all tabulate a waveform as a vector of amplitude samples at equally-spaced phase points which correspond to the lookup table addresses. At the simplest level, a waveform can be ‘hand drawn’ as a graph of amplitude against time (and hence phase) using appropriate -interface software, possibly augmented by

16


filtering to smooth discontinuities. For periodic waveforms, it is important to ensure that the beginning and end points are phase-continuous to avoid a periodic amplitude discontinuity when the waveform is regenerated. (Conversely, if we are specifying a ‘single-shot’ aperiodic waveform, phase continuity between the waveform beginning and end points is unimportant.) A refinement of the ‘drawn by hand’ approach is to specify a piecewise-linear approximation to a desired waveshape as a set of phase– amplitude ‘way points’ that are interconnected by interpolating line segments before tabulation. Finally, the most precise time domain specification method is to express the desired waveform as a causal mathematical function of an independent phase variable. Tabulated waveform samples are then calculated by computing this function at appropriate phase points that correspond to the lookup table addresses (or, equivalently, waveform phase points). There are broadly two methods for specifying an arbitrary waveform in the frequency domain. The first is applicable to lookup table based waveform generation which computes the tabulated phase–amplitude samples in non-real-time using the inverse discrete Fourier transform (IDFT) of a harmonic amplitude and phase parameter specification. The second method computes the IDFT of a harmonic amplitude and phase specification in real time. A variation of this approach sums a non-harmonic set of sine waves with parameterised amplitudes,6 effectively executing a ‘quasi-IDFT’ linear combination. Accordingly, this technique produces waveforms with non-harmonic spectra. It is instructive to observe the similarity in waveshape between two signals with relatively large differences in their spectra. This example serves to illustrate the difficulty in precisely controlling a spectrum from waveshape – there is a non-intuitive correspondence between the two domains. Figure 1.7 shows two nominally sinusoidal waveforms and their corresponding spectra. The first waveform is a pure sinusoid with no harmonic components and is distortion-free. It is represented by a single spectrum line in the frequency domain that corresponds to the waveform frequency. The second waveform shows a sinusoid with high harmonic distortion corresponding to second and third harmonics with amplitudes that are 20 dB and 30 dB down on the fundamental, respectively. The two waveforms are just distinguishable in of their shape, but clearly have very different spectra. To specify the distorted sine waveform as a shape function (i.e. time domain specification) with sufficient precision to accurately control the relative harmonic amplitudes would be very difficult and error-prone, not to mention non-intuitive. It is apparent that significant changes in a waveform’s spectrum can produce subjectively small changes in perceived shape. How would you accurately specify the waveshape in Figure 1.7 when the third harmonic amplitude was changed to 35 dB down on the fundamental? Clearly, specifying the distorted waveform as a spectrum and then applying the inverse Fourier transform to compute the time domain waveform is the optimal way.

6

Since we are dealing with a non-harmonic series of sine waves, the idea of a fixed phase offset for each sine term has no meaning. An exactly harmonic sine series is intrinsically ‘phase-locked’.

17

1.1 Preliminaries

A

1

0 dB

0.5 0 - 0.5 -1

0

1

2

A

1

f

f0

3

t

1 f0

0 dB

0.5 0

-20 dB

- 0.5 -1

-30 dB 0

1

1 f0

2

t

3

f0

2 f0

3 f0

f

Figure 1.7 Two waveforms with similar waveshape but very different spectra.

1.1.9

A brief history of digital waveform generation A landmark in the history of hardware-oriented digital waveform generation is the pioneering paper by Tierney, Rader and Gold published in 1970 titled A digital frequency synthesizer [2]. This paper presented a mathematical development of discrete-time sine wave synthesis by phase accumulation and table lookup phase– amplitude mapping – or what we now generalise as direct digital synthesis (DDS). The paper begins by considering a discrete-time recursive oscillator based upon a differential equation whose z-transform has poles on the unit-circle. The discussion proceeds to formulate a discrete-time complex exponential (i.e. a complex sinusoid) function of a frequency index and a time index. The frequency index is defined as an integer multiple of a minimum frequency which is equal to an integer fraction 1/N of the sample frequency. The authors show that computing samples of this complex exponential indexed on the frequency and time variables is equivalent to computing N equispaced points around the unit circle in the complex plane. This representation provides an elegant introduction to the fundamental concept of phase accumulating frequency synthesis. The paper continues to develop sine wave phase–amplitude mapping using lookup tables. Although the conclusion of this paper is a real-time hardware implementation using early transistor-transistor logic (TTL) technology, there are earlier examples of the phase accumulation technique being applied in computer music software applications. The ‘unit generator’ was a software-based audio generation and processing function (e.g. parametrically programmable oscillators, filters and amplifiers) conceived by Max Mathews during the development of computer music synthesis programs at the Bell Labs in the late 1950s. Unit generators could be arbitrarily interconnected or ‘patched’ by programming to form complex virtual instruments that produced audio samples when the program was run. The enormous number of operations required to compute each output sample meant that real-time synthesis was impossible. Instead,

18


the computed samples were stored on a tape or disk buffer and then ‘played back’ at the appropriate sample rate into a DAC and reconstruction filter before being amplified and fed to a loudspeaker. The first appearance of a unit generator oscillator using phase accumulation was in the MUSIC III computer programme developed by Max Mathews and Joan Miller [3] in 1960. MUSIC III was designed to execute on one of the latest generation of transistorised mainframe computers, specifically an IBM 7094 machine. The MUSIC program series was notable as the first computer software for generating audio waveforms through entirely digital synthesis and processing, albeit in non-realtime. However, the underlying technique of phase accumulation followed by table lookup phase–amplitude mapping is conceptually identical to that presented by Tierney et al. Indeed, the early unit generator OSCILI as described in [3] implements phase– amplitude mapping by linear interpolation of a lookup table containing one cycle of a pre-computed non-sinusoidal waveform. This is perhaps the earliest conceptual (albeit non real-time) example of what today we would call arbitrary waveform generation. The MUSIC range of computer programs represented a pioneering contribution to the later development of real-time ‘performance’ digital music synthesisers which initially used hardware-based waveform generation and processing. Some of the first commercially available ‘all-digital’ instrumentation signal generators appeared in the late 1980s and were marketed as arbitrary function generators (AFG) and later arbitrary waveform generators (AWG), with both in common use today. There is a generally accepted distinction between the AFG and AWG categories. An AFG is primarily intended for ‘analogue’ function generation applications with some arbitrary waveform generation capability. However, the AWG7 is primarily intended for arbitrary waveform generation with high signal fidelity (i.e. low signal distortion) and greater control flexibility. It was the ’s ability to arbitrarily specify or customise the synthesised waveform that led to the ‘arbitrary’ term to describe these instruments. The LeCroy 9100 AFG series is a typical example of these early variable sample rate instruments, and they are still in use today. They contain a high speed memory which stores an integer number of sampled waveform cycles as a table of amplitude-quantised values such that the end of the table is phase-continuous8 with the beginning. A counter clocked by a variable frequency oscillator incrementally addresses this memory to produce an amplitude-quantised discrete-time waveform sequence which is fed to a DAC and reconstruction filter to produce an analogue output signal. The synthesised waveform frequency is a function of the number of stored waveform cycles and the address counter clock frequency. The stored waveform can be programmed using software tools or selected from a set of predefined analogue function waveforms (e.g. sine, triangle, sawtooth, square, etc.). The software tools allow a waveform to be specified or ‘drawn’ in the time 7

8

For consistency, throughout the remainder of this book we use the description ‘arbitrary waveform generator’ or AWG. We assume that the AWG category subsumes AFG instruments. We consider phase continuity in Chapter 2, but for our present discussion we can define it as a discontinuityfree amplitude transition as we from the end of the tabulated waveform to the beginning.

1.2 A taxonomy of electronic waveform generation

19

domain, or computed directly according to a Fourier series of -specified harmonic amplitude and phase parameters. A third and rather innovative method allows a waveform captured on a digital storage oscilloscope (DSO) to be ‘replayed’ using the AFG. If required, the captured waveform can be ‘edited’ to add (or remove) particular features, such as error-related transients, before being ed into the AFG memory for regeneration. This capability allows the generation of complex test and diagnostic stimuli for system verification using ‘known good’ signals as a baseline. Today, there are numerous AFG and AWG instruments available from LeCroy, Agilent (formerly Hewlett Packard) and Tektronix.

1.2

A taxonomy of electronic waveform generation

1.2.1

Background In this section we present an outline taxonomy of the most prevalent electronic waveform generation techniques. We use this to introduce some important underlying concepts that shape the chapter structure and organisation of this book. At this point in history there are broadly three categories of waveform generation methods, which we denote as analogue, digital and hybrid. Figure 1.8 illustrates a hierarchical taxonomy of these three categories and Figure 1.9 expands the digital subclass according to the structure and focus of this book. Figure 1.8 does not attempt to present an exhaustive breakdown of the analogue and hybrid categories, but provides an indication of the most popular methods in use today.

1.2.2

Analogue waveform generation Analogue waveform generation techniques operate entirely in the continuous-time domain and we can broadly classify them into ‘reactive ’ and ‘function generator’ groups. From a control system perspective, these groups use positive and bounded negative , respectively. Reactive oscillators are fundamentally limited to generating sine waves and are characterised by a resonant or phase shift network within the path of an amplifier that provides overall positive (i.e. 180 phase shift). Typically, the network may comprise a quartz crystal resonator, resistor-capacitor (RC) or inductor-capacitor (LC) network having the required resonant or phase shift properties necessary for sustained oscillation. The Wien bridge oscillator is a classic example of a reactive oscillator and uses an RC bridge network (based on the Wien bridge9) with a band- frequency response. This network is placed inside the positive path of an amplifier whose gain is dynamically adjusted using a separate servo loop to regulate 9

The Wien bridge is an AC bridge network originally conceived to measure the value of an unknown capacitance relative to a known value.

20


Electronic waveform generation

Analogue

Hybrid

Digital

Quartz crystal Reactive

LC tank Wien bridge Phase shift

Sine wave Digital control

DDS

Arbitrary waveform

Analogue waveshaping

Phase domain IDFT

Direct synthesis Switched integration Function generator

Clock

Direct conversion Variable sample rate

Interleaved DAC Oversampling DAC

Charge-balancing

Direct-form

Relaxation oscillator Recursive oscillators

Coupled-form (CF) Modified CF Waveguide-form

Figure 1.8 A taxonomy of electronic waveform generation techniques including some common subclasses.

oscillation amplitude. The Barkhausen10 stability criterion combined with a band- loop gain function provides the necessary design conditions for sustained sinusoidal oscillation in such networks, which we discuss further in Section 1.3. These conditions are also applicable (albeit in their discrete-time form) to the digital recursive oscillators that we present in Chapter 3. Another example of a reactive oscillator is the quartz crystal oscillator where the crystal can be considered as a narrowband (high Q) resonator at the specified operating frequency. Crystal oscillators provide excellent frequency stability over time and temperature together with low phase noise11. They are the principal choice for precision ADC sampling and digital clock 10

11

The Barkhausen stability criterion was suggested in 1921 by the German physicist Heinrich Georg Barkhausen. It specifies simple mathematical conditions that are necessary for a linear system to oscillate. A sinusoidal oscillation can be considered as narrow-band noise and the quality of this signal as measured by the spectral purity is determined by how much of its energy is contained within a defined frequency band close to its oscillation frequency. Phase noise is a qualitative metric that can be likened to the standard deviation of the narrow-band noise frequency around the oscillation frequency. For example, a good crystal oscillator can contain 99.99% of its energy within 0.01 Hz of the oscillation frequency.


21

Digital waveform generation

Recursive oscillators

DDS

Variable sample rate

Noninterpolated

Direct wavetable lookup Phase-dithered wavetable lookup Linear

Sine wave

Direct computation (e.g. Taylor series) Interpolated

ROM compression CORDIC Trigonometric

Phase accumulator division Clock

Hard-limited sine wave

Static waveshape Arbitrary waveform

Wideband Narrowband

Interpolated phase–amplitude mapping

Sequenced wavetables Dynamic waveshape

Interpolated wavetables

Wavetable combination

Single frequency Multiple frequency

Contiguous series Harmonic Phase domain

Non-contiguous series Non-harmonic ‘band-’ signals

Figure 1.9 A taxonomy of the digital waveform generation subclass. (Note that the variable

sample rate subclass is only outlined in this book, which is concerned with fixed sample rate systems.)

22


oscillators in most data conversion and DSP systems. So-called ‘LC tank’ oscillators such as the Colpitts or Hartley oscillators use a resonant inductor–capacitor (LC) network within the path of an amplifier and operate under similar principles to the quartz crystal oscillator, but with much lower Q. We observe that strictly speaking not all oscillators in this class contain resonant networks. The phase shift oscillator is one example of a non-resonant network and in one embodiment uses a lumped RC phase shift network in the path of an inverting amplifier to provide a precise 180 phase shift at the oscillation frequency. Combined with the 180 phase shift from the inverting amplifier, the necessary 360 loop phase shift required for sustained oscillation is achieved. Another example of a phase shift oscillator is the state-variable oscillator which is based on an analogue computer ‘model’ of an ideal two-pole resonator with adjustable damping. The model incorporates two series-connected integrators each providing exactly 90 phase shift. Setting the damping factor to zero enables sustained sinusoidal oscillation due to an overall 360 loop phase shift that is bounded by a closed-loop gain adjustment mechanism that maintains stable oscillation amplitude. Function generators use a systematic approach to signal generation that can be likened to an analogue computer simulation of a corresponding linear or ‘piecewise-linear’ mathematical model. An important and widely exploited example is the switched integration oscillator that controls the charging and discharging rate of a capacitor (i.e. an integrator) within fixed amplitude bounds in an oscillatory manner. The capacitor charge is controlled by a bounded negative loop so as to maintain a constant average capacitor voltage by oscillating between two voltage levels. Parameters within a well-designed function generator provide independent control of frequency, phase,12 amplitude and (to a limited extent) the output waveform shape. Simple relaxation oscillators are an example of this approach and generate only square or pulse waveforms. In more advanced implementations, a precision integrator integrates a switched polarity constant current whose polarity is controlled by a hysteretic comparator that sets the upper and lower amplitude bounds. This is a free-running oscillator and in its simplest form generates precision triangle (i.e. equal rising and falling slopes) and square waveforms. This oscillator provides very high waveform slope linearity and an oscillation frequency that is linearly proportional to the integrator current which is easily made voltage-controlled. If separate tracking current sources are used for the rising and falling integration slopes, it is possible with careful design to provide independent control of waveshape duty-cycle (i.e. the ratio of the waveform’s rising or falling slope time to the waveform period) and oscillation frequency. We outline such a design and the corresponding design criteria in Section 1.3. The charge-balancing oscillator or voltage to frequency convertor (VFC) provides extremely linear voltage control of frequency and can be thought of as a precision voltage-controlled frequency synthesiser. However, by itself it is only capable of

12

Strictly, we should observe that phase control, by definition, requires a reference point. Within a function generator model this is typically provided by a synchronisation output pulse, which defines the start time of a waveform cycle. Alternatively, our phase reference point could be a secondary output channel ‘phase locked’ to the primary channel or the start of a ‘burst envelope’, which contains a programmable number of waveform cycles.


23

generating pulse waveforms. The charge-balancing VFC is based upon a precision integrator which integrates a current that is linearly proportional to the control voltage. When the integrator output voltage reaches a pre-defined threshold (usually zero), a precisely defined ‘reset’ charge packet is taken from the integrator capacitor which resets the integrator back to some initial condition voltage. The process repeats in an oscillatory fashion at a frequency that ensures the net charge flow in the integrator capacitor is exactly zero. Unfortunately, the integrator ‘initial condition’ voltage following reset is necessarily a function of control voltage (to achieve the net zero charge flow condition) and so the integrator ramp waveform exhibits an amplitude variation with frequency. Therefore, the VFC can only generate pulse waveforms and requires further waveshaping if other waveforms are required. However, chargebalancing VFCs provide an extremely linear transfer function between control voltage and frequency. We provide a circuit-level overview of the Wien bridge, state variable, switched integration and charge-balancing oscillator techniques in Section 1.3 when we investigate purely analogue waveform generation techniques. In general, all analogue waveform generation methods exhibit drift in output frequency, control linearity and waveshape with temperature, supply voltage variation and component ageing. Drift is a fundamental property of all analogue circuits and is an error mechanism that can only be minimised through careful design, component selection and regular calibration. However, we should observe that outstanding levels of performance are possible with carefully designed analogue techniques.

1.2.3

Hybrid waveform generation As their name suggests, hybrid (or so-called ‘mixed-signal’) techniques include both analogue and digital processing. For the purposes of our present discussion, they divide into three main subclasses: digital control of an analogue signal generation function, analogue waveshaping with digitally controlled or derived frequency synthesis and so-called direct synthesis. One method to effect digital control of an analogue signal generation process requires that the appropriate control parameters are made voltage-controlled. Digital control is then effected by using a digital to analogue convertor (DAC) to convert digital control signals into corresponding control voltages. Alternatively, it is possible to effect digital control of resistively controlled analogue functions (e.g. the state-variable or Wien bridge oscillators) by use of a so-called multiplying DAC. The multiplying DAC (or MDAC) can be considered as a digitally controlled ‘virtual resistor’ that exists between the DAC reference voltage input and output, whose value is linearly controlled in fixed increments according to the value of a digital input binary word. However, there are limitations to this approach imposed by internal DAC error mechanisms and dynamic range [4]. It is also possible to implement a ‘capacitive DAC’ using a radix-2 capacitor sequence (i.e. C, 2C, 4C, 8C, etc.) connected in parallel by analogue switches. The digital input word controls the analogue switches producing a unit-increment composite capacitance value (i.e. C, 2C, 3C, 4C, etc.). This technique is popular in digitally controlling the gain of an op-amp inverting integrator embedded within a filter,

24


function generator or state-variable oscillator. An MDAC controls the input resistor value and a switched capacitance DAC controls the capacitance, realising a wide control dynamic range of the integrator gain. Irrespective of the exact implementation, DAC-based digital control should really be considered as a refinement of a purely analogue signal generation technique. In multiplying phase-locked loop (PLL) frequency synthesis, a digitally programmable integer divider is introduced into the path of the PLL to effect digital control of output frequency. The PLL output frequency is now an integer multiple of the input reference frequency according to the division value. The fractional-N PLL uses two (or more) integer digital dividers in the PLL path whose dutycycles are controlled so that the effective division ratio is a weighted average of the individual divider ratios [5]. The output frequency is equivalent to the input reference frequency multiplied by a division ratio that can now take on fractional values. Analogue waveshaping can, in principle, be applied to the output of direct synthesis, fractional-N PLL, DDS and variable sample rate frequency synthesisers. In most cases, waveshaping is based upon controlled integration of a derived voltage (or current) that is proportional to the programmed frequency and is used to compensate waveform amplitude variation. Typically, this voltage is derived from the frequency control digital word using a DAC. DDS combined with analogue waveshaping can be likened to phase accumulation frequency synthesis with analogue phase–amplitude mapping. We investigate some of these techniques in Chapter 5. So-called direct synthesis uses an ‘open-loop’ combination of analogue frequency multipliers, digital dividers and analogue mixers to generate an arbitrary multiple of a reference frequency. A modular ‘mix and divide’ direct synthesiser provides an n-digit decimal weighted frequency synthesiser requiring n identical modules [6].

1.2.4

Digital waveform generation Digital waveform generation techniques operate in the discrete-time domain and generate signals according to an algorithm which simulates an underlying mathematical model. For the generation of analogue output signals we observe that all digital algorithms require a digital to analogue conversion (DAC) stage followed by appropriate reconstruction filtering, both of which are analogue operations. However, for classification purposes, we observe that the underlying synthesis processes occur entirely in the digital domain and so we classify these techniques as ‘all digital’. Three distinct digital waveform generation models are evident: recursive oscillators; fixed sample rate phase accumulation and phase–amplitude mapping, which is generally known as direct digital synthesis13 (DDS); 13

To date, DDS has been mostly associated with sine wave synthesis. However, DDS is equally suited to arbitrary waveform generation with suitable modification of the phase–amplitude mapping function.


25

a simplification of DDS where a phase counter and phase–amplitude mapping function are clocked at a variable sample rate to control output frequency. Recursive oscillators are limited to generating sinusoidal signals and can suffer from various instability behaviours due to their closed-loop structure and iterated arithmetic with quantised values. These instabilities can appear as a variation of the oscillation amplitude or quantisation noise growth over time, often requiring periodic initialisation of the algorithm to bound them. Recursive techniques, while having distinct advantages in low cost or less performance-critical applications, also lack control flexibility compared to the phase accumulation approach. However, their computational simplicity makes them attractive in many applications. The DDS model comprises two distinct processing stages – phase accumulating frequency synthesis and phase–amplitude mapping waveform generation. These two independent processes elegantly partition frequency synthesis and waveform generation. The phase accumulator is a first-order process and is therefore wellbehaved and intrinsically stable. However, the phase–amplitude mapping function often requires arithmetic approximation to simplify hardware design (often to minimise memory requirements) causing error components in the output spectrum whose distribution and amplitude are a complex function of the phase increment (i.e. the frequency control parameter). Elimination or reduction of these error components to an acceptable level is often the principal design driver in these systems. Variable sample rate synthesis is a simplification of DDS where the phase accumulator is replaced by a simple binary counter that is clocked at a variable sample rate to control output frequency. The binary counter addresses the phase–amplitude mapping lookup table and is equivalent to a phase accumulator with a unit phase increment. This technique is conceptually the simplest to understand and apply. It defines the present state of the art in very high speed arbitrary waveform generators where maximum sample rates exceed 10 GHz [7]. The key digital elements of these systems are the address counter and high speed memory, which often uses timeinterleaved low speed commodity memory devices. Major design challenges lie in the predominantly analogue DAC and low jitter variable sample clock source. Deg a DAC with a 14-bit dynamic range at a 10 GHz sample rate is a nontrivial undertaking.

1.2.5

Arbitrary waveform generation The exploitation of arbitrary waveform generation (AWG) techniques within test instrumentation and bespoke applications has followed two distinct methodologies, which we classify as fixed sample rate and variable sample rate. In fixed sample rate phase accumulating frequency synthesis, the output frequency is a rational fraction of a fixed reference frequency (i.e. the sample frequency), usually derived from a high stability crystal oscillator. The reference oscillator can be designed and optimised to meet the frequency stability and phase noise requirements of the application. By definition, variable sample rate synthesis requires a variable reference oscillator to generate the

26


fs Length 2M waveform memory

M-bit counter

Low reconstruction filter

DAC

A

fo =

fs 2M

(a) ½ sample delay 2M-1 even waveform samples

fs

DAC Low reconstruction filter

å

(M-1)-bit counter M-1

2 odd waveform samples

DAC

A

fo =

fs 2M

(b)

Oversampling DAC

fs M

/N

M-bit counter

Length 2 waveform memory

Order-N interpolation filter

DAC


A

fo =

f

2

s M +N

(c) Figure 1.10 Three popular variable sample rate AWG architectures. (Note that the output frequency expressions assume a single waveform cycle is stored in memory.)

sample clock. This can be a wide range VCO operating over some low frequency interval which is translated to the desired operating frequency by a frequency-multiplying PLL. Alternatively, for more precise frequency control, a fractional-N PLL frequency synthesiser referenced to a crystal oscillator may be used. The outlines of three variable sample rate AWG architectures are illustrated in Figure 1.10. Figure 1.10a shows the simplest ‘brute force’ approach, which we denote as direct conversion AWG and is also known as ‘true AWG’ in the literature [8]. Direct conversion uses an M-bit unit-increment binary counter clocked by a variable frequency oscillator of frequency fs that controls the frequency of the synthesised waveform. Typically, the variable sample rate oscillator is based on a digitally controlled frequency synthesiser such as a fractional-N PLL rather than a phase accumulator as with DDS.


27

The counter addresses a high speed semiconductor memory of length 2M locations that stores pre-computed waveform samples as a ‘lookup table’. The indexed waveform samples are fed to a DAC, followed by a low- reconstruction filter to produce a continuous-time output waveform of frequency f s =2M , assuming a single waveform cycle is stored in the memory. If k waveform cycles are stored in memory the output frequency is kf s =2M . The variable sample frequency may also be derived from a multiplying PLL referenced to a DDS. Figure 1.10b shows a simple development of this approach, which we denote as the time-interleaved DAC AWG and which uses two independent waveform memories each of length 2M-1 samples and addressed by a single (M 1)-bit unit-increment address counter. Each waveform memory feeds a respective DAC clocked at the variable sample rate, but with a half sample period delay between the two DAC clocks. The DAC outputs are then summed to form the output signal. The 2M pre-computed waveform samples are interleaved across the two memories so that one tabulates even addressed samples and the other tabulates odd addressed samples. The effective memory length is 2M samples and the output frequency is fs/2M, assuming a single waveform cycle is stored in the memory. The advantage of this approach is that it provides a higher effective sample rate by cancelling the first alias images from each DAC channel, enabling useful bandwidth out to the sampling frequency. However, each DAC is only sampled at a rate consistent with half the combined bandwidth. The alias image cancellation arises from the 180 phase shift between the first alias images of the two DAC channels as outlined by Mercadé [9]. It is important to that any mismatch in gain and phase over frequency between the DAC channels or deviation from the half sample period delay between DAC sample clocks will tend to degrade alias cancellation performance when the two channels are summed. This, in turn, causes reduced suppression of the first alias image and so reduced dynamic range in the output signal. Proper application of this technique therefore requires careful calibration and matching of the two DAC channels. One method, as conceptualised in Figure 1.11, embeds the time-interleaved DAC AWG within an auto-calibration loop, allowing automatic correction of thermal and ageing induced DAC gain, phase and sampling time errors. Finally, Figure 1.10c shows the oversampling DAC AWG which indexes waveform samples from memory at an integer sub-multiple N of the DAC sample rate. The waveform memory is then addressed at fs/N, where N is defined as the oversampling factor. The output of the waveform memory is fed to an N-fold interpolation filter which effectively computes interpolated samples between the tabulated values stored in memory. The output frequency is fs/2M þ N, assuming a single waveform cycle is stored in the memory. The advantages of this approach are smoother synthesised waveforms (from a waveshape perspective), significantly reduced sampling alias images (from a spectral purity perspective), and therefore improved signal to noise ratio. However, there is an N-fold reduction in maximum waveform frequency compared to the other approaches. The oversampling DAC principle is strictly a DAC processing strategy and can be applied to any fixed sample rate system. Fixed sample rate DDS AWG uses a constant sample clock frequency and accumulates a phase increment parameter φ on each sample clock to control output waveform

28


Signal analyser

Calibration controller

Calibration frequency

Delay adjust

Calibration waveform

Output monitor

DAC gain, phase and offset adjust

½ sample delay 2M-1 even waveform samples

DAC 1

å

(M-1)-bit counter M-1

2 odd waveform samples

fs


A

DAC 2

Figure 1.11 Conceptual auto-calibration methodology in the time-interleaved DAC AWG.

frequency. The phase accumulator generates a discrete-time phase function whose slope (controlled by the phase increment parameter) determines the output waveform frequency. The phase function is converted to a desired waveform by a phase–amplitude mapping process usually based upon a table-lookup operation, possibly augmented by interpolation. There are principally two categories of DDS AWG that concern us here – non-interpolated and interpolated – whose processing architectures are illustrated in Figure 1.12. Figure 1.12a shows the signal-flow of a simple non-interpolated DDS AWG. Essentially, we have a series-connected phase accumulator, waveform memory, DAC and low- reconstruction filter all clocked at a constant sample rate fs. The output frequency is given by the simple linear expression fo ¼ φfs/2M, assuming a single waveform cycle is tabulated in the waveform memory. Non-interpolated DDS AWG can exhibit significant shortcomings when the number of tabulated samples (i.e. the number of tabulated waveform phase points) is less than the 2M phase states of the phase accumulator (which it nearly always is). In essence, this condition causes noise artefacts that appear as phase jitter in the time domain and reduced spurious-free dynamic range (SFDR14) in the frequency domain (i.e. amplitude spectrum). The level of the associated error signals is dependent on the phase increment and the number of bits truncated from the phase accumulator output. Unfortunately, there are conflicting design considerations here. The phase accumulator word size M should be as large as possible to maximise frequency control resolution fs/2M but the lookup table length should be as short as possible to minimise lookup table ‘fill time’ 14

We discuss the SFDR metric further in Chapter 2. It is defined as the difference between the full-scale amplitude and the amplitude of the largest spurious component in the output spectrum when expressed on a dB scale.

29


fs

Phase increment

j

S

z-1

Waveform memory

DAC


A

fo =

Phase accumulator M

jfs 2M

(a)

fs Phase increment

j

‘Fractional’ phase address

S

z-1

Order-N interpolation addressing

Waveform memory

Order-N interpolation processing

DAC


A

fo =

Phase accumulator

jf s 2M

M

Nfs (b) Figure 1.12 Fixed sample rate non-interpolating and interpolating DDS AWG architectures. The non-interpolated architecture is equivalent to so-called phase truncated lookup table indexing.

(i.e. when programming arbitrary waveforms), associated memory cost and power consumption. The optimal condition occurs when the lookup table length is 2M samples, which becomes impractical or uneconomical when M is large (i.e. the lookup table length is 2M samples and so increases exponentially with M ). Interpolating a small lookup table is an effective way to mitigate these effects. Figure 1.12b shows the generalised signal-flow of interpolated DDS AWG which processes multiple reads from the waveform memory lookup table (according to the interpolation order) for each output waveform sample fed to the DAC. The phase accumulator output is now interpreted as a fractional address into the waveform memory lookup table, otherwise this architecture is identical to non-interpolated DDS AWG. The simplest interpolation scheme is first-order linear interpolation, requiring two reads from the waveform memory for each output sample fed to the DAC. Higher-order polynomial interpolation is also possible, producing steadily reducing noise performance at the expense of computational overhead. Optimal interpolation is achieved by using a truncated sinc function to interpolate a block of consecutive waveform samples.

30


We bound the scope of this book by focusing on DDS sinusoidal and arbitrary waveform generation and present only an outline review of variable sample rate methods. However, many of the key DDS waveform generation operations which we investigate (e.g. polynomial interpolation, high speed interleaved memory access and digital to analogue conversion) are also applicable to variable sample rate synthesis. Accordingly, we define four categories of fixed sample rate DDS waveform generation for investigation:

sinusoidal (i.e. ‘classic’ DDS); digital clock (i.e. a low jitter square wave); arbitrary (i.e. DDS AWG); ‘phase domain’ methods which can implement the IDFT as a real-time phase– amplitude mapping algorithm.

The latter two categories are the main focus of this book. The principal differences between these classifications lie largely in the phase–amplitude mapping function, although in phase domain synthesis there is further arithmetic manipulation of the phase accumulator output prior to the phase–amplitude mapping stage. Sinusoidal DDS is concerned with choosing a sinusoidal phase–amplitude mapping method that optimises performance, power consumption and cost for a given specification. DDS clock generation is concerned with generating low jitter (i.e. low phase noise) square wave (or pulse) clock waveforms for frequency-agile digital clocking applications that require very low phase jitter (e.g. variable sample rate analogue to digital conversion). DDS AWG is concerned with generating waveforms that have a defined waveshape or spectrum. Finally, phase domain synthesis is a novel, computationally efficient method for generating multiple, harmonically related sinusoids in contiguous or non-contiguous sequences relative to a fundamental frequency. These harmonic sequences are typically used to compute the inverse discrete Fourier transform (IDFT) in real time as a waveform ‘synthesis from scratch’ algorithm according to harmonic amplitude and phase parameters. Phase domain synthesis therefore provides a precise harmonic spectrum synthesis technique. The fundamental principles of phase domain processing also find utility in the design of high speed phase accumulators that we discuss in Chapter 8. DDS AWG is fundamentally more amenable to hardware implementation due to its fixed sample rate processing. Throughput enhancement techniques such as arithmetic pipelining, time-division multiplexing and parallel processing can be optimised for a constant processing interval (i.e. the sample period). This is particularly relevant to interpolated DDS AWG, which can require considerable memory read activity and subsequent arithmetic processing within the interpolation stage. Conversely, a variable sample rate system requires every process to be designed and optimised to execute in the shortest sample period (i.e. highest sample frequency). At lower sampling frequencies the ‘extra’ processing bandwidth is wasted. The use of arithmetic pipelining in a variable sample rate system (aside from being difficult to implement) causes the pipeline latency time, and hence system responsiveness to control parameter changes, to vary inversely with sample rate. Lastly, with variable sample rate AWG, the Nyquist

1.3 Analogue waveform generation

31

frequency also varies in direct proportion, requiring the cut-off frequency of the low reconstruction filter to track the sample rate (i.e. it must be made variable). This adds significant complication to the design. In a fixed sample rate system the cut-off frequency of the low- reconstruction filter is constant.

1.3

Analogue waveform generation We begin this section by briefly outlining the history of analogue waveform generation as applied in commercial test instrumentation. We then proceed to discuss several important analogue waveform generation techniques that have been widely applied in both test instrumentation and bespoke applications. We summarise their important shortcomings that can be overcome or significantly improved by application of the digital techniques which follow. There are two popular categories which we consider here – resistor-capacitor (RC) tuned reactive oscillators and voltage-controlled switched integration function generators.

1.3.1

Analogue waveform generation in test instrumentation Before discussing some specific circuit architectures, we briefly outline the evolution of laboratory test instrumentation that has utilised wholly analogue signal generation techniques. Manually controlled, so-called RC tuned oscillators were the first to be applied in commercial test instrumentation signal generators and were only much later augmented by digital control. The first instruments generated sinusoidal waveforms in the audio range using a Wien bridge oscillator that provided independently controlled amplitude and frequency from 20 Hz to around 35 kHz in switched decade ranges. The most historically significant of these early instruments was the groundbreaking HP200B produced by Bill Hewlett15 and Dave Packard – the first commercial product of the early Hewlett–Packard Company in circa 1940 [10]. These instruments evolved through the HP200 series, HP204 and HP650 to provide progressively wider frequency control range and lower distortion sine wave outputs. Later still, instruments appeared that used a voltage-controlled oscillator or function generator to provide sine, triangle, sawtooth, square and pulse ‘function’ waveforms. The function generator was capable of generating these waveforms over a very wide frequency range extending from sub-millihertz to tens of megahertz. Waveshape control was limited to variation of the waveform duty-cycle, typically from 10% to 90%. This allowed triangle waveforms that have precisely equal rising and falling slopes to be continuously transformed into sawtooth waveforms with unequal or asymmetric rising and falling slopes. The ratio of rising (or falling) slope to waveform period is defined as the waveform duty-cycle. Examples of these early instruments include the HP3310B and HP3312A function generators – the latter providing internally generated amplitude and frequency modulation and programmable frequency sweep. 15

The HP200A prototype was Bill Hewlett’s 1938 Stanford University Masters project in 1938.

32


In the late 1970s, frequency synthesised function generators such as the ubiquitous HP3325B were introduced. The HP3325B uses a microprocessor controlled fractional-N phase-locked loop (PLL) frequency synthesiser combined with analogue waveshaping and provides frequency and phase control with superior frequency control precision and stability compared to voltage-controlled function generator techniques. Notable performance improvements over previous analogue methods included extremely fine frequency control resolution (1 μHz) and temperature stability comparable with a temperature-compensated crystal oscillator (TCXO), which could be chosen to provide near-zero temperature drift. Strictly, these instruments are properly described as hybrid technologies due to the microprocessor control and digital divider within the otherwise analogue PLL and subsequent waveform shaping. Instruments based on the voltage-controlled function generator evolved in the 1980s to acquire digital control of output frequency, amplitude and waveshape, greatly increasing their control precision and operational flexibility. This was particularly true in the automatic test equipment (ATE) domain. A digital to analogue convertor (DAC) generated control voltages from an internal microcontroller and embedded software that controlled a push-button and numeric display -interface. Examples of such instruments include the HP8116A and HP8112A, which are optimised for function and pulse waveform generation applications, respectively.

1.3.2

The Wien bridge oscillator An outline schematic of a Wien bridge oscillator and the corresponding loop gain and phase frequency responses are illustrated in Figure 1.13. This oscillator uses both positive via the series-parallel RC network and negative via R1 and R2 around the op-amp A1. In a typical implementation, R2 is controlled by a separate amplitude-stabilising servo loop that compares the oscillator output amplitude with a fixed reference voltage that determines steady-state oscillation amplitude. The behaviour of this closed-loop system is governed by which path dominates. Circuit analysis and design are greatly simplified if we let both RC networks have the same values. We begin by considering the system as an ideal non-inverting amplifier that amplifies the voltage at the op-amp non-inverting input Vþ by 1 þ R2/R1. Vþ is supplied via the two RC networks which form a potential divider of the op-amp output voltage Vo. Hence we have Vþ ¼ Vo Z1/(Z1 þ Z2), where Z1 ¼ Rk(1/2π jfC ) and Z2 ¼ R þ 1/2π jfC. The transfer function of the reactive network is then given by Vþ 1 , where f0 ¼ 1/2πRC. The loop gain, AL ( jf ), is ¼ Aþ ð jf Þ ¼ V o 3 þ jð f =f 0 f 0 =f Þ then given by AL( jf ) ¼ (1 þ R2/R1)Aþ( jf ) and after substitution we obtain AL( jf ) ¼ (1 þ R2/R1)/(3 þ j( f/f0 f0/f )). The loop gain expression is a band- function since it approaches zero at high and low frequencies, with a maximum value at f ¼ f0 of AL( jf0) ¼ (1 þ R2/R1)/3. Since AL( jf0) is a real-valued quantity, a signal of frequency f0 will experience a precisely zero phase shift around the loop. We now observe three distinct closed-loop behaviours depending on the value of AL( jf0):

33


C

R

V+

+ –

+ 90°

0°

AL ( jf )

R

f0

C

A1

Vo R1

f

ÐAL ( jf ) - 90°

R2

Voltage-controlled resistor

f0 0

f

-Vref

AL ( jf )

A2

– +

Amplitude-stabilising servo loop Figure 1.13 A Wien bridge oscillator and corresponding loop gain responses.

1. For AL( jf0) < 1 or (1 þ R2/R1) < 3 the loop gain is less than unity (i.e. AL( jf ) < 1) and so any initialising noise disturbance progressively reduces as it propagates around the loop. Negative therefore dominates over the positive and the system is inherently stable. 2. For AL( jf0) > 1 or (1 þ R2/R1) > 3 the loop gain is greater than unity (i.e. AL( jf ) > 1) and so any initialising noise disturbance is amplified regeneratively as it propagates around the loop. Positive now dominates and so the system is inherently unstable. The regenerative oscillations build up until saturation of the op-amp occurs leading to a clipped sinusoidal oscillation. 3. For the exact condition AL( jf0) ¼ 1 or (1 þ R2/R1) ¼ 3 we have the so-called neutral stability condition where positive and negative are applied in exactly equal amounts. This condition is achieved when R2/R1 ¼ 2. Any disturbance leads to a sustained oscillation at frequency f0, assuming ideal circuit behaviour. The conditions ∠AL( jf0) ¼ 0 and jAL( jf0)j ¼ 1 are collectively known as the Barkhausen criterion for oscillation at f ¼ f0. In a real implementation, non-ideal component behaviour such as thermal and agerelated drift makes it difficult to maintain the exact neutral stability condition over time. Consideration must be given to reliable and spontaneous oscillation at power-on and maintaining steady-state oscillation amplitude to prevent op-amp saturation. This is

34


achieved by making the ratio R2/R1 amplitude dependent, so that it is slightly greater than 2 to ensure oscillation at start-up and slightly less than 2 to limit amplitude. During steady-state operation amplitude is servo regulated so that R2/R1 ¼ 2 exactly. The amplitude stabilisation servo loop can be implemented in several ways. The simplest technique replaces R2 with a small tungsten filament lamp whose resistance increases with filament temperature. As the oscillation amplitude grows, more current flows in the lamp filament and so the filament resistance (R2) increases. This negative mechanism has the effect of regulating oscillation amplitude and was successfully applied by Bill Hewlett in the first HP200 oscillator which used a Wien bridge design. An alternative and more precise amplitude stabilisation technique is depicted in Figure 1.13 where R2 is a symmetrically driven JFET or optically controlled resistor, thereby providing voltage control of the oscillator loop gain. A servo error amplifier A2 compares two currents – one proportional to the oscillation amplitude and the other a fixed reference current. The resultant error voltage in turn controls the voltage-controlled loop gain so as to regulate steady-state oscillation amplitude. The error amplifier capacitor is chosen to provide a long time constant compared to the lowest oscillation period. This minimises second harmonic ripple into the voltage-controlled loop gain point. Wien bridge oscillators using carefully designed active amplitude stabilisation loops can achieve very low distortion, with 0.0015% total harmonic distortion reported by Williams [10] for an audio range design. This reference also provides an enlightening discussion of precision Wien bridge oscillator design, building on that presented in Bill Hewlett’s master’s thesis. It concludes with a modified Wien bridge oscillator design that achieves total harmonic distortion levels below 0.0003%. One significant drawback of the Wien bridge approach is the difficulty in achieving digital control of frequency, which requires two RC time constants (with one floating) to be simultaneously controlled. A typical implementation might use switched capacitor networks to provide decade range control and digitally controlled resistors to effect fine frequency control. However, maintaining low distortion levels with the necessary analogue switching represents a significant design challenge.

1.3.3

The state variable oscillator A state variable filter16 uses two integrators within a loop that implements an analogue computer model of a second-order differential equation that describes an ideal two-pole filter with adjustable damping and hence Q factor. As a filter, this model can simultaneously generate high-, band- and low- responses with Q factor and cut-off frequency that are independently variable. Furthermore, summation of the low- and high- outputs produces a notch function. An outline schematic of a state variable oscillator is illustrated in (Figure 1.14) and is based upon a state variable filter arranged to operate in the neutral stability region with zero damping. The statevariable oscillator can also be viewed as a class of so-called phase shift oscillator since 16

A state variable filter is also known as a ‘KHN filter’, after its inventors Kerwin, Huelsman and Newcomb who first reported it in 1967.


35

R1

R2

-cos C

R3

– +

R4

A1

R

– +

A2

C

R

– +

cos

A3

sin

R6

R7

-Vref C1

Voltage-controlled resistor A4

R5

–

R8

+

Amplitude-stabilising servo loop

Figure 1.14 A state variable oscillator with amplitude stabilisation.

the two integrators provide exactly 90 phase shift at their unity gain frequency. Combined with the 180 phase shift of the inverting amplifier, this produces the 360 loop gain phase shift required for oscillation. Two identical integrators comprising op-amps A2 and A3, and a summing amplifier A1 form the core of the oscillator loop. In this mode, the loop is effectively solving the un-damped differential equation x€ þ ð2π f 0 Þ2 x ¼ 0 for which the steady-state solution is the sinusoid x ¼ A sin2π f0t (ignoring initial conditions and phase offset). The oscillation frequency is given by f0 ¼ 1/2πRC, where f0 is the unity gain frequency of each integrator. We observe that the precision op-amp integrators used in the state variable design produce exactly quadrature sinusoids at the outputs of A2 and A3. In a similar manner to the Wien bridge oscillator, an amplitude stabilising servo loop comprising the error amplifier A4 ensures a stable oscillation amplitude by balancing two paths – one regenerative (R5/(R4 þ R5)), and one degenerative (R2/R3). The circuit is designed so that the amplitude stabilising servo loop can adjust the loop gain from regenerative (needed to ensure reliable oscillation start-up) through to degenerative to enable steady-state oscillation amplitude stabilisation. A detailed discussion on the design of a state variable oscillator is provided by Jung [11]. The servo error amplifier A4 compares two currents – one proportional to the oscillation amplitude and the other a fixed reference current which sets the set point of the steady-state oscillation amplitude. The resultant error voltage in turn controls the regenerative path loop gain through the voltage-controlled resistor R5 so as to regulate steady-state oscillation amplitude. The error amplifier capacitor is chosen to provide a

36


+V

C

Duty cycle

if

Vc ir

Hysteretic comparator

A + Integrator

-V

Figure 1.15 A representation of a voltage-controlled switched integration oscillator.

long time constant compared to the lowest oscillation period in a similar manner to the Wien bridge oscillator. This minimises the error amplifier output ripple into the voltagecontrolled loop gain point. Some implementations report operating the error amplifier A4 as a pure integrator (i.e. R6 omitted) thereby providing infinite DC gain. The fixed frequency state variable oscillator with servo amplitude stabilisation is inherently capable of very low harmonic distortion performance (<0.0003%). This arises principally from all op-amps running in a ‘virtual earth’ summing mode thereby minimising linearity errors due to input common-mode voltage variation. Strictly speaking, the schematic of (Figure 1.14) shows the loop summing amplifier A1 not operating in this mode. However, by the addition of an inverting amplifier within the regenerative path, the loop summing amplifier A1 can now be operated in the optimum virtual earth summing mode. Since the oscillation frequency is set by the time-constant (RC ) of the virtual earth integrators, there is greater scope for low distortion digital control of oscillation frequency over a wide range. Foote et al. [12] report a novel, high performance digitally controlled state variable oscillator as used in the HP8903B distortion analyser. This design achieves harmonic distortion around 0.001% over the audio band. The Tektronix SG505 audio oscillator [13] achieves similar performance, albeit with only manual control of oscillation frequency.

1.3.4

The voltage-controlled switched integration oscillator A voltage-controlled switched integration oscillator that generates triangle and square waveforms is shown schematically in Figure 1.15. In principle, this architecture allows independent control of waveform, frequency and duty-cycle where a 50% duty-cycle corresponds to exactly equal triangle waveform slopes. Deviation from a 50% dutycycle produces progressively sawtooth-like waveforms. The oscillator is based around two voltage-controlled current sources that charge and discharge a precision integrator via a switch controlled from a hysteretic comparator or Schmitt trigger. The input to the comparator is fed from the integrator output producing a closed-loop, two-state positive system. The hysteretic comparator is designed to have two precisely defined and temperature invariant threshold switching voltages

37


denoted VH and VL, and usually symmetrically located around zero volts. The width of the hysteresis window is VH VL and sets the oscillation amplitude. As the integrator output voltage increases in a particular direction, a point is reached where one of the comparator thresholds is met causing it to switch output states. The comparator output transition switches the opposite polarity current source into the integrator which in turn begins integrating in the opposite direction. This cycle repeats continuously, producing a triangle waveform at the integrator output, and a square waveform at the comparator output assuming equal magnitude integrator input currents. For a given value of integration capacitor, the corresponding rise and fall times are set by the currents ir and if , respectively. Since the precision integrator is charged and discharged from a current source, the integrator output varies linearly with time (i.e. constant slope). If the two current sources are controlled so that the sum of the corresponding slope times, tr and tf (i.e. the oscillation period) is independent of the ratio tr/(tr þ tf) (i.e. waveform duty-cycle), independent control of oscillation frequency and duty-cycle is achieved. Figure 1.16 is a schematic of a typical voltage-controlled switched current source that provides independent control of oscillation frequency and waveform duty-cycle.

+V

R11

+V

R1

A2 + Frequency control voltage R

A4 +

T3

T1

From hysteretic comparator

R3

R2

if

R

Vc

R4

A1 +

D1

D4

To integrator summing node

R5

Duty cycle

R6

D2

R7

D3

ir

R8

A3 +

T2

R9

+ A5 -

T4

R10

-V

R12

-V

Figure 1.16 A voltage-controlled switched current source providing independent control of oscillation frequency and duty-cycle.

38


Op-amp A1 provides unity gain inversion of a positive-going frequency control voltage as the current source requires a negative-going control voltage. It is possible to show that for independent control of oscillation frequency and duty-cycle the following component relationships must apply: R2 ¼ R9, R4 ¼ R7, R1 ¼ R10, R11 ¼ R12 and R3/R2 ¼ (1 ¼ R8/R6). Under these conditions the oscillation frequency is given by f ¼ Vc/(VWCRc), where VW is the width of the comparator hysteresis window and defined by VW ¼ VH VL, C is the integration capacitor value and Rc ¼ R7R12(2R2 þ R5)/R3R10.

1.3.5

The charge-balancing voltage to frequency convertor A charge-balancing voltage to frequency convertor is illustrated in Figure 1.17 and can be likened to a high linearity voltage-controlled frequency synthesiser. We include this oscillator for completeness since it offers the best voltage-control linearity performance despite generating only pulse waveforms. Further waveshaping is required if other waveforms are required. The charge-balancing voltage to frequency convertor is based upon a precision integrator that integrates a current iin from an initial (post reset) condition, where the integrator output is at a positive potential with respect to ground (i.e. the voltage across C1 with respect to the op-amp inverting input is positive). The input current is directly proportional to the positive input control voltage Vin with iin ¼ Vin/R1. As integration proceeds, the integrator output voltage Vo ramps in a negative direction until it reaches the zero-volt reference of the comparator. When the comparator switches state it triggers a precision monostable which generates a precisely defined reset pulse of width tr . During the reset period a precision current sink ir pulls charge from the integrator capacitor C1, causing the integrator output to ramp in the positive direction. At the end of the reset period the integrator is at its initial condition voltage and the process repeats in a cyclic manner. We observe that for sustained operation the input voltage is bound so that jiin(max)j <jirj and therefore Vin(max) < jirjR1. If we denote the charge flowing in C1 during the integration and reset phases as Qi and Qr respectively, we observe that during normal operation Qi ¼ Qr since charge is conserved by the negative loop (i.e. the average integrator capacitor current is always precisely zero). Therefore, iinti/C1 ¼ icr t r /C1 or iinti ¼ icr tr . Now, the output frequency is given by fo ¼ 1/(ti þ tr) and hence by substitution we obtain fo ¼ (icr tr/iin þ tr)1. Since icr ¼ ir iin we finally obtain fo ¼ ((ir iin)tr /iin þ tr)1, which simplifies to fo ¼ Vin/(R1irtr). We observe that this expression is independent of C1 and linearly proportional to Vin. The only scaling constants are R1, ir and tr . The reset current and monostable period are critical design parameters to ensure low temperature drift and high linearity.

1.3.6

The shortcomings of analogue waveform generation By definition, all analogue electronic circuitry comprises a combination of ive components such as resistors and capacitors, and active components such as transistors, diodes and operational amplifiers. All of these components have well-documented ideal

39


Integrate

iin

Reset C1

icr

R1

iin

Comparator

-

+Vin

+

ir

Vo

+ -

Precision monostable

fo

Integrator Switch in reset position ir

Precision current sink

tr

-V +Vin1

+Vin

+Vin2 (ir - Vin 2 R1 )t r C1

(ir - Vin1 R1 )t r C1 Vo 0v tr

Reset

1/fo

ti Integrate

Reset

Integrate

Figure 1.17 Charge-balancing voltage-to-frequency convertor and operational timing diagram.

behaviours and corresponding mathematical models that the initial ‘paper design’ process. However, real-world components invariably exhibit non-ideal behaviours whose effects in real-world circuits can only be minimised by careful component selection and good design. It is evident from the previous discussion that all analogue waveform generation circuits exhibit varying degrees of sensitivity to some or all of the following error mechanisms: drift in the absolute and relative value of ive components (e.g. resistors and capacitors) over temperature, time or other environmental effects (e.g. mechanical shock, humidity, etc.); active and ive component non-linear behaviours (e.g. op-amp harmonic and intermodulation distortion, capacitor dielectric absorption and voltage dependency and resistor voltage dependency); drift in active component AC and DC parameters over temperature and time (e.g. op-amp slew rate, input offset voltage and input bias current);

40


matching of active component parameters over temperature and time (e.g. transistor Vbe and diode forward voltage drop); thermal and other noise sources in active and ive components; dependency on supply voltage variation. Although the effects of these error mechanisms may be reduced to extremely low levels by good design, careful component selection and periodic calibration, they can never be completely eliminated. Notwithstanding the DAC, reconstruction filter and output stages, all of these errors (and more) are eliminated when we use digital techniques such as DDS AWG. This leads to several fundamental performance advantages over analogue methods which include: waveform frequency accuracy and stability are governed entirely by the performance of a reference oscillator (e.g. a TCXO); frequency and phase control resolution and linearity are temperature and time invariant; precise specification, dynamic control and repeatability of waveshape; simplified (or eliminated) calibration to maintain performance within specifications. If our digitally generated signals are to be used in the analogue domain, we must consider errors in the DAC, reconstruction filter and output processing stages. The principal errors that concern us here are: DAC non-linearity and its effect on waveform distortion and the amplitude error spectrum; DC offsets in the DAC and subsequent stages; -band gain accuracy; reconstruction filter -band flatness and phase response. All of these error mechanisms affect waveshape conformity, spurious-free dynamic range (SFDR) and absolute waveform amplitude. They do not affect frequency control or stability. Today, most commercially available DACs are well-characterised monolithic devices that have defined linearity and SFDR specifications with very good stability over time. Proper DAC selection and careful design of the associated circuitry (e.g. voltage references, supply decoupling, ground management and the output amplifier) guarantee and maintain SFDR performance to a specified level of accuracy. DC offset errors can be minimised by good circuit design and the use of auto-calibration servo techniques. Similarly, gain drift, -band flatness and distortion errors are also minimised by careful circuit design and component selection. This is particularly true in the reconstruction filter where ive component non-linearity (e.g. capacitor voltage dependency) is an important design consideration when minimising distortion. Auto-calibration of gain is an effective technique for compensating thermal and agerelated component drift. One approach uses a periodically activated auto-calibration servo loop which compares the amplitude of a full-scale reference waveform to a precision DC reference. The resulting amplitude error signal is used to calculate a correction factor to normalise the channel gain. With careful circuit design, component

1.4 Applications of arbitrary waveform generation

41

selection and application of auto-calibration techniques, DAC and related processing error effects can be reduced to second-order severity or almost eliminated. The application of wholly analogue methods to the problem of generating electronic signals will continue for the foreseeable future due to their relative simplicity and adequate performance in many applications. However, the limited frequency stability, control precision and waveform complexity suffered by analogue methods are eliminated or vastly improved with digital techniques such as DDS AWG. Finally, we should that all digital waveform generation systems still require critical analogue functions such as the reference oscillator, DAC, reconstruction filter and output processing. ‘Going digital’ should not be seen as a panacea for the problems of analogue methods. In the field of waveform generation (and indeed many others) they are complementary technologies, where each has its role to play.

1.4

Applications of arbitrary waveform generation In this section we outline some application areas that exploit the unique advantages and capabilities of digital arbitrary waveform generation. These areas may be loosely grouped into four overlapping categories:

test and diagnostic; signal emulation; bespoke embedded; RF up-conversion.

This simple categorisation is not meant to be exhaustive, but summarises the most prevalent application areas and serves as a basis for discussion. It is important to that these categories overlap significantly. For example, signal emulation (e.g. the simulation of a unique transducer signal or system response) is clearly relevant to test and diagnostic applications, but is also a distinct application area in its own right. Similarly, the emulation of sonar, seismic or ultrasound imaging signals with particular characteristics s processing algorithm development and optimisation.

1.4.1

Test and diagnostic applications Generation of test and diagnostic signals is a very broad application area and may be defined as the synthesis of systematically ‘engineered’ stimulus signals that the functional test, diagnostic debug and design verification of electronic systems or components. As electronic systems become increasingly complex, with multiple operating and failure modes, it is often necessary that test signals have predetermined timevarying attributes (e.g. waveshape, frequency, phase or amplitude) to enable emulation of some complex real-world behaviour. As part of a complex system test strategy, our test signal may be required to vary in waveshape as part of a real-time interaction with the system under test. This often means dynamic variation of waveshape to emulate the

42


output of a subsystem under specific conditions. Selecting a particular waveform or controlling the dynamic variation of waveshape is performed by computer control or from a control input derived from the system under test. Some test and diagnostic example applications include:

1.4.2

advanced automatic test equipment (ATE); control system test and diagnostics; signal processor test and diagnostics; shaped spectrum pseudo-random noise generation; audio amplifier harmonic and intermodulation distortion measurement; power supply load profile simulation.

Signal emulation applications Signal emulation involves controlled replication of a ‘signal of interest’, usually as part of a system test or diagnostic procedure. Examples include emulation of an accelerometer, vibration sensor, microphone or pressure sensor output signal according to a simulated virtual environment. Often, the emulated signal is generated by a computer model and can therefore include the deliberate addition of unique error features to assess system behaviour under abnormal conditions. Alternatively, the emulated signal can be based upon the capture of a ‘known good’ real signal, modified to add erroneous features if necessary. The test, diagnostic debug and design verification of measurement systems that transmit and receive a known signal (e.g. radar, sonar or ultrasound imaging systems) can use an AWG to emulate a received signal with complex timevarying properties. In this application, the AWG must be synchronised with the transmit event and receiver input gating to maintain a realistic closed-loop system. The waveform characteristics can be designed to simulate return signals corresponding to particular ‘target behaviours’ or transmit–receive channel distortion mechanisms (e.g. multipath phase distortion and fading effects).

f

q

A Channel 1

AWG AWG trigger (if required)

Waveform programming

Channel 2

System under test Test points

Synchronisation signal

Measurement system (e.g. DSO)

Figure 1.18 A rudimentary AWG-based test signal or signal emulation configuration.


43

A hypothetical test configuration is shown in Figure 1.18, where the AWG provides predefined test signals or synchronised signal emulation to the system under test. Typically, other equipment such as a digital storage oscilloscope (DSO) or spectrum analyser measures the system response signals to the AWG stimulus. Some signal emulation example applications include: signal detection, analysis and classification algorithm testing; signal-to-noise ratio (SNR) emulation; parametric sensor signal emulation (e.g. vibration transducers, accelerometers, geartrain acoustic sensors and biometric sensors); radar and sonar return signal emulation; physical-layer data waveform emulation; signal failure mode emulation.

1.4.3

Bespoke embedded applications Bespoke embedded signal generation covers AWG applications such as integrated complex signal sources or test signal generation as part of a system built-in self test (BIST) capability. This category also includes standalone applications such as laboratory test instrumentation whose primary function is not signal generation per se, but a measurement function that requires an internal signal source with unusual attributes. Some bespoke embedded example applications include:

1.4.4

test and measurement instrumentation; transducer excitation; built-in self test (BIST) signal generation; radar and active sonar; computer music synthesis.

RF up-conversion applications RF up-conversion describes a category of AWG applications where the band- spectra of near-baseband (i.e. no near-DC spectrum content) or intermediate frequency (IF) waveforms are up-converted to RF. This is accomplished by mixing with a local oscillator carrier signal at the desired RF frequency followed by image filtering. AWG signals whose band- spectrum is up-converted to RF have similar utility as test, diagnostic debug or emulated signals within baseband applications, only now we are working at a higher frequency part of the frequency spectrum (e.g. RF or microwave). AWG DAC performance limitations constrain the highest directly synthesisable frequency for a given upper bound of spurious error components in the output spectrum. Generating a desired arbitrary band- signal at near-baseband or IF and then upconverting to a specific frequency enables AWG utility to be extended into the RF or microwave range as illustrated by the two methods outlined in Figure 1.19. With a simple (i.e. single mixer) up-conversion approach as shown in Figure 1.19a it is important to eliminate near-DC spectrum content in the AWG waveform due to

44


Figure 1.19 Simple and quadrature up-conversion of an arbitrary waveform. The quadrature up-conversion simplifies or eliminates the image rejection filter.

limitations in the post up-conversion image rejection filter. An alternative, so-called quadrature up-conversion technique, is shown in Figure 1.19b and exploits the potential multi-channel capability of digital AWG to generate precisely quadrature output waveforms. Quadrature up-conversion eliminates or reduces the complexity of the image rejection filter and in principle allows the AWG waveform bandwidth to extend down to DC (i.e. a ‘true’ baseband signal). However, the technique requires a precisely matched quadrature mixer and local oscillator signals. Trimming the phase offset and relative amplitude of the quadrature AWG output signals provides one method for optimising image suppression performance in the RF signal. Some RF up-conversion example applications include:

quadrature carrier modulation; ultrasound imaging return signal emulation; electronic warfare jamming waveforms; general purpose RF or microwave complex signal generation.


1.4.5

45

Unique DDS AWG attributes Many attributes are provided by DDS AWG that are unattainable with analogue or hybrid methods and enable generation of signals with unique characteristics and wide utility. Some of the more important attributes that set DDS AWG apart from other signal generation techniques include: generation of -defined arbitrary waveforms (or their equivalent spectra) with precisely controlled frequency, phase and amplitude; essentially ‘drift-free’ output frequency; minimum synthesised frequency and frequency control resolution can be made arbitrarily small; generation of ‘polyphase’17 arbitrary waveforms with independently controlled waveshape and phase offset; generation of arbitrary waveform sequences; waveshape or spectrum interpolation according to a single control parameter;18 real-time adaptive waveshape according to a single control parameter. The accuracy of the generated waveform or spectrum (i.e. the similarity between specified and generated signals) is ultimately bound by only three design parameters: the sample rate and hence Nyquist bandwidth, arithmetic quantisation (i.e. the number of bits used to represent the waveform samples) and DAC linearity errors (including all analogue post-processing). For a given bandwidth, which is typically less than the Nyquist limit, DDS algorithm synthesis errors can, at least in principle, be made vanishingly small with the application of sufficient digital processing power (e.g. increased wavetable memory length and high-order phase–amplitude mapping interpolation). Finally, a distinct and fundamental feature of all fixed sample rate DDS techniques is their inherent19 suitability to multi-channel implementation through a process known as time-division multiplexing. This enables the economic generation of independently controlled, polyphase arbitrary waveforms.

1.4.6

A simple example – testing a PLL We conclude this section by outlining a simple but illuminating test application that exploits the unique properties of DDS AWG to the functional test, diagnostic debug and design verification of a simple phase locked loop (PLL). The PLL under test could be a simple FM demodulator or part of a complex fractional-N frequency synthesiser with demanding lock-in time and noise immunity requirements that need 17

18

19

We define ‘polyphase’ waveforms as those generated by multiple synchronised AWGs whose phase offsets can be set relative to a reference output. In this context ‘parametric control’ describes a form of waveshape modulation according to an analogue or digital input parameter (e.g. a control voltage or digital data). Digital systems which use a fixed sample rate may be time-division multiplexed to realise multiple instantiations of a given function or operation with essentially one set of hardware. For a given hardware speed, the price paid is a pro-rata reduction in the effective sample rate for each channel.

46


PLL filter response control

Phase detector

VCO

Figure 1.20 An adaptive PLL showing hypothetical test and response signals.

to be verified or debugged during development. The fundamental nature of the PLL function suggests some possible test waveforms: triggered or periodic waveform bursts with varying amplitude, frequency and signalto-noise ratio over the burst interval; continuous waveforms with time-varying (or parametrically controlled) amplitude, frequency and signal-to-noise ratio (SNR); continuous waveforms with specific waveshape, harmonic distortion or other spectrum-related properties; continuous waveforms with periodic (or randomly distributed) fault-mode behaviours such as transients at specific parts of the waveform cycle and ‘drop-outs’ of varying duration and distribution. Figure 1.20 illustrates a simple second-order PLL comprising a phase detector, voltagecontrolled low- loop filter and voltage-controlled oscillator (VCO). The voltagecontrolled loop filter provides an example of adaptive PLL functionality according to an external control system that determines loop behaviour and is typical of many realworld PLL systems. As a negative system, the PLL can be tested by injecting an input signal whose characteristics are ‘engineered’ to expose particular properties of the closed-loop behaviour that can be measured by appropriate means. For example, specific input signals are required to accurately measure acquisition time, lock-in range, capture range, capture transient and noise immunity [14]. To measure these properties and thereby determine PLL behaviour, key signals within the loop (e.g. the phase detector and loop filter outputs) are measured using appropriate instrumentation (e.g. a digital storage oscilloscope or voltmeter). It is not uncommon for the low- loop filter to have voltage-controlled breakpoint frequencies to provide real-time control of bandwidth and response shape as part of an adaptive PLL. In conjunction with an external control system, the adaptive PLL can dynamically optimise such properties as acquisition time and noise immunity. Comprehensive testing of an adaptive PLL therefore requires at least two independent test

1.5 Summary

47

stimuli – an input signal having known time-varying properties and a synchronised loop filter voltage control signal. Figure 1.20 shows example input test signals where the PLL input signal is arranged to have a step reduction in signal-to-noise ratio just before a step frequency increase. A possible loop filter control signal is also shown which varies around the input signal frequency transition. In this simple and somewhat idealised test scenario, a PLL output signal exhibiting a clean frequency transition indicates a well-behaved PLL design. The AWG can also be used as a signal source to evaluate the performance of the individual PLL functional blocks. For example, the phase detector and loop filter can be tested in isolation from the main loop by applying a pair of coherent signals from a twochannel AWG. The phase offset, signal-to-noise ratio and other application-specific properties (e.g. varying waveshape) of these signals can be fixed or arranged to vary over time to exercise the phase detector under simulated real-world conditions. Similarly, emulation of the phase detector output waveform with time-varying input phase offsets can be used to evaluate loop filter and VCO behaviour.

1.5

Summary After an introductory section, two important continuous-time concepts which underpin digital waveform generation have been introduced. Firstly, the modulo bounding of a continuous instantaneous phase function to generate periodic phase functions with programmable frequency; and secondly the idea of distinct instantaneous phase and phase to amplitude conversion functions. This latter idea is very important – it is essentially the continuous-time equivalent of discrete-time phase accumulation frequency synthesis which underpins this book. We extend these concepts into the discrete-time domain beginning in Chapter 2, and in Chapter 4 we investigate sinusoidal DDS. We have presented an outline history of digital waveform generation beginning with the seminal paper by Tierney et al., and indicated earlier work in the realm of computer music software that has exploited the same fundamental principles. A simple taxonomy of the most prevalent electronic waveform generation techniques has been presented. This leads us to the DDS subclass, whose generalised form enables the generation of arbitrary waveforms and their corresponding spectra which is the focus of this book. For completeness, we also include the digital recursive oscillator subclass. To help provide some historical context and to help justify the need for exploiting digital techniques, we present several important analogue waveform generation circuits that represent landmarks in that field. These circuits are discussed in sufficient detail to reveal their common sensitivity to particular analogue error mechanisms which we summarise. Finally, we indicate that these error mechanisms are eliminated or at least mitigated by the application of digital techniques. We conclude Chapter 1 with an outline of some important AWG application areas that are either self-evident or have been reported and which we group into four overlapping categories. It is hoped that these will provide the reader with ‘food for thought’ and help spawn new application areas or development of the techniques presented in this book.

48


1.6

References 1. V. F. Kroupa, Direct Digital Frequency Synthesizers, IEEE Press, 1999. 2. J. Tierney, C. M. Rader, and B. Gold, ‘A digital frequency synthesizer’, IEEE Transactions on Audio and Electroacoustics, Vol. AU-19, No. 1, pp. 48–57, 1971. 3. J. H. Appleton and R. C. Perera, The Development and Practice of Electronic Music, Prentice-Hall, Inc, 1975. 4. W. Kester, Data Conversion Handbook, Newnes, 2005. 5. J. A. Crawford, Frequency Synthesizer Design Handbook, Artech House, Inc, 1994. 6. J. B. Hagen, Radio-Frequency Electronics, 2nd edition, Cambridge University Press, 2009. 7. XYZs of Signal Generators. Tektronix technical publication www.tektronix.com/ signal_generators. 8. J. Mercadé, Waveform generators vary in architecture. Available online at http://www. arbitrary.es/s.html, 2010. 9. J. Mercadé, DAC interleaving in ultra-high speed arbs. Available online at http://www. arbitrary.es/s.html, 2009. 10. J. Williams, Analog Circuit Design – Art, Science and Personalities. EDN Series for Design Engineers, Butterworth-Heinemann, Inc, 1991. 11. W. Jung, IC Op-Amp Cookbook, 3rd edition, Howard W. Sams & Co, 1989. 12. J. D. Foote, C. J. Boyan, G. D. Pontis and C. Y. Lau ‘A complete self-contained audio measurement system’, Hewlett Packard Journal, August 1980. 13. Tektronix, SG505 Oscillator Instruction Manual, 1979. 14. R. E. Best, Phase-Locked Loops – Design, Simulation and Applications, McGraw-Hill, 1999.

2


We begin this chapter by reviewing some important mathematical principles that underpin digital waveform generation. We then proceed to introduce and develop a concept which is central to this book – sampling a tabulated signal – and an associated concept – the wavetable. After introducing the wavetable as a fundamental building block, we consider several methods for specifying an arbitrary waveform function that is tabulated within it. Section 2.4 introduces phase accumulation frequency synthesis and phase– amplitude mapping based upon wavetable lookup as the foundations of what we call generalised direct digital synthesis (DDS). This section also outlines some important error mechanisms that are fundamental to the technique, and whose mitigation is the topic of later chapters. We conclude this chapter by reviewing the principal control parameters of a digital waveform generation system against their ideal characteristics. Finally, we define some qualitative performance metrics that we use in later chapters to investigate the effects of design and control parameter changes using computational simulation of a mathematical model. These metrics are also used to compare different waveform generation algorithms under identical control parameter conditions.

2.1

Mathematical preliminaries In this section we briefly review some important mathematical concepts which underpin the generation of electronic signals by digital means, particularly those based upon phase accumulation and phase–amplitude mapping (i.e. DDS). Our objective is to provide a sufficiently detailed review to enable an understanding of the concepts presented in later chapters. We begin with a review of continuous and discrete-time signals.

2.1.1

Continuous- and discrete-time signals A continuous-time sinusoidal signal ^y ðtÞ is defined by the expression: ^y ðtÞ ¼ Acos ðΩt þ θÞ, t 2 ð∞, ∞Þ, where A is the amplitude of the sinusoid, Ω is the angular frequency in radians per second, θ is the phase offset in radians and t is time. We can also describe the frequency f in cycles per second or hertz (Hz), since Ω 2πf, and obtain: ^y ðtÞ ¼ A cosð2π f t þ θÞ, t 2 ð∞, ∞Þ:

ð2:1Þ

50


We use the cosine function as this satisfies the requirement that the zero frequency condition give a DC value equivalent to the amplitude A. The continuous-time sinusoidal signal ^y ðtÞ has the following properties: for every fixed value of f, ^y ðtÞ is periodic and so ^y ðt þ τÞ ¼ ^y ðtÞ, where the fundamental period τ ¼ 1/f; continuous-time sinusoids with different frequencies are themselves distinct; the frequency of a continuous-time sinusoid is unbounded; increasing the frequency f increases the rate of oscillation and produces more cycles within a given time interval. We can also define non-sinusoidal continuous-time signals. Any periodic continuoustime waveform ^y w ðtÞ can be represented (or at least approximated) by a linear combination of Nh sinusoids with harmonically related frequencies and suitably weighted amplitudes and phases, thus: ^y w ðtÞ ¼

Nh X

Ak cosð2πkf t þ θk Þ,

ð2:2Þ

k¼1

where Nh denotes the highest harmonic number in the set of harmonically related sinusoidal frequency components that make up ^y w ðtÞ, Ak denotes a vector of harmonic amplitude coefficients, θk denotes a vector of harmonic phase coefficients and f is the fundamental frequency of ^y w ðtÞ in cycles per second. The bandwidth of this discrete spectrum, continuous-time signal is defined by the highest frequency component and is simply Nh f. In the frequency domain, the spectrum of our sinusoidal signal comprises a single line with amplitude A and frequency f. Similarly, the spectrum of our nonsinusoidal weighted harmonic series waveform comprises multiple harmonically-spaced lines with amplitudes corresponding to the respective Ak and fundamental frequency f. A generalised discrete-time sinusoidal signal y(n) is defined by the sequence y(n) ¼ A cos(ωn þ θ), n 2 (∞, ∞), where A is the amplitude of the sinusoid, ω is the angular frequency in radians per sample, θ is the phase offset in radians and n is the sample index which counts discrete-time intervals and takes on only integer values. Since ω ¼ 2πfd, where fd represents the digital frequency of the discrete-time sinusoid in cycles per sample, we can express the discrete-time sinusoid as: yðnÞ ¼ A cosð2πfd n þ θÞ,

n 2 ð∞, ∞Þ:

ð2:3Þ

Discrete-time sinusoids have several important properties: 1. A discrete-time sinusoid is periodic only if its frequency fd is a rational number (i.e. the ratio of two integers). 2. Discrete-time sinusoids whose angular frequencies are separated by integer multiples of 2π are identical. 3. Discrete-time sinusoids with frequencies jωj π or j fd j 12 are unique. A discretetime sinusoidal sequence with frequency jωj > π or j fd j > 12 is identical to a

2.1 Mathematical preliminaries

51

sequence where jωj < π or j fd j < 12. We call the sinusoid with frequency jωj > π an alias of a corresponding sinusoid with frequency jωj < π. 4. The highest frequency of a discrete-time sinusoid is attained when ω ¼ π, or equivalently when fd ¼ 12. We can prove the first property by considering the fundamental period of a discrete-time sequence which is defined as the smallest value of N for which y(n þ N ) ¼ y(n) [1]. Therefore, for a discrete-time sinusoid to be periodic we require cos(2πfd (n þ N) þ θ) ¼ cos(2πfdn þ θ), which is satisfied if and only if there exists an integer k such that 2πfdN ¼ 2kπ or, equivalently, fd ¼ k/N. Since fd is the ratio of two integers, fd must be a rational number. Property 2 follows from the expression of a discrete-time sinusoid when we add a 2kπ offset to the angular frequency term giving cos(ωn þ 2kπn þ θ) cos (ωn þ θ) for all integer values of k. We observe that a small change in the frequency of a discrete-time sinusoid can result in a large change in the fundamental period. Consider f1 ¼ 23/40, which gives N1 ¼ 40, while f2 ¼ 24/40 gives N2 ¼ 5. We now consider the periodic sampling of a continuous-time sinusoidal signal ^y ðtÞ where t only takes on equally spaced discrete values. Sampling the continuous-time sinusoid ^y ðtÞ ¼ A cosð2πf t þ θÞ every T seconds at a sample frequency fs ¼ 1/T establishes the relationship t ¼ nT ¼ n/fs and yields the discrete-time sinusoid ^y ðnT Þ yðnÞ ¼ A cosð2πf nT þ θÞ ¼ A cosð2πn f =fs þ θÞ. Comparing this expression with the generalised discrete-time sinusoid of Eq. (2.3) we determine that fd ¼ f /fs, which we also call the normalised frequency of the sinusoid. The relationship between fd and f can only be defined if the sampling frequency is known. The minimum sampling frequency is bound by the Nyquist sampling theorem [2] which requires that the maximum frequency of our sinusoid satisfies the inequality fmax fs/2. The frequency band from DC to fs/2 is variously known as the Nyquist interval, Nyquist region or Nyquist bandwidth. The normalised frequency is therefore bound on the interval [0,0.5). We can also periodically sample the non-sinusoidal waveform ^y w ðtÞ as defined by Eq. (2.2) to give: yw ðnÞ ¼

Nh X k¼1

Ak cosð2πkf nT þ θk Þ ¼

Nh X

Ak cosð2πkn f=fs þ θk ),

ð2:4Þ

k¼1

where f 2 [fs/2, fs/2]. Equation (2.4) represents a discrete-time arbitrary waveform sequence according to a weighted harmonic series specification. For Nh ¼ 1, Eq. (2.4) reduces to the discrete-time sinusoid definition. The sampling process produces images or aliases of the signal frequency around all harmonics of the sampling frequency. In general, a spectrum component with frequency f will have alias images located symmetrically around integer multiples of the sampling frequency, whose frequencies are given by kfs f with k ¼ 1, 2, 3,. . .. The amplitudes of these images follow a sin x/x or sinc function frequency response due to the staircase or ‘sample/hold’ nature of the digital to

52


Nyquist region

Sine spectrum

1st image

2nd image

Amplitude (dB)

Zero-order hold response

fs − f f

fs + f 3 fs

fs 2 Harmonic spectrum

fs

2 fs

fs

2

3 fs

Frequency

Figure 2.1 The spectra of discrete-time single sinusoid and multi-harmonic signals illustrating

spectrum replication due to aliasing. The frequency response of the zero-order hold is also shown.

analogue convertor (DAC) reconstructor. More formally, this frequency response is due to a zero-order hold reconstructor. Figure 2.1 illustrates the spectrum replication nature of aliasing that occurs in the spectra of discrete-time sampled signals, and shows the spectra of a discrete-time sinusoid and a simple multi-harmonic waveform.

2.1.2

The phase–frequency relationship of a discrete-time sinusoid The instantaneous phase ϕ(t) and frequency f (t) of a continuous-time sinusoid are mutually related according to the simple integral and differential equations: ðt ϕðtÞ ¼ 2π f ðτÞdτ þ ϕð0Þ

ð2:5Þ

0

and f ðtÞ ¼

1 dϕðtÞ : 2π dt

ð2:6Þ

If we set the initial condition ϕ(0) ¼ θ where θ denotes the initial phase or phase offset in radians, the instantaneous phase ϕ(t) ¼ 2πft þ θ is in exact agreement with that of a continuous-time sinusoid with constant frequency.


φ (n)

53

Phase (radians)

φ (t ) = 2π ft

φ (n) = 2π fnT

T

φ (n) = 2π fnT

2π 0

10

2π

20

Sample index

n

Figure 2.2 Unwrapped and wrapped discrete-time instantaneous phase functions.

We can define the instantaneous phase ϕ(n) of a discrete-time sinusoid by replacing the continuous integral with a discrete summation, thus: ϕðnÞ ¼ 2πT

n X

f ðmÞ þ ϕð0Þ:

ð2:7Þ

m¼0

The summation operation represents an accumulation of the instantaneous frequency parameter f (n) at the sample rate and may also be expressed as the difference equation: ϕðnÞ ¼ ðϕðn 1Þ þ 2πf ðnÞT Þ:

ð2:8Þ

Assuming a constant frequency f, setting the initial condition ϕ(1) ¼ θ 2πf T gives ϕ(0) ¼ θ and hence the general solution ϕ(n) ¼ (2π fnT þ θ). This expression for the radian-valued instantaneous phase ϕ(n) is in exact agreement with that of a discrete-time sinusoid. For the constant frequency condition, we observe that ϕ(t) and ϕ(n) describe a ramp function with constant slope 2πf and unbounded amplitude which we call the unwrapped phase in a similar manner to the continuous-time case. The discrete-time phase–amplitude mapping of a periodic waveform function (e.g. a sine function or a weighted Fourier series) effectively imposes a modulo 2π bounding on ϕ(n) which we call the wrapped phase and follows a periodic sawtooth function on [0, 2π). Figure 2.2 illustrates some simple examples of unwrapped and wrapped discrete-time instantaneous phase functions at constant frequency. Hypothetically, we can compute ϕ(n) in radians by a modulo 2π accumulation of a radian valued phase increment parameter defined by φ ¼ 2πfT ¼ 2πf /fs with φ 2 [0, π). ϕ(n) is then defined by the modulo 2π difference equation: ϕðnÞ ¼ hϕðn 1Þ þ φi2π :

ð2:9Þ

If we compute Eq. (2.9) at the sample rate fs we observe that the slope (and hence frequency) of the ϕ(n) sequence is a function of φ alone. We observe in the example of Figure 2.2 that the wrapped phase sequence is identical on each cycle. This occurs only if the ratio fs /f is an integer (i.e. the sample frequency is an exact integer multiple of the

54


signal frequency). When this condition is not satisfied there is a cyclic repetition of a locally periodic phase sequence whose frequency as measured by the average number of steps per cycle (i.e. the period) is in exact agreement with fs/f. We consider the behaviour of phase accumulator output sequences and their average frequency further in Section 2.4.1.

2.1.3

Analogue reconstruction and alias image rejection Reconstruction describes the process by which we convert from a sequence of numerical values spaced at the sampling interval T to a continuous-time analogue signal. Mathematically, we represent the discrete-time sequence as impulses whose height represents the sample value at the sampling instant. Fundamentally, analogue reconstruction represents a low- filtering of the sampled signal. The ideal reconstructor is defined by an unattainable ‘brick wall’ response with unity gain from DC to fs/2 and zero everywhere above fs/2. A practical reconstructor is the digital to analogue staircase or sample/hold reconstructor which fills the gaps between sample impulses by holding the current sample value constant until the next sample. Such reconstructors are generally known as digital to analogue convertors (DAC) or staircase reconstructors. The staircase reconstructor is the simplest reconstructor and most widely applied. It generates a piecewise-constant approximation to the original signal and has a frequency response H( f ) ¼ T (sin(πfT )/ πfT )eπj f T. The magnitude response jH( f )j exhibits nulls at integral multiples of the sampling frequency fs exactly where the alias images are centred. However, the stop-band above fs / 2 does not completely eliminate the replicated alias images. To suppress alias images above fs / 2 we use an analogue low- filter after the digital to analogue convertor. This filter is variously known as an anti-aliasing filter, image rejection filter or reconstruction filter. In practice, this filter works in conjunction with the staircase reconstructor to suppress alias images and approximate the ideal reconstructor. The ideal low- filter response is unity from DC to the Nyquist frequency and zero elsewhere – unattainable in practice. Real-world anti-aliasing filters have a finite stop-band suppression.

2.1.4

Quantisation and digital to analogue conversion Sampling and amplitude quantisation of analogue signals are fundamental digital signal processing operations. An analogue signal with full-scale dynamic range V and quantised to b-bits, has 2b quantisation levels. The corresponding quantisation width is then given by q ¼ V/2b. Assuming a bipolar analogue signal that swings symmetrically about zero, the discrete-time quantised signal yq(nT) satisfies the inequality V/2 yq(nT) < V/2. The maximum level is (V/2) q. Amplitude quantisation introduces an error in the quantised signal since analogue signals samples are approximated to the nearest quantisation level using rounding or truncation. The amplitude error sequence is given by ε(nT ) ¼ yq(nT ) y(nT ) and is always bound on the interval ε(nT) 2 [q/2, q/2]. The RMS value of ε(nT ) is given by pffiffiffiffiffi εðnT ÞRMS ¼ q= 12 [2] and can be considered as a noise signal that sets a lower bound on the dynamic range of the quantisation process. If we consider V and q as the ranges of the signal and quantisation noise, respectively, we may define the dynamic range of the quantisation process as a signal-to-noise ratio

2.2 A fundamental concept – sampling a tabulated signal

55

given by SNR ¼ 20log (V/q). We observe that SNR ¼ 6b and is known as the 6 dB per bit rule. If we know the full-scale range and the permissible RMS error in a given application, we may determine the number of DAC bits required to achieve a given SNR and dynamic range.

2.2

A fundamental concept – sampling a tabulated signal In this section we introduce a fundamental concept in digital sinusoidal and arbitrary waveform generation – sampling a periodic signal tabulated in a lookup table. This concept is fundamental to phase accumulation frequency synthesis and arbitrary waveform generation that we discuss later. In the context of waveform generation we call the lookup table a wavetable. In Section 2.2.1 we discuss the important properties of a wavetable and present several methods for specifying the waveform function tabulated within it. For our present discussion, we abstract the wavetable as a vector of discretetime (strictly discrete-phase) contiguous signal samples that are obtained by sampling a continuous-time signal at a suitable sampling frequency. As we will see later, the tabulated samples are usually computed as an ‘off line’ arithmetic operation according to a particular waveform specification method.

2.2.1

Tabulating a signal – introducing the wavetable We begin by sampling a continuous-time sinusoidal signal to generate contiguous samples that we store as a vector in consecutive memory locations. This enables us to relate the tabulated signal (which is just a sequence of numbers) to a ‘real’ continuoustime signal through the sampling process. We call this process tabulation and the memory-based vector a lookup table or wavetable. Let us assume a wavetable of radix-2 length L ¼ 2M with M 2 N that is filled with uniformly spaced samples of a continuous-time sinusoidal signal of frequency fx Hz given by x(t) ¼ sin(2πfxt). To accomplish this our wavetable is addressed by a variable increment M-bit counter that is set to increment by unit amounts on each sample clock. We represent the wavetable by the vector W where W[a] denotes the ath element of the vector. In our present example, the wavetable address a is provided by the sample index sequence a(n) 2 [0, L 1] when the wavetable is being filled with our sampled signal. The sinusoidal signal x(t) is sampled at fs samples per second starting from t ¼ 0 until the wavetable contains L contiguous samples of the corresponding discrete-time sequence x(n) ¼ sin(2πfxnT), with n 2 [0, L 1] and T ¼ 1/fs seconds. We observe that the sampling process can be described by the substitution t ¼ nT in the continuous-time function x(t). The number of cycles of x(n) contained in the wavetable is given by Nc ¼ fxL/fs with Nc 2 [1, L/2) to satisfy the requirements of the Nyquist sampling theorem. Furthermore, tabulation of x(n) must be arranged so that Nc always takes on exactly integer values to prevent a discontinuity between the beginning and end points of the wavetable. With a fixed value of fs, only sinusoids whose frequencies are integer multiples of fs /L can be tabulated (i.e. fx ¼ Nc fs /L with Nc 2 [1, L/2)) if we are to avoid an endpoint

56


fs x(t )

Low filter

ADC

y (m)

x(n)

Wavetable write (fill)

DAC

Low filter

y (t )

Wavetable read (regenerate)

Data

Wavetable Address Counter increment

M Write = 1 Read =

L = 2 M samples

M-bit counter

fs Figure 2.3 Conceptual arrangement for sampling, tabulating and regenerating a continuous-time sinusoidal signal.

discontinuity. We also observe that the number of samples per cycle, fs /fx ¼ L/Nc, is the only frequency related information preserved when a signal is tabulated.

2.2.2

Regenerating a tabulated signal We can regenerate the tabulated signal at a new frequency f by setting the variable increment M-bit address counter to increment continuously by φ counts on every sample clock (i.e. every T ¼ 1/fs seconds). To differentiate the wavetable signal regeneration and fill processes we use the sample index variable m in our sequence denotations. The M-bit wavetable address sequence a(m) now cycles continuously modulo L ¼ 2M and may be expressed by the modulo function a(m) ¼ 〈mφ〉L, where the function 〈a〉b denotes ‘a modulo b’. The a(m) sequence represents the phase argument of the tabulated signal that we wish to regenerate. Although not strictly pertinent to our present discussion, the M-bit variable increment counter can also be thought of as a phase accumulator with phase increment φ. This is an important distinction and fundamental to generalised direct digital synthesis that we investigate later. The wavetable output samples y(m) are fed to a digital to analogue converter (DAC) and low- reconstruction filter to generate a continuous-time signal y(t). This conceptual arrangement is illustrated in Figure 2.3 where the wavetable is filled by setting φ ¼ 1 until L samples have been written into the wavetable memory.1 Conversely, the tabulated signal is regenerated by reading from the wavetable with arbitrary values of φ. 1

The signal samples tabulated in the wavetable are normally pre-computed from a periodic waveform function that maps phase to amplitude (e.g. the sine function).

2.2 A fundamental concept – sampling a tabulated signal

57

If we set φ ¼ 1, the output signal from the low- reconstruction filter is identical to the original signal that was sampled to fill the wavetable (i.e. y(t) ¼ x(t)), ignoring a small phase shift due to the reconstruction filter.

2.2.3

A sample rate conversion view When φ > 1 the tabulated sinusoid is said to be decimated since wavetable samples are skipped according to the value of φ as the wavetable is indexed and samples read out and fed to the DAC. It is essential at this point to appreciate a fundamental principle that is now apparent. This process is equivalent to the original sinusoid x(t) being sampled at a lower sample frequency than the tabulation sample frequency fs, but fed to the DAC at the sample frequency fs. This can be viewed as a sample rate conversion of the tabulated data which causes an increase in the regenerated signal frequency when φ > 1, as illustrated in Figure 2.4.

W[a]

Wavetable x(n)

ϕ=2

ϕ=2

x(t )

f s′ = 0.5 f s

f x = 1 LT a

Regenerated signal

y(m)

y (m) T mT

y (t ) f y = 2 LT

Figure 2.4 Wavetable indexing viewed as a sample rate conversion process.

58


An address increment of φ > 1 represents a wavetable ‘resample interval’ of φT seconds or equivalently a wavetable resampling frequency of f s0 ¼ fs /φ. For Nc tabulated sinusoid cycles, we have L/Nc samples per cycle and so φ 2 [1, L/2Nc) to satisfy the requirements of the Nyquist sampling theorem. We may represent the wavetable which tabulates the discrete-time sinusoid x(n) by the vector expression W[a] ¼ sin(2πa/L) with a 2 [0, L 1]. The regenerated waveform is then given by y(m) ¼ W[〈mφ〉L] and since φ ¼ fs /f s0 we obtain y(m) ¼ cos(2π/L〈m fs /f s0〉L). We observe that this expression defines y(m) as a function of the ratio of two sample frequencies, thereby ing the sample rate conversion view. As the modulo wavetable indexing proceeds, the wavetable is cycled every L/Ncφfs seconds producing an output frequency given by fy ¼ Ncφfs /L Hz. If we eliminate Nc from this expression by substituting Nc ¼ fxL/fs we obtain fy ¼ φfx where φ 2 [1, L/2). This expression reveals that this method of wavetable indexing can only generate integer multiples of the original sinusoid frequency fx ¼ Nc fs /L. When Nc ¼ 1, our wavetable tabulates a single sine wave cycle and we obtain: fy ¼

φfs φfs ¼ M: L 2

ð2:10Þ

This conceptual example has described a rudimentary waveform generator with programmable frequency constrained to integer multiples of the original signal frequency fx. Since Nc ¼ 1, it is clear that for a fixed sample rate and integer address increments, we can increase the output frequency only in integer multiples of a minimum frequency fs /L ¼ fs /2M.

2.2.4

Frequency control resolution and wavetable length The frequency control resolution of this simple waveform generator is defined by dfy /dφ ¼ fs /2M, and for a fixed sample frequency is governed by the number of bits in the address counter M. While an arbitrarily small frequency control resolution can be obtained by choosing a suitably large value of M, we observe that the wavetable length increases exponentially with M. This soon leads to impractically large wavetables for values of M consistent with typical frequency control resolution requirements. This can be dramatically illustrated with a simple example. Let us assume we have a sample frequency of 250 MHz and require a frequency control resolution of better than 0.1 Hz, which is not an unreasonable requirement. The minimum value of M which satisfies this requirement is 32 and equates to a wavetable length of 232 samples – a somewhat impractical figure. Aside from the cost and design issues of implementing very large, ultrafast memories there is a more fundamental restriction on wavetable length – wavetable fill time. Invariably, wavetables have to be filled, which means evaluating a wavetable function at fixed phase increments to obtain the samples, storing those samples for later recall and ing them into the wavetable memory as required. Several important features are evident from this conceptual waveform generator: frequency control resolution is fs /2M and can be made arbitrarily small only by reducing fs or increasing M;

2.3 Tabulating a waveform function

59

M output frequency is an integer multiple of fs/2 ; M wavetable length and therefore memory requirement is 2 and so increases exponentially with M; wavetable fill time increases exponentially with M; the 2M wavetable samples could have been pre-computed from a periodic waveform function at phase points equally spaced by 2π/2M radians.

An important and fundamental question is now apparent: for a given sample frequency, how can we achieve arbitrarily small frequency control resolution yet maintain a manageably small wavetable length? It turns out that the answer to this question is ingeniously simple and introduces the concepts of fractional addressing and wavetable phase interpolation, which completely remove an otherwise interdependence between the frequency control resolution and wavetable length design parameters. We investigate these concepts further in Section 2.4 when we formalise the sampling of a tabulated signal into phase accumulation and phase–amplitude mapping. However, we must first develop our understanding of a fundamental building block in digital waveform generation – the wavetable and the tabulation of a mathematically defined waveform function.

2.3

Tabulating a waveform function

2.3.1

The wavetable revisited With the exception of some important recursive sine wave generation techniques discussed in Chapter 3, all of the waveform generation techniques presented in this book are based upon the generic model of phase accumulation frequency synthesis followed by phase–amplitude mapping using a wavetable to generate a waveform amplitude sample sequence. For generation of sinusoidal signals this technique is well established and widely known as direct digital synthesis or DDS in the literature [3]. From now on, we generalise the DDS acronym to denote a fundamental principle rather than sinusoidal DDS specifically. As we will see, the principles of sinusoidal DDS are extendable to the generation of arbitrary waveforms where we generalise the phase– amplitude mapping operation. We call this technique DDS arbitrary waveform generation or DDS AWG and for the most part, the wavetable is a fundamental element. In this section we develop the wavetable concept introduced in Section 2.2 as a fundamental operation in DDS AWG. We formally define a wavetable as a vector of regularly time-sampled, amplitude-quantised waveform samples stored in consecutive memory locations as a sequence of binary numbers with a defined number representation format. The tabulated waveform is typically a single cycle of a periodic waveform function (e.g. a sine wave), although any integral number of cycles is permissible subject to sampling limitations that we consider later. A wavetable performs a discrete-time translation from the phase to amplitude domain according to its tabulated function – the so-called phase–amplitude mapping operation. Therefore, a wavetable should strictly be thought of as comprising a vector of phase indexed amplitude samples. The tabulated sample values are necessarily quantised in amplitude and

60


therefore require a particular number of bits in the memory word and number representation format (e.g. 16 bit, fixed-point 2’s complement). The wavetable samples may be generated directly from a time domain waveshape specification or computed using the inverse discrete Fourier transform (IDFT) from a frequency domain specification comprising harmonic amplitude and phase parameters. We begin by considering the simplest time domain specification method based upon the sine function.

2.3.2

Tabulating the sine function To begin our investigation of waveform function tabulation we consider tabulation of the sinusoidal function. Tabulating any periodic function requires consideration of two variables: the independent variable – phase – and the dependent variable – amplitude. In the digital domain, both of these variables necessarily take on discrete or quantised values. When computing samples of a discrete-time signal in real time, the independent phase variable is a function of discrete-time nT, where n is the sample index and T is the sampling period. However, as a non-real-time, ‘off line’ process, waveform function tabulation requires that the phase variable is only a function of the wavetable address. The nature of digital storage requires that the amplitude variable is quantised according to a particular number of amplitude bits that determines quantisation noise. We now consider amplitude quantisation in an analytic form irrespective of any number coding scheme that would be used in a real-world implementation (e.g. fixed-point 2’s complement or sign-magnitude). We define a so-called rounding2 quantiser with input range xmax by the function: QðxÞ ¼ sgnðxÞ q

j jxj q

þ

1k , 2

ð2:11Þ

where the function sgn(x) returns the sign of x, ⌊z⌋ returns the largest integer z and q denotes the quantisation interval given by q ¼ xmax/2b1 for b 1 magnitude bits in the number representation (i.e. b bits including a sign bit). If we assume normalised amplitude and so xmax ¼ 1, we have q ¼ 2(b1). We now consider the phase argument of a tabulated sine function. A function f(x) is periodic with period τ if f (x) f (x þ τ), where x denotes the independent phase variable. When we tabulate the sine function we have f(x) ¼ sin(x) and observe that the periodicity condition is satisfied when τ ¼ 2π. The sine function should therefore be tabulated on the phase interval x 2 [0, 2π), which corresponds to the wavetable address range [0, L 1], where L is the wavetable length in samples.3 To ensure this correspondence, we must preserve the equality x/2π ¼ a/L when calculating the tabulated 2

3

Quantisers may be classified into two types – mid-tread and mid-riser – analogising the quantiser output to a ‘staircase’. The mid-tread or rounding quantiser has a defined zero output level corresponding to the tread of a staircase. We will see later that the wavetable length can also be ‘measured’ in samples per cycle assuming a single cycle of a periodic function is tabulated.

61


1 0.875 0.75 0.625

Sample amplitude

0.5

W[a ] = Q sin

0.375 0.25

2 16

0.125 0 − 0.125 − 0.25

sin a

2π 16

4

5

− 0.375 − 0.5 − 0.625 − 0.75 − 0.875 −1

0

1

2

3

6

7

8

9

10

11

12

13

14

15

Wavetable address a Figure 2.5 A simple sinusoidal wavetable. Note the amplitude error due to quantisation.

values of f (x) to ensure phase continuity at the wavetable boundaries, where a 2 [0, L 1] denotes the wavetable address. The phase argument of our periodic function sin(x) is therefore given by x ¼ 2π a/L, where a 2 [0, L 1]. We observe that a is analogous to the phase of the tabulated signal with a resolution of 2π/L radians. Sine and cosine wavetables of length L samples and amplitude-quantised to b bits are therefore defined thus: 2π W½a ¼ Q sin a , ð2:12Þ L 2π , ð2:13Þ W½a ¼ Q cos a L where W[a] denotes the amplitude-quantised sample in the ath location of the wavetable vector W. Wavetables generated using Eqs. (2.12) and (2.13) satisfy the periodicity requirements W[a] W[a þ L] and W[L] W[0], with the beginning and end samples exactly phase-continuous as required. Figure 2.5 illustrates a simple sinusoidal wavetable comprising 16 locations with 4-bit amplitude quantisation. It is informative to compare a sinusoidal wavetable defined according to Eqs. (2.12) and (2.13) with a generalised discrete-time sinusoid of frequency f defined by y(n) ¼ sin(2πn f/fs), where fs is the sample frequency and n is the time index. If we take the first fs /f samples of y(n) we have effectively compiled a wavetable of length fs /f comprising exactly one cycle of y(n). We observe that the ratio fs /f is therefore analogous to the wavetable length L measured in samples per cycle and is the only frequency related information preserved in the tabulation of a periodic signal. Similarly, the time index n is analogous to the wavetable address a over the interval [0, L 1].

62


2.3.3

Time domain arbitrary waveform specification In many applications, we are only concerned with the shape of an arbitrary waveform described as a ‘voltage-time contour’ and not its corresponding spectrum. In this section we consider wavetable tabulation of arbitrary waveform functions that are specified in of time domain (i.e. waveshape) properties. Before proceeding, we must appreciate that a wavetable lookup performs a phase–amplitude mapping operation where the wavetable index corresponds to the phase argument of the tabulated function. Only when the phase argument (i.e. wavetable index) is a linear function of time do we generate a periodically repeating waveform according to the tabulated function. Irrespective of the specification method, we define and tabulate our periodic waveform function over the phase argument interval [0, 2π] radians which corresponds to exactly one4 cycle. If a periodic amplitude step discontinuity (e.g. as in the sawtooth waveform) is not part of the waveform specification, the beginning and end points of the waveform must be contiguous.5 We may specify the shape of an arbitrary waveform using several methods which comprise: ‘drawing’ the waveform from scratch as a voltage-time graph; using a piecewise linear (PWL) description to approximate a voltage-time graph as a set of contiguous linear segments whose vertices are precisely defined; using a mathematical function to define the waveform exactly; editing a ‘real’ waveform captured on a digital storage oscilloscope (DSO). Drawing a waveform function as a graph of voltage against time over one period is an obvious way to think of and specify a particular waveshape although not necessarily a very precise one. Maintaining a one–one time-voltage correspondence between the beginning and end points of the record is particularly difficult. We shall not consider this particular method any further here and observe that it is a limiting condition of the more structured piecewise-linear method we consider next. However, a hand-drawn sketch of a desired waveshape could be used to assist a PWL specification. Piecewise-linear (PWL) specification partitions the definition of a waveform function into a contiguous set of linear segments with each segment describing the instantaneous amplitude as a function of phase over a sub-interval of one cycle. The complete waveform is specified as a list of arbitrary phase–amplitude coordinates, or ‘waypoints’, which are connected (or interpolated) by linear segments to define the waveform function which we denote w(ϕ), where ϕ 2 [0, 2π). This enables the shape of complex waveform functions to be easily approximated using relatively few data. We discuss this method further in Chapter 5 when we investigate methods for specifying an arbitrary waveform. Finally, we outline a method for specifying a waveform function that is based upon a ‘real’ continuous-time signal captured on a DSO. This signal could represent a specific

4

5

In principle, it is permissible to have an integral number of cycles in the wavetable, but here we are only concerned with single-cycle wavetables. In this context we define contiguous as free from a step amplitude discontinuity.


63

response from a test or diagnostic measurement, and is used to generate further stimulus or emulated transducer signals. The captured waveform data record is a vector of discrete-time samples that generally requires truncation to ensure a single cycle is available for resampling to fill a specific radix-2 length wavetable. Depending on the relative lengths of the single-cycle DSO capture record and the wavetable length, the tabulation process will require careful interpolated or decimated resampling of the DSO capture record. Additionally, the DSO timebase should be set so that the capture and DDS AWG sample rates are as close as possible, if not identical. Using a so-called ‘deep memory’ DSO will generally make this condition easier to achieve. If the DSO and DDS AWG sample rates are identical, a unit phase-increment in the DDS AWG will regenerate the original waveform captured by the DSO exactly.6

2.3.4

Frequency domain arbitrary waveform specification If the spectrum of an arbitrary waveform must be precisely defined, a time domain or waveshape specification is not always appropriate due to the weak and non-intuitive correlation between waveshape and spectrum. This is particularly true if the phase of the waveform harmonics is important. Two identical harmonic spectra, but with different harmonic phase offsets, generally produce very different waveshapes. We may define a single-cycle, multi-harmonic wavetable vector according to a harmonic spectrum specification using the inverse discrete Fourier transform (IDFT). The IDFT provides a direct transformation between the frequency and time domains and computes a wavetable sample vector directly from a harmonic amplitude and phase spectrum specification. The IDFT may be expressed in a non-complex form that allows the length L wavetable sample values W[a] to be defined as a function of the wavetable address a 2 [0, L 1], the highest harmonic number Nh 2 [1, L/2 1] and the kth harmonic amplitude and phase vectors that we denote by Ak 2 [0, 1] and θk 2 [0, 2π), respectively. We then have: W½a ¼

a Ak cos 2πk þ θk , L k¼0

Nh X

ð2:14Þ

where k 2 [0, Nh]. We observe that A0 is the waveform zero-frequency or DC term when θ0 ¼ 0. We consider this expression and its application further in Chapter 5. By choosing appropriate amplitude and phase values for each harmonic, in principle any band-limited periodic function can be tabulated. The number of samples per cycle in the fundamental is simply L, therefore a particular harmonic number h will have L/h samples per cycle. The highest harmonic number in the series Nh is therefore bound on the interval Nh 2 [1, L/2 1] to satisfy the Nyquist sampling criterion which requires at least two samples per cycle. The length of the wavetable therefore determines the highest harmonic number that can be tabulated. 6

Assuming no significant errors occur in resampling of the DSO capture record and the DDS AWG DAC and analogue post-processing stages.

64


φ (n) = φ (n − 1) + ϕ

fs = 1 T

ϕ

2M

M −1 z-1

∑

M

M a

Wavetable

W[a ]

ϕ ⎛ ⎞ y (n) = cos⎜ 2π M nT ⎟ ⎝ 2 ⎠

a ⎞ ⎛ W[ a ] = cos⎜ 2π M ⎟ 2 ⎠ ⎝

Figure 2.6 The ideal DDS implementation – an M-bit phase accumulator addresses a 2M location

wavetable.7

2.4

The foundations of direct digital synthesis (DDS) In this section we introduce the fundamental principles of direct digital synthesis (DDS) ahead of more extensive development in later chapters. We begin by investigating phase accumulation frequency synthesis and proceed to phase–amplitude mapping based on a wavetable which generates the output waveform sequence. However, our idealised approach, while providing optimal phase–amplitude mapping, introduces a fundamental implementation restriction – impracticable wavetable length. After summarising the key properties of an idealised DDS, we introduce the important concept of fractional addressing as a method for significantly reducing wavetable size from its optimal value while maintaining arbitrarily fine frequency control resolution. Fractional addressing enables an important design trade-off between waveform precision and computational burden. These concepts are the basis of DDS AWG.

2.4.1

Phase accumulation frequency synthesis In a typical hardware or software realisation, we eliminate the need for the complex floating point modulo 2π accumulation implied in Section 2.1.2 by using unsigned M-bit binary integers to represent ϕ(n) and φ. Modulo 2π operation is now effected by discarding the carry bit in a binary accumulation of the integer-valued phase increment φ using an M-bit adder and as depicted in Figure 2.6. The is clocked at the sample frequency fs and so the accumulation of φ proceeds modulo 2M as the accumulator overflows. The (M 1) -bit phase increment is bounded on the interval φ 2 [0, 2M1 1] to prevent aliasing when f =fs > 12, and has an equivalent radian value given by 2π(φ/2M ). We observe that phase accumulation using signed 2’s complement integer (or fixedpoint fractional) arithmetic produces phase sequences with positive or negative slope depending on the sign of the phase increment. Phase sequences with negative slope underflow to positive full-scale, exactly satisfying the mathematical requirements 7

For the sake of clarity we ignore for now that a wavetable stores quantised sample values which are defined according to the number of amplitude magnitude bits in the wavetable sample locations.

2.4 The foundations of direct digital synthesis (DDS)

65

of a negative frequency. Unless stated otherwise, we henceforth assume that the φ and ϕ(n) denotations relate to unsigned binary integer or fractional numbers with a defined number of bits and fraction point position. We now define ϕ(n) by the modulo 2M accumulation of a constant phase increment parameter φ with phase offset ϕ(0) ¼ 2M (θ/2π), thus: ϕðnÞ ¼

n DX

φ þ ϕð0Þ

i¼1

E 2M

:

ð2:15Þ

Equation (2.15) may be expressed as a modulo 2M difference equation that suggests a hardware or software implementation using a binary adder and unit delay: ϕðnÞ ¼ hϕðn 1Þ þ φi2M :

ð2:16Þ

For the specific case of constant frequency and therefore constant φ, Eq. (2.15) illustrates a multiplicative interpretation of the accumulation process that is important when we investigate phase domain processing in Chapter 7. For an M-bit unsigned binary accumulator there are 2M possible phase states which we denote by the set Φ ¼ {0, 1, 2, . . . (2M 1)} and so ϕ(n) 2 Φ for all n. The frequency of the phase sequence is given by Eq. (2.10), where the upper limit on the range of φ is imposed by the Nyquist sampling theorem to ensure f < fs / 2. Values of φ in the range φ 2 [2M1, 2M 1] produce an aliased output frequency equal to fs f. For non radix-2 phase increments, the phase accumulator output sequence comprises a cyclically repeating set of sawtooth sequences whose average period is always exactly 2M/φ samples. The number of sawtooth sequences and the number of samples over which they repeat are a function of M and ϕ. In Chapter 4 we consider this behaviour in greater detail, but for now illustrate it with a simple example. Figure 2.7 shows an example constant frequency phase sequence defined by ϕ(n) ¼ 〈7n〉32. We observe that the ‘minor’ sawtooth phase sequences comprise a different set of values on successive cycles, with a ‘major sequence’ of 7 cycles repeating every 32 samples. This is typical behaviour of a modulo phase accumulated sequence and is mathematically consistent with the instantaneous phase of a discrete-time sinusoid whose frequency is not an integer multiple of the sample frequency. The average period of the 7 minor sawtooth sequences computed over the repetition period (i.e. 32 samples in this example) is illustrated in Table 2.1 and is always in exact agreement with Eq. (2.10). In general, the frequency of the phase sequence is a minimum when φ ¼ 1. Under this condition all phase states are output contiguously and take exactly 2M sample clocks to complete a cycle. This sets a lower bound on the output frequency and therefore defines the frequency control resolution fr, thus: fr ¼

df fs , ¼ M dφ 2

ð2:17Þ

so that fr is determined by only two parameters – the phase accumulator word size M and the sample frequency fs. The upper bound on the value of M (and therefore the


Table 2.1 Illustrating the exact average period of the sawtooth phase sequence ϕ(n) ¼ 〈7n〉32. ϕ(n) sequence

Period

ϕ(n) sequence

Period

{0, 7, 14, 21, 28} {3, 10, 17, 24, 31} {6, 13, 20, 27} {2, 9, 16, 23, 30}

5 5 4 5

{5, 12, 19, 26} {1, 8, 15, 22, 29} {4, 11, 18, 25}

4 5 4

Average period ¼

ð5 þ 5 þ 4 þ 5 þ 4 þ 5 þ 4Þ 32 2M ¼ φ 7 7

32

32

64

24 16

Phase accumulator output

66

8 0 0

24

48

72

96

0

8

16

24

32

32 24 16 8 0

Sample index Figure 2.7 A constant frequency phase sequence with M ¼ 5 and φ ¼ 7. Observe that different

phase values are output on successive cycles over a period of 32 samples.

frequency control resolution) is constrained by carry propagation time in a physical realisation of the accumulator adder and may (at least in principle) be set at any desired value to achieve a specific frequency control resolution consistent with available hardware speed.


2.4.2

67

Phase–amplitude mapping To synthesise a specific waveform we must convert the modulo 2M phase sequence ϕ(n) into a waveform amplitude sequence. A simple and computationally efficient way to accomplish this is with a wavetable of length L ¼ 2M samples. The wavetable tabulates the required waveform (e.g. a sine wave) over exactly one cycle at discrete phase points separated by 2π/2M radians. The wavetable address (or index) interval a 2 [0, 2M 1] then corresponds to the phase interval [0, 2π). Tabulating 2M waveform amplitude samples (i.e. corresponding to all possible phase accumulator output states) ensures that every possible phase accumulator output value is mapped to a unique amplitude value which we define as the optimal phase–amplitude mapping condition. A 2M location sinusoidal wavetable as defined by Eqs. (2.12) or (2.13) converts the accumulator phase sequence to a sinusoidal amplitude sequence y(n) given by: φ ð2:18Þ yðnÞ ¼ cos 2π M nT : 2 We observe that Eq. (2.18) is in exact agreement with the definition of a discrete-time sinusoid given by Eq. (2.3) with fd ¼ φ/2M and represents optimal phase–amplitude mapping. If we rearrange Eq. (2.6) and observe the direct correspondence between the phase interval [0, 2π) and the index interval [0, 2M), we may express the output frequency f of y(n) as a function of the control parameter φ and the design parameters M and fs, thus: 1 ϕðnÞ ϕðn 1Þ φf ð2:19Þ f ¼ ¼ Ms , 2π T 2 where φ 2 [1, 2M1 1]. Equation (2.8) is fundamental to phase accumulating sinusoidal and arbitrary waveform generation (i.e. DDS AWG) and indicates three fundamental properties of the technique: waveform frequency f is directly proportional to the phase increment φ; frequency resolution is exactly fs/2M and therefore constant; optimal phase–amplitude mapping is possible only with a wavetable of length 2M samples. Frequency control in phase accumulation frequency synthesis is therefore inherently linear and frequency control resolution is constant (assuming the sample frequency is also constant). However, we observe an important design limitation where the wavetable length is observed to increase exponentially with M whereas frequency control resolution reduces as the inverse exponential of M. Very high frequency control resolution (a usually desirable property) therefore leads to impractically long lookup table lengths. In Section 2.2 we introduced a novel concept in digital waveform generation – sampling a tabulated waveform function to generate a periodic signal at a specific frequency. In this section we have formalised and extended this approach into two

68


distinct operations – computing a modulo (i.e. wrapped) phase sequence whose slope is controlled by a phase increment parameter and sets the output frequency, and mapping this phase sequence to a corresponding amplitude sequence using a lookup table or wavetable which tabulates a waveform function. These two operations are the foundations of DDS sinusoidal and arbitrary waveform generation.

2.4.3

Phase continuity Phase accumulating frequency synthesis provides inherently phase-continuous step frequency transitions in the output waveform and is an important property which we now investigate. A phase-continuous step frequency transition is defined as one where the instantaneous phase of the waveform shows only a change in slope (with no step discontinuity) that is coincident with the step change in frequency or phase increment. Before considering a phase-continuous frequency change in ϕ(n), we consider the effect of a step change in the frequency parameter of a discrete-time sinusoid at an arbitrary sample index point m. We begin by defining a unit-amplitude discrete-time sinusoid with zero phase offset by y(n) ¼ cos(2πf (n)nT ), whose frequency is determined by the timevarying parameter f(n). We now define a step change in f (n) at sample index m, thus: f n<m f ðnÞ ¼ : ð2:20Þ f0 n m It is apparent that a step change in f (n) at n ¼ m as described by Eq. (2.20) produces a corresponding step change in the instantaneous phase argument of the cosine function ϕ(n) ¼ 2πf (n)nT. This causes a discontinuity in the amplitude sequence y(n) as depicted in Figure 2.8a with the corresponding phase ∠y(n) shown in Figure 2.8b, where the step discontinuity is clearly evident. The magnitude of the step phase discontinuity is 2πT (mf 0 (m 1) f ) radians and independent of n (i.e. constant). A phase-continuous frequency change in y(n) at sample index m requires that we compute the instantaneous phase function ϕ(n) by integrating f (n) over n samples assuming n m according to Eq. (2.7). Since this is a discrete-time system the integration can be represented by a two-stage summation around m given by: ! m n X X 0 ϕðnÞjnm ¼ 2πT ¼ 2πT ðnf 0 mð f 0 f ÞÞ: f þ f ð2:21Þ 1

mþ1

with ϕ(0) ¼ 0. In general, we have: 2πT nf n<m : ϕðnÞ ¼ 2πT ðnf 0 nð f 0 f ÞÞ n m

ð2:22Þ

Equation (2.22) describes a phase-continuous frequency change in ϕ(n) according to a step change in frequency at sample index m. This expression effectively subtracts a fixed phase offset from the instantaneous phase ϕ(n) ¼ 2πTnf 0 for n m equal to the magnitude of the otherwise phase discontinuous step change 2πT[mf 0 (m 1) f ] less the phase increment at the original frequency 2πfT for n < m. Equation (2.22) therefore


69

1

(a)

y(n)

0.5 0 − 0.5 −1

25 0

10

20

30

40

50

30

40

50

30

40

50

30

40

50

25

∠y (n)

20

(b)

15 10 5 25 0 0

10

20

10

20

1

(c)

y(n)

0.5 0 − 0.5 −1

25 0

20

(d)

∠y (n)

15 10 5

25 0

0

10

20

80

φ (n)

60

(e)

40 20 50

0 20

40

60

80

60

80

1

y(n)

0.5

(f)

0 − 0.5 −1 20

50 40

Sample index n Figure 2.8 (a) A discrete-time sinusoid with a phase discontinuous frequency change at sample

index n ¼ 25; (b) The corresponding unwrapped phase sequence; (c) A discrete-time sinusoid with a phase-continuous frequency change at sample index n ¼ 25; (d) The corresponding unwrapped phase sequence; (e) A typical phase accumulator output sequence with M ¼ 6, φ ¼ 2, φ0 ¼ 4 and m ¼ 50; (f) The corresponding sinusoidal sequence.

70


defines a generalised phase sequence ϕ(n) with only an instantaneous change in the slope at the frequency transition point with no step discontinuity, thereby producing a phase-continuous change in y(n) as illustrated in Figures 2.8c and 2.8d. Finally, we consider a step change in the phase increment parameter at sample index m, as defined by: φ n<m φðnÞ ¼ : ð2:23Þ φ0 n m The phase increment integration is represented by a two-stage modulo bounded summation around m to give the wrapped phase accumulator output sequence for n m, thus: ϕðnÞjnm ¼

m DX 1

φþ

n E X φ0 mþ1

2M

¼ hnφ0 mðφ0 φÞi2M ,

with ϕ(0) ¼ 0. In general we deduce that: hnφi2M ϕðnÞ ¼ hnφ0 mðφ0 φÞi2M

n<m : nm

ð2:24Þ

ð2:25Þ

It is evident from Eq. (2.25) that the phase accumulator produces inherently phasecontinuous output sequences following a step change in the phase increment φ at any sample index. Figure 2.8e illustrates an example phase-continuous output sequence from a phase accumulator with a step change in phase increment at sample index m ¼ 50. The corresponding phase-continuous sinusoidal signal is shown in Figure 2.8f.

2.4.4

Phase–amplitude mapping and fractional addressing In Section 2.4.2 we stated that optimal (i.e. error-free) phase–amplitude mapping is only possible when the lookup table length L ¼ 2M and every phase state of the phase accumulator output is mapped to a unique amplitude value. However, this generally leads to impractically large lookup table lengths for typical levels of required frequency control resolution. We can reduce the required lookup table length below the optimal value of 2M by employing a phase–amplitude mapping technique known as fractional addressing. The concept of fractionally addressing a tabulated waveform function was introduced and developed by Max Mathews in his pioneering work at Bell Telephone Laboratories during the 1950s and 1960s developing software-based music synthesis oscillators [4]. Phase–amplitude mapping based on fractional addressing assumes that the desired waveform function is tabulated in a lookup table at integer-spaced phase points. The essence of fractional addressing is to estimate, to a specified accuracy, waveform amplitude values at a fractional wavetable index between the tabulated values. The process of estimating a fractionally addressed value necessarily involves a process known as interpolation. In this section we introduce and outline the basis of fractional addressing, developing it further in Chapters 4 and 5. Firstly, we set the lookup table length to an appropriate


71

M-bit phase accumulator output φ (n) I-bits

F-bits

Wavetable address φ I ( n ) 2 I −1 2 I − 2

1

Fractional phase φ F (n) 2−1

2 − F +1 2 − F LSB

MSB

Fractional phase increment ϕ ∈ [0, 2 I − 1] Δϕ = 2 − F 2 I −1 2 I − 2

1

2−1

2 − F +1 2 − F

Integer phase increment ϕ ∈ [0, 2 M − 1] Δϕ = 1 2M −1 2 M − 2

21

20

Fractional and integer phase increment representations Figure 2.9 Partitioning the phase accumulator output into integer and fraction fields.

radix-2 value with L << 2M , L ¼ 2I and I 2 N. The M-bit phase accumulator output ϕ(n) is now partitioned into integer and fraction fields comprising the I most-significant and F least-significant bits, respectively. Figure 2.9 illustrates this partitioning. We now interpret ϕ(n) as an M-bit fixed-point phase sequence comprising I integer bits, which we denote ϕI(n) and F fraction bits which we denote ϕF(n). This representation allows ϕ(n) to be interpreted as a fractional valued quantity where the integer part ϕI(n) indexes a lookup table tabulating L ¼ 2I samples modulo L, and the fractional part ϕF(n) represents the fractional phase between adjacent integer phase points. Figure 2.10 illustrates the concept of fractional addressing by representing the sequence of possible phase accumulator output states and tabulated waveform samples as a circular depiction with M ¼ 6 and I ¼ 4. This representation is often referred to as the ‘phase wheel’, with increasing phase proceeding anti-clockwise around the wheel. Lookup table indexing therefore proceeds as a continuous anti-clockwise path around the circle according to a particular phase increment φ. In this illustration we set φ ¼ 6 and observe that successive trips around the circle produce different lookup table index values until the cycle repeats after three trips. Depending on the value of φ, some fractional phase values will exactly index the tabulated samples (i.e. take on exactly integer phase values) and others will point to a phase point between tabulated samples (i.e. take on fractional phase values) and therefore require interpolation to estimate the true waveform amplitude value at that phase point.

72


2 I tabulated samples M

2 phase accumulator states

(3) (4)

(2)

Fractional addresses (1) =6

(5) (0)

(6)

3 2 1 0 2 M −1 2M −2

(10)

(9)

(7 ) (8)

Key: Phase accumulator states Tabulated samples Non-fractional wavetable read Fractional wavetable read Figure 2.10 Circular representation of modulo phase accumulation and fractional addressing with M ¼ 6 and I ¼ 4 (i.e. 64 phase accumulator states and 16 tabulated samples).

The simplest (and most erroneous) fractional addressing implementation discards the fractional phase information and is widely known as phase truncation – strictly this is not fractional addressing, but direct wavetable lookup. A similar method uses the fractional phase information to round the phase up or down to the nearest integer value and is known as phase rounding. With either method, all fractional phase values are mapped directly to a tabulated amplitude value that corresponds to an integer phase point less than the fractional value (i.e. phase truncation) or to a phase point nearest the fractional value (i.e. phase rounding). This causes waveform shape errors that are manifest as spurious signals with complex amplitude and frequency distributions in the waveform spectrum that are a function of the tabulated waveform function, φ, I and M. In the limit as I ! M these errors correspondingly tend to zero. We generalise these errors as phase truncation noise that we measure as a signal-to-noise ratio or error spectrum and define in Section 2.6. For a given value of I (and hence wavetable length L), phase truncation represents a lower bound on phase–amplitude mapping accuracy.


73

We can reduce phase–amplitude mapping errors due to phase truncation by using the fractional phase information to interpolate the tabulated waveform using an interpolation algorithm that estimates the non-tabulated value at the fractional lookup table address. Interpolation uses the tabulated values surrounding the fractional address to construct a polynomial function which es through the tabulated values and so locally approximates the underlying waveform function. The number of points used sets the polynomial order, with first-order8 or linear interpolation using the two points surrounding the fractional address, proceeding to higher orders and ultimately truncated sinc function interpolation. Generally speaking, more interpolation points produces a more accurate approximation of the fractionally addressed wavetable value at the expense of an increased number of wavetable memory accesses and more complex arithmetic computations. We develop interpolated phase–amplitude mapping further in Chapters 4 and 5. Finally, we observe that with fractional addressing, the phase increment parameter can be interpreted as a fixed-point fractional value or an integer value. Either interpretation is equally valid since they both specify the same information – output waveform frequency. A fractional interpretation with φ 2 [0, 2I 1], φ2 R and resolution 2F, specifies output frequency as a fractional multiple (or sub-multiple) of a base frequency equal to fs/2I with frequency control resolution fs/2M. An integer interpretation with φ 2 [0, 2M 1] and φ 2 N specifies output frequency as an integer multiple of the lowest possible frequency fs/2M (i.e. the frequency control resolution).

2.4.5

The aliasing problem We conclude this section by introducing a fundamental error mechanism in wavetable based phase–amplitude mapping that is distinct from interpolation error. We discuss methods for reducing or eliminating this error in Chapters 5 and 7. Let us assume our length L lookup table tabulates a periodic waveform function that has a harmonic spectrum whose fundamental exactly fills the table (i.e. L samples per cycle). The bandwidth of the tabulated waveform is therefore defined by the highest harmonic number Nh in the spectrum whose amplitude is significantly above some lower bound (e.g. the quantisation noise). Regenerating this waveform at a frequency f therefore increases the highest significant frequency to Nh f and requires a Nyquist bandwidth > Nh f to ensure that the higher harmonics are not aliased. If Nh f > fs/2, aliasing of the higher harmonics will occur as illustrated in Figure 2.11. As Nh f exceeds fs/2, progressively more harmonics are aliased to non-harmonic multiples of f causing waveform distortion and increasing levels of error spurious signals in the waveform spectrum. For a given Nyquist frequency (and hence sample frequency) this problem can only be alleviated by band-limiting the tabulated waveform function prior to indexing. We investigate this further in Chapters 5, 6 and 7. 8

Zero-order interpolation is equivalent to phase truncation where the fractional phase is simply discarded or used to round the truncated phase value.


Amplitude

74

Tabulated waveform spectrum

1

Nh

Harmonic Regenerated waveform spectrum at frequency f

Amplitude

First alias spectrum

f

Nh f

fs

fs-Nh f

fs-f

fs

2

fs-Nh f

Aliased harmonics

Nh f >

fs 2

fs 2

fs Frequency

Figure 2.11 Harmonic aliasing when indexing a wavetable tabulating an arbitrary waveform with multi-harmonic spectrum.

2.5

Control parameters and their characteristics In this section we discuss four fundamental signal generation control parameters and their ideal properties, which include:

frequency; phase offset; amplitude; signal waveshape or spectrum.9

In addition to these fundamental parameters, we introduce the idea of a metaparameter to simplify complex ‘application-specific’ parametric control. We define a metaparameter as a single control parameter that in combination with a predefined ‘one-many’ mapping function indirectly controls many separate parameters. For example, consider a polyphase signal comprising multiple phase-locked sine or arbitrary waveforms with identical frequency that require control of relative phase offset. This might be accomplished with many individual control parameters or a single metaparameter 9

It is evident that control of signal waveshape may be effected by time or frequency domain methods depending on whether waveform shape or spectrum accuracy is important in the context of the application.

2.5 Control parameters and their characteristics

75

which controls the individual phase offsets according to a predefined rule. Another example is a metaparameter that controls the total harmonic distortion (THD) of a sine wave signal by varying the relative amplitudes of multiple harmonics according to some rule. We assume for now that we have a waveform generation technique that provides real-time control of its constituent harmonic parameters. By definition, THD is a function of the amplitude spectrum of many distortion harmonics and so the question arises as to which harmonics are used and in what proportion they are added to the fundamental sine wave as the THD metaparameter varies. This difficulty is managed by appropriate definition of the THD metaparameter mapping function,10 thereby enabling application-specific THD control of the generated sinusoid. We consider metaparameters further in Chapter 7 when we investigate real-time computation of the IDFT combined with DDS frequency synthesis.

2.5.1

Desirable control characteristics We observe that digital control of any waveform parameter (e.g. frequency) is characterised by several fundamental properties which are independent of the parameter being controlled. These include:

dynamic range; resolution; linearity; latency and switching time; orthogonality.

The dynamic range of a digital control parameter is defined as the ratio between the maximum and minimum values of that parameter. The expression of this ratio depends on the parameter being controlled. Frequency control dynamic range is usually expressed as a linear ratio (e.g. 223–1 : 1) or an equivalent number of bits (e.g. 23). Amplitude control dynamic range is usually expressed logarithmically in dB relative to full-scale and a minimum amplitude or the system noise floor. Since a digital control parameter is quantised in magnitude according to the number of bits used to represent it, the corresponding output parameter can only be controlled in discrete steps. The control resolution or step size is defined as the difference in output parameter per unit change in the corresponding control parameter, or equivalently, the size of the smallest parameter change. Control resolution is ideally constant and set according to a design parameter (e.g. the phase accumulator word size in bits), but in some systems it varies with the absolute value of the control parameter. Most recursive oscillators have a nonlinear relationship between oscillation frequency and the corresponding control coefficients, which leads to a varying frequency control resolution (or step size) across the dynamic range.

10

By way of a simple example, a function that specifies the amplitude of each harmonic in the THD spectrum as a weighted proportion of the metaparameter.

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Control linearity is concerned with the relative changes between a control parameter and the corresponding output parameter. Let us consider an output parameter y (e.g. frequency) that is a function F of a control parameter x. Now consider two different control parameter values x1 and x2, that produce corresponding outputs y1 ¼ F(x1) and y2 ¼ F(x2). Our system is linear if and only if y1 þ y2 ¼ F(x1 þ x2). If this relationship is not satisfied we describe the system as non-linear. A digital system which has a nonlinear control relationship between input and output parameters always has a variable control resolution or step size. Control latency occurs in all digital waveform generation systems and is defined as the time delay between a change in the value of a control parameter and the corresponding change being observed in the output signal. In pipelined digital systems latency is nearly always an integer number of clock cycles and therefore predictable and repeatable. Switching time is defined as the time taken to transition from one state to another within a specified tolerance after the latency period. It is usually only applicable to analogue and hybrid PLL systems which typically exhibit a non-instantaneous slew and overshoot from one frequency to another following a step-change in PLL input frequency or division ratio. In general, DDS and recursive waveform generation systems do not exhibit such ‘analogue-like’ loop stabilisation behaviour and generally exhibit well-behaved parameter transitions synchronous with the system clock. We define ‘well-behaved’ as the absence of overshoot or discontinuity in the parameter being changed and transient anomalies in the output waveform. Switching time is pertinent to digital waveform generation systems that have servo-stabilised or levelled output amplitude control mechanisms. The stabilisation loop is typically second-order and can therefore exhibit a slew change and overshoot in output amplitude following a step-change in ‘demanded’ amplitude control. The behaviour of the output waveform following a gradual or step-change in a particular control parameter defines a fundamental requirement of all digital waveform generation systems – that control parameters should be independent of each other or orthogonal. Control parameter orthogonality (i.e. non-interdependency) describes the ideal condition where a change in one parameter produces no corresponding change in any other parameter. If this condition is satisfied across all control parameters we can say formally that they are mutually orthogonal within an abstract ‘parametric control space’. For example, a step-change in the frequency control parameter should only produce a corresponding well-behaved phase-continuous step-change in output frequency – with amplitude and waveshape remaining invariant. We now discuss several fundamental waveform generation control parameters: frequency, phase offset, amplitude, waveshape and spectrum.

2.5.2

Frequency control Frequency is defined as the number of waveform cycles that occur in each second. The units of frequency are hertz (Hz), where 1 Hz is equivalent to one cycle per second. In phase accumulating frequency synthesis as used in DDS, the output frequency fout is an


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exact fraction of a precisely defined reference frequency which is typically the system sample rate fs. The set of possible output frequencies comprises integer multiples of a fixed fraction of the reference frequency (or sample rate) given by φ/2M. The output frequency is controlled by an M-bit unsigned integer representation of φ and given by fout ¼ φfs/2M; where φ is the phase increment or frequency control word, and M is the bit width of the phase accumulator. Since frequency control resolution fr is defined as the change in output frequency per unit change in the frequency control word φ we have fr ¼ fs/2M. We observe that fr is constant and therefore indicates a linear relationship between the frequency control word and output frequency. In digital (i.e. sampled) waveform generation systems the maximum frequency is fundamentally limited by an upper bound equal to half the sampling frequency fs/2 and known as the Nyquist frequency. The frequency control dynamic range is therefore defined by the interval φ 2 [1, 2M 1 1] and so fout 2 [ fs/2M, ( fs/2 fs/2M)]. However, in a real-world implementation the maximum output frequency is often deliberately constrained to be less than the Nyquist frequency (e.g. 0.4fs) to help reduce or eliminate aliasing errors. Aliasing manifests as unwanted spurious signals in the output amplitude spectrum and is caused by broadly two mechanisms: the finite roll-off slope of the postDAC reconstruction filter and undersampling in lookup table based phase–amplitude mapping. In Chapter 3 we will see that all recursive oscillators have output frequency given by an expression of the form fout ¼ f (k)fs/2π, where f(k) is an inverse sine or cosine function of a frequency control coefficient k. This expression is similar to that of a DDS waveform generator where f (k) is analogous to the phase increment parameter. The simplest recursive oscillator, the so-called direct-form or biquad, has f (k) ¼ 2 cos1(k/2), with k a fractional signed quantity (e.g. a fixed-point 2’s complement number). Assuming the binary representation of k is uniformly quantised it is evident that most recursive oscillators exhibit a variable frequency control resolution over frequency (i.e. a variable ‘hertz per unit change’ in the frequency control coefficient). Accordingly, they have a non-linear frequency control response. Some recursive oscillators have a small step size at low frequencies and a large step size at high frequencies, while others exhibit the opposite behaviour. In all recursive oscillators that exhibit nonlinear frequency control, the transfer function shape is defined by a sine or cosine function. In a non-pipelined DDS implementation, frequency control latency is one sample clock period due to the phase accumulator . In high speed DDS systems control latency is increased due to pipeline delays in the accumulator adder and phase– amplitude mapping stages. A control latency of many tens of clock cycles is not uncommon in highly pipelined systems that inherently trade processing throughput with latency. We discuss pipelined processing and the trade-off between processing throughput and latency in Chapter 8. The behaviour of a digital waveform generator following a step change in the frequency control word usually refers to the corresponding behaviour in an important output parameter such as phase, amplitude or waveshape. DDS-based waveform generators exhibit intrinsically phase-continuous step frequency changes (ignoring pipeline delays)

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with waveshape and waveform amplitude invariant. Conversely, some recursive oscillators exhibit a phase discontinuous frequency transition and a step change in amplitude following a change in their frequency control parameter.

2.5.3

Phase offset control Phase offset is defined as the time difference between a fixed reference point on a waveform cycle (e.g. the start or 0 point) and an arbitrary time reference point; usually expressed in degrees or radians as a fraction of one waveform cycle. The time reference can be a secondary output waveform (as in polyphase waveform generators) or a synchronisation pulse (or edge) that is arranged to occur at the start of every waveform cycle. Phase offset describes the relative phase between two or more phase-locked waveforms with precisely the same frequency. The phase offset between two waveforms of different frequency is continuously varying with the time rate of change equivalent to the instantaneous difference frequency. The units of phase offset are degrees ( ) or radians, where 360 is equivalent to 2π radians and corresponds to one complete waveform cycle. The phase offset of a DDS waveform generator is controlled by a signed or unsigned digital word. The number of magnitude bits in this word determines the resolution with which the phase offset can be controlled. The control dynamic range is the difference between the maximum and minimum programmable phase offsets. The control resolution is defined as the phase difference per unit change in the phase offset control word relative to a fixed time reference point. Phase offset control in DDS waveform generation is effected by adding a numerical offset to the phase accumulator output before the phase–amplitude mapping stage. The dynamic range is therefore always 0 to 2π radians. Control resolution is a function of the phase–amplitude mapping resolution (e.g. wavetable length) with an upper bound set by the number of bits in the phase accumulator. If we assume the phase–amplitude mapping stage accepts the most significant I-bits of the phase accumulator output and is non-interpolated, the phase offset control resolution is 2π/2I radians. Accordingly, DDS waveform generation has a fixed ‘degrees (or radians) per unit change’ in the phase offset control word and so DDS phase offset control is inherently linear. As with frequency control, DDS phase offset control latency is a function of the pipeline depth used in the phase offset adder and phase–amplitude mapping stages. Under a step change in phase offset, DDS waveform generators do not exhibit frequency11 or amplitude errors and only produce amplitude discontinuities that are mathematically consistent with a step transition to a new part of the waveform cycle corresponding to the step phase offset. Recursive oscillators do not have a direct mechanism to control phase offset. Instead, the oscillator must be re-initialised with new initial condition values that preserve oscillation amplitude and set the new start phase according to the required phase offset. 11

As we have seen in Section 2.1.2, the time derivative of phase corresponds to frequency. Therefore, a timevarying DDS phase offset causes a corresponding variation in output frequency that is not an error phenomenon, but just a property of dynamic phase control.


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As we will see in Chapter 3, recursive oscillators generally require periodic reinitialisation to mitigate progressive amplitude errors or ‘arithmetic noise’ due to recursive processing with quantised arithmetic.

2.5.4

Amplitude control The amplitude of a waveform is usually measured in RMS or peak to peak volts, often with a specified load resistance. It is also possible to define waveform amplitude (particularly for sine waves) in of the power delivered to a specified load resistance. In professional test equipment and audio applications, load (or ‘termination’) resistances are typically 50 Ω and 600 Ω, respectively. Logarithmically scaled amplitude measures relative to a specific RMS voltage (or power) are also common. For example, the dBV measures RMS amplitude relative to 1 V RMS with AdBV ¼ 20log (ARMS). For example, 0 dBV corresponds to an amplitude of 1 V RMS and 60 dBV corresponds to an amplitude of 1 mV RMS. Similarly, the dBm measures the power delivered into a 50 Ω load relative to 1 mW with 0 dBm corresponding to 1 mW. Digital amplitude control is accomplished by multiplying the waveform samples by an amplitude control parameter either in the digital or analogue domain. If we assume that the waveform samples and the amplitude control parameter are represented by a binary word with b bits including 1 sign bit (e.g. a fractional 2’s complement representation), the amplitude control dynamic range is 2b 1 or 20 log(2b 1) 6.02b dB. The magnitude of the change in amplitude as a fraction of full-scale for a 1-bit change in the control word is (2b 1)1, 2b assuming 2b >> 1. The amplitude control resolution expressed as a scaling factor for a 1-bit change in the amplitude control word is therefore 1 2b or 20 log(1 2b) dB assuming 2b >> 1. In a real-world hardware implementation (particularly with test instrumentation waveform generators), output amplitude control is a two-stage process. The first stage comprises continuous amplitude control according to a multiplicative control parameter as just described, with the second stage applying discrete attenuation values in the analogue domain. This method provides a very wide amplitude control dynamic range beyond that achievable by digital (or analogue) multiplication alone. Amplitude control is linear since digital multiplication by a scaling factor is an inherently linear mathematical operation. Amplitude control latency is a function of the pipelining level in the amplitude multiplier and corresponding control path. For DDS waveform generation, a step-change in the multiplicative amplitude parameter is well-behaved and produces (after any latency delay) a corresponding step-change in the instantaneous amplitude of the waveform. Aside from multiplicative scaling of the output, recursive oscillators can be re-initialised with new initial condition values that are calculated so as to maintain oscillation frequency and phase, but change amplitude to a new value.

2.5.5

Waveshape control We have already met the idea of real-time waveshape control in our discussion of the switched integration analogue function generator in Section 1.3.4. Here a single parameter (e.g. a variable resistance potential divider) controls the waveform duty-cycle in a

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well-behaved way. The dynamic control of waveshape in a digitally generated waveform is not usually associated with a single parameter that can vary with time. One reason lies in the difficulty of defining how variation of a single parameter maps to a corresponding variation of waveshape in a useful and arbitrarily definable way in real time. In Section 2.2 we introduced the concept of a wavetable as a lookup table that tabulates amplitude quantised samples of an integral number of periodic waveform cycles. The tabulated samples are determined from a wavetable function evaluated at equally spaced phase points that correspond to an integer wavetable phase index. Wavetables are the basis of phase–amplitude mapping in both sinusoidal and arbitrary waveform DDS that we develop further in Chapters 4 and 5. Two problems are immediately apparent when we think about arbitrary waveshape control – how to intuitively specify an arbitrary waveshape variation and how to implement that variation according to a single parameter in a well-behaved way. The nature of wavetable phase–amplitude mapping in DDS AWG suggests a novel method for tackling both of these problems. We describe this method as paged wavetable indexing, which underpins two advanced forms – paged wavetable interpolation and linear wavetable combination – that we investigate in Chapter 6. Paged wavetable indexing does not appear to have been exploited in commercial arbitrary waveform instrumentation, but has been extensively researched and reported in computer music literature [5]. In this domain it has been successfully utilised to provide real-time dynamic control of a synthesised sound’s tonal quality or timbre. Indeed, it is the foundation of a whole subclass of music synthesiser architectures. Paged wavetable indexing provides a novel and exact method for dynamically controlling waveshape in DDS AWG by selecting the synthesised waveshape from a precomputed group of wavetables according to a page address parameter. Paged wavetable interpolation is a refinement of this technique that interpolates a group of wavetables according to a fractional page address. ‘Virtual wavetables’ that lie between the tabulated ones are effectively computed in real time by interpolation. We can think of each wavetable in the group as containing a predefined waveform that specifies a waypoint in an abstract ‘waveshape space’ that we move through as the page indexing proceeds. In a real-time hardware or software implementation, the wavetables occupy a contiguous block of memory partitioned into consecutive radix-212 length pages with each page storing a unique wavetable. Linear wavetable combination sums multiple waveforms with dynamically adjustable amplitude and phase. In the limit, when the waveforms in the set have harmonically related frequencies, we have the real-time inverse discrete Fourier transform (IDFT). The qualitative control attributes of dynamic range, resolution, linearity, latency and orthogonality have limited or at best abstract relevance to waveshape control by such methods as paged wavetable indexing. Waveshape control dynamic range is difficult to define concisely as there is no simple numerical measure of waveshape. It may be

12

Radix-r denotes an integer equal to rk, where k is a positive integer.


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loosely represented by the beginning and end waveshape waypoints in the group of wavetables. For paged wavetable indexing, a reasonable definition of waveshape control resolution is the number of distinct waveshapes that can be generated. With linear wavetable interpolation, it may be defined as the total number of virtual wavetables interpolated between the tabulated ones and is bound only by the number of fraction bits in the wavetable page index. The concept of waveshape control linearity is clearly not pertinent to paged wavetable indexing or interpolation. We may define latency in the context of paged wavetable indexing or interpolation as the time delay between a change in the wavetable page index and that change being observed in the output waveform. Paged wavetable indexing or interpolation satisfies the control parameter orthogonality condition and any observed amplitude variation with wavetable page index is always mathematically consistent with a transition or interpolation between two different waveforms. Under certain conditions (e.g. a phase offset between the tabulated waveforms being interpolated), a step-change in the wavetable page index may produce an amplitude discontinuity that is consistent with a step change between two waveforms (with different waveshape) at a particular phase point in the waveform cycle.

2.5.6

Spectrum control Precise control of a waveform’s spectrum may be realised in essentially one of two ways: by means of a time-varying waveshape whose spectrum variation is well-defined (e.g. time domain wavetable synthesis); ‘synthesis from scratch’ according to a weighted harmonic series whose amplitude and phase offset values are dynamically controlled. The first method is identical to paged wavetable indexing or interpolation discussed earlier, except that we are now concerned with the spectrum of the waypoint wavetables rather than their waveshape. As we saw in Section 2.3.4, it is possible to define a wavetable function (and hence tabulate the waveform) according to a spectrum of harmonic amplitude and phase parameters. The second ‘brute force’ method provides comprehensive spectrum control by using the IDFT to synthesise a waveform in real time from a set of harmonic amplitude and phase parameters. This is an example of signal ‘synthesis from scratch’ and provides real-time spectrum control at the expense of significantly increased computation compared to paged wavetable indexing or interpolation. In of spectrum control, this method at first appears little different from the paged wavetable approach although much more costly in computational complexity. Indeed, with a large number of waypoint wavetables, paged wavetable interpolation synthesises waveforms with smoothly varying spectra according to the wavetable page index parameter. However, if the harmonic variation across the group of wavetables has to be changed all of the waypoint wavetables must first be recomputed. This is generally time consuming, particularly for a large number of long wavetables and therefore difficult to implement ‘on the fly’ in

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real time. The real-time IDFT allows spectrum changes to be observed immediately in the output waveform (discounting any processing latency). Another advantage of the IDFT approach is the prevention of ‘harmonic aliasing’. We recall from Section 2.4.5 that any harmonic of a tabulated waveform function which exceeds the Nyquist frequency (i.e. half the sample frequency) will alias into the Nyquist band where it represents an error signal which is generally not harmonically related to the waveform fundamental frequency. Since paged wavetable interpolation uses fixed waypoint wavetable spectra, care has to be taken to ensure that aliasing of the higher harmonics does not occur as the waveform (i.e. fundamental) frequency is increased. Real-time IDFT waveform synthesis allows independent control of all harmonic amplitudes, and so aliasing can be prevented by ensuring that the amplitude of any harmonic that would exceed the Nyquist frequency is set to zero. This, of course, requires additional processing to implement. We investigate the real-time IDFT approach further in Chapters 7 and 8. It is also possible to conceive of non-harmonic spectrum control based upon a linear combination of arbitrary frequency sinusoids, or indeed, more complex waveforms. The period of the composite quasi-aperiodic waveform is now the lowest common multiple of the individual component periods and therefore likely to be much longer than the longest period of the constituent frequency components. We consider this approach further in Chapter 6 when we investigate linear combination of multiple wavetables to implement dynamic spectrum control of both harmonic (as a precursor to efficient IDFT implementations) and so-called band- signals whose spectral components are usually defined relative to a carrier or centre frequency. As with waveshape control discussed earlier, the qualitative attributes of dynamic range, resolution, linearity, latency and orthogonality have limited relevance to spectrum control. Spectrum control dynamic range is simply the number of distinct spectra that can be generated and is arbitrarily large. For metaparameter spectrum control, the dynamic range is strongly influenced by the underlying mapping function. Spectrum control resolution is easier to define concisely, and for a harmonic spectrum involves two independent quantities: the maximum number of harmonics that make up the spectrum and the control resolution for each of the harmonic amplitude and phase parameters. The concept of spectrum control linearity based upon the definition given earlier has some relevance to metaparameterised spectrum control, but only if the spectral characteristics being controlled in the synthesized signal are well defined and quantifiable (e.g. total harmonic distortion (THD)). We define spectrum control latency as the time delay between a change in the spectrum control parameters (e.g. harmonic amplitude and phase values or a metaparameter) and that change being observed in the output waveform’s spectrum. Spectrum control based upon the IDFT (with metaparameterised control or otherwise) is orthogonal with respect to all other parameters. However, under certain conditions, a step-change in spectrum by whatever control means may produce an amplitude or phase discontinuity in the output waveform that is mathematically consistent with a step change between two spectra and their corresponding waveforms.

2.6 Performance metrics

2.6

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Performance metrics In this section we define some qualitative metrics that we use in later chapters to measure and compare the performance of digital waveform generation algorithms using analysis or computational simulation of a mathematical model. These metrics are also used to explore the effects of design parameter changes as part of the ‘performance– design trade-off’ process.

2.6.1

Phase truncation noise We define phase truncation noise as the magnitude of the amplitude error signal typically observed with interpolated phase–amplitude mapping algorithms. Interpolated phase–amplitude mapping implies distinct integer and fractional phase components where the integer part indexes the wavetable and the fraction part is used to interpolate the tabulated values to estimate the sample amplitude at a fractional address according to a specific interpolation function. In the simplest case, the fraction field is discarded (or used to round the integer field) and we have phase truncation or zero-order interpolation. The magnitude of the interpolation error signal is a strong function of the waveform function (i.e. harmonic complexity) and phase increment (i.e. waveform frequency), and is modelled as a generalised noise signal added to an otherwise ideal underlying signal. We now introduce the concept of signal to noise ratio (SNR), where the noise signal is the sum of several independent error mechanisms in the digital waveform generation process (e.g. quantisation, arithmetic round-off and phase truncation errors). Quantisation noise corresponding to the number of bits in the sample word and arithmetic processing round-off errors set a bound on SNR performance. In the context of this book, SNR provides a simple scalar metric for evaluating and comparing the performance of phase–amplitude mapping algorithms under specific design and operating conditions. To determine the noise magnitude we first define the amplitude error sequence εa (n), thus: εa ðnÞ ¼ yðnÞ yr ðnÞ,

ð2:26Þ

where y(n) denotes the test signal sequence computed using a particular phase– amplitude mapping algorithm (or indeed any waveform generation algorithm) and yr(n) denotes an error-free reference signal sequence of the same frequency, amplitude and phase, but computed to full arithmetic precision with no approximations. It is important to ensure that both the test and reference sequences are normalised in amplitude to prevent gain errors in generation of the test signal y(n) becoming manifest in the error sequence values. The waveshape error metric that we discuss in Section 2.6.3 uses the εa (n) sequence and is defined on the basis of normalised test and reference sequences to for amplitude reduction observed in wavetable function band-limiting.

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Assuming that the test and reference signals have identical frequency, any phase error will cause an increase in the error sequence amplitude due to incomplete suppression of the fundamental frequency. Therefore, when simulating phase truncation noise performance with purely phase truncated phase–amplitude mapping (i.e. no wavetable fractionally addressed interpolation) we must compensate the phase of the test signal accordingly. The AC component of the RMS noise amplitude is obtained by taking the standard deviation of the error sequence εa (n) with respect to the mean over a fixed number of samples Ns. The standard deviation σ(x(n)) of a sequence x(n) over Ns samples is defined by: vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u N s 1 u1 X σ ðxðnÞÞ ¼ t ðxðnÞ μðxðnÞÞÞ2 , ð2:27Þ N s n¼0 where μ(x(n)) denotes the mean of x(n) computed over Ns samples. We define the SNR computed over Ns samples as the ratio of the AC signal and error noise powers, thus: ! σ ðyðnÞÞ2 SNR ¼ 10 log , ð2:28Þ σ ðεa ðnÞÞ2 SNR is usually defined relative to full-scale amplitude and takes on increasingly positive values with improving performance. To complete our discussion of the SNR metric, we define the sinusoidal and multiharmonic reference waveform sequences (i.e. yr(n)) to simulation of SNR performance for several phase–amplitude mapping algorithms under various conditions. The sinusoidal and multi-harmonic reference sequences with zero phase offset are given by: hnφi2M yr ðnÞ ¼ cos 2π M , ð2:29Þ 2 khnφi2M , Ak cos 2π yr ðnÞ ¼ 2M k¼1 Nh X

ð2:30Þ

where our normal parameter denotations apply. We observe that these sequences are necessarily defined over all of the 2M phase accumulator output states and so represent the optimal phase–amplitude mapping condition. In a simulation environment these sequences are computed to full arithmetic precision and so are essentially free from quantisation noise, arithmetic round-off and phase–amplitude mapping errors due to phase truncation. These sequences are therefore exact discrete-time waveform representations with any residual errors bound only by floating point arithmetic limitations which can be made vanishingly small in typical simulation environments (e.g. Mathcad, MATLAB, etc.). To reduce computational complexity when simulating SNR performance we set the phase offset in both the reference and test signals to zero, as absolute static phase offset does not affect interpolation error.


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Full-scale (FS)

0

Amplitude (dBFS)

Spurious-free dynamic range (SFDR) Analysis noise floor Spurious signals in spectrum of

(n) Peak spur level

Frequency (Hz) Figure 2.12 A hypothetical error spectrum illustrating SFDR, peak spur level and noise floor.

2.6.2

The amplitude error spectrum The error spectrum is simply the frequency domain view of the amplitude error sequence εa (n). Since εa (n) is a discrete-time sequence we compute its spectrum by taking the discrete Fourier transform (DFT) of Ns consecutive samples of this sequence. The resulting spectrum can be plotted as a logarithmic voltage or power spectrum relative to full-scale (i.e. dBFS) to reveal both harmonic and non-harmonic spectral error components resulting from approximations in the phase–amplitude mapping process. Several scalar metrics can be determined directly from the error spectrum; of which the most useful is the spurious-free dynamic range (SFDR). SFDR is defined as the difference (measured in dBs) between full-scale and the largest component in the amplitude error spectrum. Figure 2.12 illustrates an example amplitude error spectrum showing SFDR, peak spur level and noise floor.

2.6.3

Waveshape error We define waveshape error as the difference in shape over one cycle between a digitally generated waveform and an ideal reference waveform of the same frequency and amplitude. There are fundamentally three causes of waveshape error in a digital waveform generation system: ‘analogue’ errors in the DAC and analogue post-processing stages (e.g. due to nonlinearity and slew-rate limiting mechanisms); quantisation noise due to the number of bits representing the waveform amplitude samples; finite Nyquist bandwidth resulting from discrete-time processing with a fixed sample frequency. The waveshape error metric therefore measures the deviation of a waveform’s instantaneous amplitude from an ideal or expected waveform function of the same frequency, phase and amplitude over one complete cycle. Here we are only concerned with

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quantifying waveshape errors due to finite bandwidth as this is a fundamental constraint in discrete-time processing systems with fixed sample frequency. In particular, finite bandwidth (and slew-rate limiting in the post DAC analogue processing stages) can cause significant waveshape errors in waveforms with fast step amplitude transitions or discontinuities. Non-linearity and slew-rate limiting effects are discussed in Chapter 9 as they are due entirely to the DAC and its associated analogue post-processing stages. We do not concern ourselves with quantisation noise effects13 on waveshape and assume these are negligible compared to those attributable to finite bandwidth. We can evaluate waveshape error as a scalar quantity by computing the peak magnitude of the amplitude error sequence, max jεa(n)j, over one cycle. Typically, we state this error as a percentage deviation relative to the reference waveform amplitude. We could also compute the RMS amplitude of the εa(n) sequence over one cycle and express the waveshape error as a ratio of error amplitude to reference signal amplitude. Alternatively, we can interpret the amplitude error sequence directly as a description of how the waveshape error varies over time. The instantaneous amplitude of εa(n) represents the corresponding deviation from the ideal reference waveform at sample index n. A periodic waveform function that is to be tabulated in a wavetable can be low- filtered (i.e. band-limited) before tabulation to bound harmonic bandwidth and thereby mitigate aliasing during regeneration. This necessarily introduces waveshape errors in the tabulated waveform, particularly around discontinuities or regions with high time rate of change. In digital arbitrary waveform generation, we know the desired waveshape exactly and so have a reference against which we can compare the generated waveform by simulation of a mathematical model. We can therefore predict the generated waveshape and corresponding waveshape error function for a specific waveshape, frequency and Nyquist bandwidth according to a mathematical model that describes the generation algorithm. We consider this further in Chapter 5.

2.6.4

Phase noise Phase noise describes a stochastic or quasi-stochastic variation in the instantaneous phase of a periodic signal. Variations in phase can be interpreted as a corresponding variation in the frequency or period of the signal. Accordingly, phase noise manifests itself as ‘jitter’ in the period of a waveform generated using digital phase accumulation with phasetruncated phase–amplitude mapping (i.e. DDS AWG), as illustrated in Figure 2.13. Figure 2.13 shows an example of exaggerated jitter manifestation in simple DDS sine wave generation, although the underlying error mechanisms are equally pertinent to arbitrary waveform generation. Two post-DAC (i.e. pre-reconstruction filter) staircase sample sequences are shown overlaid, one with no phase truncation (i.e. ideal phase– amplitude mapping) and the other with phase truncation where the fraction bits have been discarded. We observe two distinct errors – sample time (i.e. edge position) due to sample clock phase noise, and sample amplitude due to phase–amplitude mapping with 13

We observe that quantisation noise determines the noise floor against which we measure error components in the frequency domain.


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Sample clock with phase noise (edge jitter)

Ideal and phase-truncated waveform samples (overlaid) Edge jitter due to sample clock phase noise

Time-varying amplitude error due to phase truncation

Post reconstruction filter waveform

Aggregate jitter due to sample clock phase noise and phase truncation

Figure 2.13 Exaggerated jitter manifestation due to sample clock phase noise and time-varying phase truncation amplitude errors.

truncated phase. After reconstruction filtering, these two error mechanisms combine to become manifest as jitter (or phase noise) in the instantaneous frequency of the continuous-time sine wave. Phase noise can be expressed as the peak-to-peak deviation in period measured in seconds (typically ps or ns) or as a percentage of the period. When expressed relative to the generated waveform frequency f we observe that jitter reduces as the ratio f /fs. Phase noise is also expressed in units of dBc/Hz representing the noise power relative to the carrier power (i.e. the generated signal) within a 1 Hz bandwidth centred at specified offsets from the carrier (generated) frequency. There are principally two sources of phase noise or jitter in DDS systems: those due to intrinsic phase noise in the sample clock source; those attributable to the phase accumulation, phase–amplitude mapping approximations and DAC error mechanisms. Assuming an ideal sample clock source (i.e. zero intrinsic phase noise), DDS AWG output jitter is determined largely by approximations in the phase–amplitude mapping stage. These approximations arise from the degree of phase truncation as determined by

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the number of phase fraction bits discarded or used to approximate the phase–amplitude mapping process by phase interpolation. We must that phase–amplitude interpolation (i.e. fractional wavetable addressing) is an inherently approximating process with a finite determinable error bound. When L ¼ 2M and there is no phase truncation, phase noise in the output waveform is due primarily to residual phase noise in the sample clock source, which therefore sets a lower bound on the phase noise performance of a DDS AWG, or indeed any digital waveform generator. We consider phase noise and jitter further in Chapter 5 when we investigate DDS digital clock waveform generation.

2.6.5

Arithmetic processing requirements We now consider comparative performance measurement according to the level of computation required to execute the waveform generation algorithm in real time. A simple yet effective metric may be defined as the number of arithmetic operations14 per sample period that are needed to execute the algorithm. We group arithmetic operations into two distinct classes: elemental arithmetic operations (e.g. addition, subtraction and multiplication); and memory read and write operations (e.g. wavetable lookup). A particular algorithm is characterised according to the number of each operation required each sample period. A typical decomposition would therefore comprise the number of:

additions; subtractions; multiplications; memory reads;

required per sample period. This decomposition can be further refined by breaking it down across sub-processes within the algorithm; for example, the phase accumulation and phase–amplitude mapping stages. Aside from enabling a qualitative comparison between algorithms, this simple decomposition in conjunction with key hardware constraints such as memory access time exposes data throughput bottlenecks and suggests architectural features such as pipelining and memory interleaving. As we will see, most DDS AWG algorithms have a ‘feed-forward’ process flow that takes place between distinctly definable functional blocks with little or no interdependency between them (i.e. no global ). This makes for ‘pipeline-friendly’ processing, where an algorithm is readily decomposable into distinct processing stages separated in time allowing processing throughput to be traded for latency. We consider pipeline process decomposition and processing architectures in Chapter 8. Depending on the target implementation technology and architecture (e.g. a pipelined process flow), this decomposition is further refined to consider execution time and logic block utilisation as might apply in an FPGA or ASIC implementation. 14

In this context, we assume ‘arithmetic operations’ includes memory access and data management operations.

2.8 References

89

Memory access, particularly multiple read operations across consecutive addresses, is a fundamental operation in many DDS AWG architectures. The number of memory read operations per sample period (which is fundamental to interpolated phase–amplitude mapping, for example) is an important computation metric as it dictates memory architecture design for a given sample frequency. Typically, memory access time is enhanced by employing pipelined parallel memory arrays, interleaving the access of multiple slow memories. We consider wavetable memory architectures further in Chapter 8.

2.7

Summary In this chapter we have introduced the mathematical basis that underpins the representation and systematic generation of discrete-time (i.e. digital) signals. From this we have developed the foundations of phase accumulating frequency synthesis, which is a fundamental operation within the direct digital synthesis (DDS) model that underpins this book. DDS has been shown to comprise only two elements – phase accumulating frequency synthesis and phase to amplitude conversion, which we denote as phase– amplitude mapping. The phase–amplitude mapping operation solely determines the synthesised waveshape (e.g. sine wave) and the level and distribution of error components in the waveform amplitude spectrum. It is therefore a critical function. In an introduction to the phase–amplitude mapping of both sinusoidal and arbitrary waveforms, we introduce several important concepts that are developed in later chapters. These include, phase truncation, phase interpolation and the concept of arithmetically manipulating the phase accumulator output sequence prior to phase–amplitude mapping. This last point underpins several enhancements to DDS and enables a novel phase–amplitude mapping technique where we effectively compute the inverse discrete Fourier transform in real time. In turn, this allows us to specify a synthesised waveform from a harmonic spectrum with all of the frequency and phase control advantages of DDS. Finally, we have discussed several fundamental control parameters and their desirable attributes, followed by a definition of performance metrics which we use to compare and contrast waveform generation techniques in later chapters.

2.8

References 1. J. G. Proakis and D. G. Manolakis, Digital Signal Processing – Principles, Algorithms and Applications, 3rd edition. Prentice-Hall Inc, 1996. 2. S. J. Orfanidis, Introduction to Signal Processing. Prentice-Hall, Inc, 1996. 3. V. F. Kroupa, Direct Digital Frequency Synthesizers. IEEE Press, 1999. 4. J. H. Appleton and R. C. Perera, The Development and Practice of Electronic Music. PrenticeHall, Inc, 1975. 5. M. Serra, D. Rubine, and R. Dannenberg, ‘Analysis and synthesis of tones by spectral interpolation’, Journal of the Audio Engineering Society, 38 (3): pp. 111–128, 1990.

3

Recursive sine wave oscillators

This chapter investigates sinusoidal oscillators based upon recursive algorithms. Recursive oscillators are essentially discrete-time simulations of physical (e.g. massspring) oscillatory systems having a simple harmonic motion with zero damping as their solution. Accordingly, this type of oscillating system can only produce sinusoidal waveforms. The principal advantage of all recursive oscillators is their computational simplicity enabling low cost implementation. However, there are also several distinct shortcomings whose importance depends upon application. For example, non-linear frequency control, oscillation amplitude instability or arithmetic round-off noise growth over time. There are many recursive oscillator algorithms reported in the literature, each with its own advantages and disadvantages. It is also evident that there is no single oscillator algorithm that is optimal and satisfies all requirements. As fundamentally closed-loop systems, all recursive oscillators are bound by the discrete-time Barkhausen criteria that must be satisfied to ensure sustained, stable oscillation. The classical continuous-time Barkhausen criteria require that the total loop gain of an oscillating system be exactly unity and the total loop phase shift be an integer multiple of 2π radians. In Section 3.1 we summarise the discrete-time form where we generalise the recursive oscillator difference equations using a matrix representation, as reported by [1]. In some recursive algorithms, quantised data representation and arithmetic rounding errors often lead to violation of these criteria, causing oscillation amplitude instability over time. Before proceeding, we state the most important properties of a generic sinusoidal oscillator which we use as a basis for comparing different algorithms. These comprise:

1

independent control of amplitude, frequency and phase offset; phase-continuous1 frequency transition; linear control of frequency; sinusoid spectral purity; arithmetic overhead; constant output amplitude over time.

We define a phase-continuous frequency transition as one where the underlying phase-time function shows only a change in slope at the transition point with no step change in phase. It follows that the corresponding amplitude signal will not contain a step change at the frequency transition point, similar to analogue (i.e. continuous-time) voltage-controlled oscillator (VCO) behaviour.


3.1

91

Mathematical preliminaries In this section we outline some important mathematical principles which underpin the derivation and analysis of recursive sinusoidal oscillators. We begin by considering the well-known trigonometric angle addition formulae: cosðA þ BÞ ¼ cosðAÞ cosðBÞ sinðAÞ sinðBÞ, cosðA BÞ ¼ cosðAÞ cosðBÞ þ sinðAÞ sinðBÞ:

ð3:1Þ

If we sum these two equations and rearrange the resulting expression, we obtain a new formula which provides our first insight into a recursive process for computing a sinusoidal sequence: cosðA þ BÞ ¼ 2 cosðAÞ cosðBÞ cosðA BÞ:

ð3:2Þ

If we now consider the angle A as a ‘step angle’ in a discrete-time iterative process, Eq. (3.2) allows us to calculate the next sample of a sinusoid given two known samples and a step factor 2cos(A). If we denote a discrete-time sinusoid sequence by y(n) we can reformulate Eq. (3.2), thus: yðn þ 1Þ ¼ 2 cosðAÞyðnÞ yðn 1Þ:

ð3:3Þ

The y(n þ 1) term denotes the ‘next’ sinusoid sample, y(n) denotes the ‘current’ sinusoid sample and y(n 1) denotes the ‘previous’ sinusoid sample. Expressing Eq. (3.3) in causal form we obtain y(n) ¼ 2 cos(A)y(n 1) y(n 2), which describes the so-called direct-form or ‘biquad’ recursive oscillator. The step angle A may be defined using parameters more applicable to an oscillating system by letting A ¼ ωT, where ω denotes the angular frequency of oscillation and T denotes the discrete-time sample period. This difference equation generates a sinusoidal sequence y(n) whose amplitude and start phase depend on the initial conditions y(1) and y(2) when n ¼ 0, and whose frequency depends on the step factor 2cos(A). In Section 3.2 we derive this expression using discrete-time resonator theory and present a derivation of the initial conditions. Turner [1] presents a generic representation of any second-order recursive oscillator using a matrix rotation operation on two state variables. This representation aligns exactly with physical implementations using adders, multipliers and unit delay elements. We denote the two current state variable values by y1(n) and y2(n), and the two new values by ^y 1 ðnÞ and ^y 2 ðnÞ. Using this representation, we may express Eq. (3.3) in matrix form as follows: ^y 1 ðnÞ 2 cosðωT Þ 1 y1 ðnÞ ¼ , ð3:4Þ ^y 2 ðnÞ 1 0 y2 ðnÞ where the 2 2 matrix represents the rotation matrix. In general, where the rotation matrix takes on real-valued elements a, b, c and d, we have: ^y 1 ðnÞ a b y1 ðnÞ ¼ : ð3:5Þ ^y 2 ðnÞ c d y2 ðnÞ

92


yˆ1 (n)

y1 (0)

∑

z-1

y1 (n)

b

a

yˆ 2 (n)

y2 (0)

∑

z-1

y2 ( n )

c

Figure 3.1 Generic second-order recursive oscillator signal flow network based upon the state variable model. The four multiplying coefficients are the rotation matrix elements in Eq. (3.5).

This expression completely specifies a recursive oscillator algorithm according to a single matrix representation. Figure 3.1 illustrates the corresponding signal flow network of a generic recursive oscillator where the elements of the rotation matrix are multiplying coefficients that effectively determine the oscillator configuration. In a physical implementation, the state variables are held in unit delay elements (i.e. the z1 blocks) and so y1(n) and y2(n) represent the unit delay output values and ^y 1 ðnÞ and ^y 2 ðnÞ represent the corresponding unit delay input values. Interpretation of the 2 2 matrix is key to the discussion presented in [1] which we summarise here. The continuous-time Barkhausen stability criteria have already been outlined and have a corresponding discrete-time form which constrains the rotation matrix values according to two simple rules. The first states that the determinant of the rotation matrix must always be unity, which is analogous to the unity loop gain requirement in the continuous-time case. This condition requires that the rotation matrix satisfies ad bc ¼ 1. The second constraint states that the rotation matrix must always have complex eigenvalues and is analogous to the loop phase shift being an integral multiple of 2π in the continuous-time case. This condition requires that the rotation matrix satisfies ja þ dj < 2. Rotation matrices which satisfy these criteria will always have two complex conjugate eigenvalues with each having exactly unit magnitude. If we define the generalised 2 2 rotation matrix A as:

3.2 The direct-form

A¼

a b , c d

93

ð3:6Þ

we may define the nth oscillator output sample vector y(n) as: yðnÞ ¼ An yð0Þ,

ð3:7Þ

where y(0) represents an initial condition vector comprising y1(0) and y2(0). Using eigenvalue theory and some simplifying denotations, we may determine a general solution to Eq. (3.7) in of the digital angular frequency ωT ¼ 2πfo /fs and the state variable phase offset θs in radians, where fo denotes the oscillation frequency. We find that the general solution for any second-order recursive oscillator takes the form: cosðnωT Þ y1 ðnÞ ¼ : ð3:8Þ yðnÞ ¼ y2 ðnÞ γ cosðnωT þ θs Þ We may also define the following general relationships between oscillation parameters and the elements of the rotation matrix, thus: ωT ¼ cos 1 ðða þ dÞ=2Þ, qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1 0 ðd aÞ þ j 4 ða þ dÞ2 A, θs ¼ arg@ 2b γ¼

pffiffiffiffiffiffiffiffiffiffiffiffi c=b:

ð3:9Þ ð3:10Þ ð3:11Þ

For a given rotation matrix A, these expressions enable us to make the following generalisations about oscillator behaviour: ωT is the step angle per iteration and constrains the two leading diagonal elements of the rotation matrix; θs is the phase offset between the two state variables and hence between the output sequences y1(n) and y2(n); if a ¼ d then θs π/2 radians and we have an oscillator with quadrature outputs independent of oscillation frequency; γ is a constant that defines the relative amplitude of the two state variables; if b ¼ c then γ 1 and both state variables have the same amplitude independent of oscillation frequency; the initial condition vector y(0) determines oscillation amplitude and the phase offset relative to n ¼ 0 of both state variable outputs.

3.2

The direct-form The simplest recursive oscillator is based on the direct-form second-order resonator that can be developed directly from the z-transform pair [2]: hðnÞ ¼ rn sinðnωT ÞuðnÞ , HðzÞ ¼

r sinðωT Þz1 , 1 2r cosðωT Þz1 þ r2 z2

ð3:12Þ

94


1 n0 and ωT represents the angular digital frequency. The poles 0 n<0 of H(z) comprise the conjugate pair rejωT, where r represents the radial distance of the pole from the origin in the complex z-plane. For r 2 (0, 1), the pole pair describe an exponentially decaying discrete-time sinusoid h(n) with frequency controlled by ω and amplitude envelope rn ¼ en ln r. Setting r ¼ 1 places the poles exactly on the unit circle and produces a sinusoidal impulse response with constant unit amplitude for all n. Since H(z) ¼ Y(z)/X(z), the right-hand side of Eq. (3.12) can be written as (1 2r cos (ωT )z1 þ r2z2)Y(z) ¼ (r sin(ωT )z1)X(z). Taking the inverse z-transform of this expression yields the second-order difference equation: where uðnÞ ¼

yðnÞ ¼ 2r cosðωT Þyðn 1Þ r2 yðn 2Þ þ r sinðωT Þxðn 1Þ,

ð3:13Þ

where y(n) represents the discrete-time oscillator output sequence and x(n 1) is a forcing function which initiates oscillation at n ¼ 1, with initial conditions x(1) ¼ 0 and y(1) ¼ y(2) ¼ 0. The frequency control parameter ω is constrained so that ωT 2 (π, π) and with r ¼ 1 produces a sustained unit amplitude oscillation after the oscillator is initiated. Applying the generalised forcing function x(n) ¼ Aδ(n), where 1, n ¼ 0 δðnÞ ¼ , produces an output sinusoid of amplitude A given by y(n) ¼ A sin 0, n 6¼ 0 (nωT ), assuming x(1) ¼ 0 and y(1) ¼ y(2) ¼ 0. We observe that the impulse input function only serves to initiate the recursive process; thereafter the oscillation is self-sustaining since the poles lie exactly on the unit circle in the complex z-plane (since r ¼ 1) and so the system has zero damping. The process may be simplified by using the initial conditions y(1) and y(2) to provide the initiation stimulus, thereby eliminating the input forcing function x(n). Equation (3.13) now simplifies to: yðnÞ ¼ 2 cosðωT Þyðn 1Þ yðn 2Þ,

ð3:14Þ

with initial conditions y(1) and y(2) at n ¼ 0. Physical implementation of Eq. (3.14) is illustrated by the signal flow schematic of Figure 3.2a, where the initiating function x(n) is shown for completeness. Equation (3.14) defines the signal at the output of the summer block y(n). Figure 3.2a also shows the two state variable outputs y1(n) and y2(n), which are linearly combined according to the rotation matrix to give the next iteration value yðnÞ ¼ ^y 1 ðnÞ to the first z1 block. In the specific case of the direct-form recursive oscillator, we observe that the y1(n) and y2(n) outputs are simply integral unit delayed forms of y(n). The state variable matrix rotation representation of the direct-form oscillator is given by: ^y 1 ðnÞ k 1 y1 ðnÞ ¼ , ð3:15Þ ^y 2 ðnÞ 1 0 y2 ðnÞ where k ¼ 2 cos(ωT) and denotes the oscillator frequency control coefficient. By examining the rotation matrix in Eq. (3.15) and applying the rules presented in Section 3.1 we may deduce the following properties of the direct-form recursive oscillator:

95

3.2 The direct-form

(a)

(b) x(n)

y1 (0)

∑

x(n)

∑

y1 (n)

r sin(ωT )

y (n)

z-1

z-1

y (−1)

r cos(ωT )

y1 (n) = y ( n − 1) 2 cos(ωT )

z-1

y (−2)

y2 (0)

y 2 ( n ) = y ( n − 2)

∑

−1

z-1

y2 ( n )

− r sin(ωT )

r cos(ωT )

(c)

(d)

y1 (0) k

y1 (0)

∑

z-1

+

∑

y1 (n)

z-1

−

y1 (n)

G (n)

∑ ∑ −k

z-1 y2 (0)

y2 ( n )

k (n) +

+

∑

z-1

y2 ( n )

y2 (0)

Figure 3.2 Four different forms of the second-order recursive oscillator: (a) The direct-form or

biquad recursive oscillator; (b) The coupled-form recursive oscillator; (c) The modified coupled-form recursive oscillator; (d) The digital waveguide-form recursive oscillator.

the phase offset between state variable outputs θs is dependent on k and so the directform oscillator does not provide quadrature outputs; the two state variable outputs always have equal amplitude. Substituting the elements of the rotation matrix given in Eq. (3.15) into the generic state variable oscillator shown in Figure 3.1 we obtain the direct-form oscillator illustrated in

96


Figure 3.2a. Recalling the discussion from Section 3.1, inspecting the rotation matrix reveals that the leading diagonal elements are unequal and so the direct-form oscillator does not produce quadrature outputs. Similarly, the off-diagonal elements have opposing signs and so both outputs have equal amplitude. Referring to the y(n) output and setting the initial condition y(1) ¼ 0 yields y(n) ¼ (y(2)/sin(ωT ))sin((n þ 1)ωT ), which describes a discrete-time sinusoid with amplitude y(2)/sin(ωT ) and no phase offset term [3]. Hence, if we set y(2) ¼ A sin (ωT ), y(n) describes a sinusoid with amplitude A and frequency a function of ωT. However, we observe that there is no simple definition of y(2) alone that provides independent control of amplitude and phase offset for a particular oscillation frequency. We now consider the initial conditions required to generate the generalised discretetime sinusoid y(n) ¼ A sin(nωT þ θ) for n 0, with amplitude A, angular frequency ω, and phase offset θ relative to n ¼ 0 in radians. We first determine the z-transform of Eq. (3.14) taking of the initial conditions y(1) and y(2). We then obtain Z{y(n)} ¼ Y(z), Z{y(n 1)} ¼ z1Y(z) þ y(1) and Z{y(n 2)} ¼ z2Y(z) þ z1y(1) þ y(2), where Z{x} denotes the z-transform of x. Hence, Y ðzÞ ¼

2yð1Þ cosðωT Þ yð2Þ yð1Þz1 : 1 2 cosðωT Þz1 þ z2

ð3:16Þ

The inverse z-transform of equation Eq. (3.16) has the general form: yðnÞ ¼ AðcosðθÞ sinðnωT Þ þ sinðθÞ cosðnωT ÞÞ A sinðnωT þ θÞ

ð3:17Þ

for n 0, and defines a generalised discrete-time sinusoid. We may use Eq. (3.17) to establish a relationship between the initial conditions and the amplitude, frequency and phase of the sinusoidal oscillation. The results follow from comparing Eq. (3.16) with the inverse z-transform of Eq. (3.17) and equating the coefficients of corresponding z in the numerators of the two expressions. After some algebraic and trigonometric manipulation we obtain: yð1Þ ¼ A sinðθ ωT Þ, yð2Þ ¼ A sinðθ 2ωT Þ:

ð3:18Þ

If the angular frequency parameter in Eq. (3.14) is changed from ω to ω0 at some sample index m, the initial conditions for the ‘new’ recursion y0 (1) and y0 (2) will be the last two samples of the recursion with frequency ω, that is y0 (1) ¼ y(m 1) and y0 (2) ¼ y(m 2). The typical effect, illustrated in Figure 3.3a, is to produce a nonphase-continuous frequency transition from ω to ω0 simultaneous with a step change in amplitude from A to A0 . The underlying phase function of y(n) is shown in Figure 3.3b and clearly illustrates the phase-discontinuity at the frequency transition point. The end sample y(m 1) of the recursion with frequency ω clearly has a different phase from the initial sample y(m) of the recursion with frequency ω0 . The new recursion amplitude is dependent on ω0 and the oscillation phase (a function of y(m 1)) where the frequency transition occurs. The new amplitude A0 is found by eliminating θ from Eqs. (3.18), yielding:

3.2 The direct-form

ω

Amplitude

1

97

ω⬘

0

−1

(a) 0

500

1000

1500

2000

2500

3000

2000

2500

3000

2500

3000

8

Phase discontinuity

(b) Phase (rads)

6 4 2 0 0

500

1500

ω

1

Amplitude

1000

ω′

0

−1

(c)

Amplitude discontinuity

0

500

1000

1500

2000

Sample index n Figure 3.3 (a) Typical oscillation sequence for a direct-form recursive oscillator with a frequency

transition at n ¼ 1500; (b) Corresponding unwrapped phase revealing a phase discontinuity at the transition point; (c) Amplitude normalised oscillation sequence revealing an amplitude discontinuity.

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi yðm 1Þ cosðω0 T Þ yðm 2Þ 2 A ¼ þ ðyðm 1ÞÞ2 : sinðω0 T Þ 0

ð3:19Þ

Using Eq. (3.19) we may determine a scaling factor 1/A0 to normalise y(n) to unit amplitude following a frequency transition. However, this necessarily introduces a step

98


amplitude discontinuity into y(n) as shown in Figure 3.3c and incurs additional computation of the 1/A0 normalising term. In the absence of reinitialising the oscillator with new initial condition values, we observe that a change in ω and hence the frequency control coefficient k produces an unwanted change in amplitude simultaneous with the required change in oscillation frequency. It is evident that this amplitude change is ‘well behaved’ in that there is no step discontinuity at the transition point. However, the imposition of amplitude normalisation introduces a step amplitude discontinuity at the transition point that is undesirable in many applications. Realising constant amplitude, phase-continuous frequency transitions therefore requires computation of new initial conditions at every step frequency transition. In turn, this requires that we determine the phase of the output sample before the frequency transition point. We consider this further in Section 3.6.1. The direct-form oscillator allows dynamic frequency control (or tuning) according to a single frequency control coefficient k ¼ 2cos(ωT ). Each frequency transition requires computation of a new coefficient k according to the required angular oscillation frequency ω. However, with quantised coefficient representation we observe a varying frequency control resolution due to the non-linear relationship between ω and k. The oscillator algorithm is computationally efficient requiring only one multiplication and one addition per sample, but with an additional overhead associated with calculation of the initial condition values at every frequency transition. Amplitude control requires an additional multiply operation of the output sample or computation of new initial conditions that correspond with the required amplitude. Finally, it is instructive to consider the pole location of the underlying direct-form resonator on the complex plane. The poles of the second-order resonator transfer function given by Eq. (3.12) are located at p ¼ rejωT and p* ¼ rejωT on the complex plane. The angular pole locations correspond directly to oscillation frequency. Now the denominator of this transfer function (whose roots determine the poles) may be factored thus: 1 2r cosðωT Þz1 þ r2 z2 ¼ ð1 pz1 Þð1 þ pz1 Þ:

ð3:20Þ

We may represent the conjugate poles in Cartesian form by p ¼ (a þ jb) and p* ¼ (a jb), where a ¼ r cos(ωT ), b ¼ r sin(ωT ) and so r2 ¼ (a2 þ b2) since sin2(ωT ) þ cos2(ωT ) ¼ 1. Equation (3.20) is then expressed as: 1 2r cosðωT Þz1 þ r2 z2 ¼ 1 2az1 þ ða2 þ b2 Þz2 :

ð3:21Þ

For the direct-form oscillator we have r ¼ 1 and hence the poles are obtained from the solutions of 1 2az1 þ z2 ¼ 0 for particular values of a. (Note that the a and b used here do not correspond with those of the generic rotation matrix defined in Eq. (3.6).) Figure 3.4 illustrates the direct-form pole locations on the complex plane when the frequency control coefficient 2 cos(ωT ) and oscillator arithmetic are coarsely quantised to exaggerate the pole distribution as ωT varies over the interval [0, π). We observe that the poles all lie exactly on the unit circle and so oscillation amplitude is stable over time. However, the pole distribution exhibits increasing angular separation between adjacent poles as the oscillation frequency tends to zero and π. Since frequency control resolution

Im(z )

3.3 The coupled-form

1

99

ωT = 0.25

ωT = 0

ωT = π −1

1

Re(z )

Unit circle

−1

Figure 3.4 Direct-form recursive oscillator pole locations on the complex plane with a coarse

arithmetic quantisation interval to illustrate uneven pole distribution.

can be equated to the angular separation between adjacent poles, we observe that it is not constant over the frequency control range ωT 2 [0, π). However, the relationship between oscillation frequency and ωT is linear where we observe a large step size in the vicinity of ωT ¼ 0 and ωT ¼ π, and the smallest step size in the vicinity of ωT ¼ π/2.

3.3

The coupled-form The coupled-form oscillator is illustrated in Figure 3.2b and is defined by the state variable matrix rotation: ^y 1 ðnÞ r cosðωT Þ r sinðωT Þ y1 ðnÞ ¼ : ð3:22Þ ^y 2 ðnÞ r sinðωT Þ r cosðωT Þ y2 ðnÞ The rotation matrix operates on the initial condition vector [y1(0) y2(0)]T to effect a combined ωT rotation and r scaling on each sample event, with initial conditions y1(0) and y2(0) obviating the initialisation input x(n). Inspecting the rotation matrix in light of the results of Section 3.1, we observe that the coupled-form oscillator produces quadrature, equal amplitude outputs. Setting r ¼ 1 and the initial conditions y1(0) ¼ A cos(ωT þ θ) and y2(0) ¼ A sin(ωT þ θ) therefore produces quadrature sinusoids y1(n) ¼ A cos(nωT þ θ) and y2(n) ¼ A sin(nωT þ θ) for n 0. These sinusoids have amplitude A and phase offset θ relative to n ¼ 0.


Im(z )

100

1 ωT = 0.25

ωT = 0 1 Re(z )

ωT = π −1 Unit circle

−1

Figure 3.5 Pole distribution around the unit-circle for the coupled-form recursive oscillator with coarsely quantised ωT values. Observe how the poles have an even angular distribution around the unit-circle, but do not lie on it.

We may determine the corresponding z-domain transfer functions relative to the x(n) input whose denominators have the form 1 2az1 þ (a2 þ b2)z2, where a ¼ cos(ωT ), qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi b ¼ sin(ωT ) and r2 ¼ a2 þ b2. However, maintaining r ¼ sin2 ðωT Þ þ cos2 ðωT Þ ¼ 1 with quantised ωT values is not possible. This results in the poles being displaced from the unit circle (i.e. r 6¼ 1) and causes exponential growth or decay of the oscillation sequence amplitude over time. Figure 3.5 illustrates the pole distribution on the complex plane for the coupled-form oscillator by plotting the roots of 1 2az1 þ (a2 þ b2)z2 ¼ 0 with quantised ωT values. We use a coarse arithmetic quantisation interval to exaggerate distribution effects. Figure 3.5 illustrates two important properties of the coupled-form oscillator with quantised arithmetic. Firstly, the poles do not lie exactly on the unit circle (i.e. r 6¼ 1) which causes amplitude instability over time. For r > 1, we observe an exponential growth in amplitude and with r < 1 we observe an exponential decay in amplitude. Therefore, some programmed frequencies will produce increasing oscillation amplitude, while others will produce decaying amplitude over time. Secondly, the poles are distributed uniformly around the unit circle, resulting in a linear relationship between ωT and oscillation frequency over the range ωT 2 [0, π). Accordingly, frequency control resolution is constant over the Nyquist interval. Dynamic frequency transition is inherently phase-continuous and does not require computation of new initial condition values. The oscillator requires four multiplications

3.5 The waveguide-form

101

and two additions per sample, with further computational overhead associated with re-initialisation or scaling of the state variables [1] to correct amplitude error over large n.

3.4

The modified coupled-form An improved coupled-form algorithm overcoming the inherent oscillation amplitude sensitivity to arithmetic quantisation was first suggested by Gordon and Smith [4] and is variously known as the ‘magic circle’ or modified coupled-form oscillator. This oscillator is illustrated in Figure 3.2c and is defined by the state variable matrix rotation: ^y 1 ðnÞ 1 k 2 k y1 ðnÞ ¼ , ð3:23Þ ^y 2 ðnÞ k 1 y2 ðnÞ where k ¼ 2 sin(ωT/2). The algorithm requires only two multiplications per sample interval, is first-order and does not suffer from the quantisation sensitivities associated with maintaining r ¼ 1 as observed with the coupled-form oscillator. The matrix determinant represents the vector scaling r and is unity for all values of k and therefore independent of quantisation effects. The oscillation frequency may be dynamically updated at the sample rate, requiring computation of k for each new frequency, and frequency transitions are inherently phase-continuous. The penalty for optimal amplitude stability over n is the loss of frequency independent phase quadrature between the oscillator outputs. As the magnitude of ωT approaches π, the phase between the state variables y1(n) and y2(n) approaches zero (i.e. in phase). Only as ωT approaches zero do the outputs approach quadrature phase offset. Therefore the modified coupled-form oscillator does not provide frequency independent quadrature between y1(n) and y2(n).

3.5

The waveguide-form The second-order digital waveguide oscillator was first proposed by Smith and Cook [5] and derived from digital waveguide theory in connection with computer music research.2 The waveguide-form oscillator is illustrated in Figure 3.2d and is defined by the state variable matrix rotation: ^y 1 ðnÞ k k 1 y1 ðnÞ ¼ , ð3:24Þ ^y 2 ðnÞ kþ1 k y2 ðnÞ where k ¼ cos(ωT ).

2

The digital waveguide-form oscillator is claimed under US patent #5701393 in the domain of computer music applications.

102


This form requires one multiplication and three additions per sample when amplitude and frequency are constant. Frequency transitions are phase-continuous and therefore do not require computation of new initial condition values. However, an additional multiply operation is needed at each frequency transition to normalise the amplitude. The amplitude normalising factor is given by G(n) ¼ r(n)g(n)/g(n 1), where pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi gðnÞ ¼ ð1 kðnÞÞ=ð1 þ kðnÞÞ and k(n) denotes the time-varying frequency control coefficient at sample index n. The r(n) term is an optional exponential growth or decay per sample, with r(n) ¼ 1 for constant amplitude. When both amplitude and frequency are constant, we have G(n) ¼ 1 and only the tuning multiplication is required on each oscillator iteration. Assuming r(n) ¼ 1, at each frequency transition G(n) deviates from unity for one sample to normalise the amplitude and incurs considerable computation overhead. In contrast to the coupled-form, the waveguide-form oscillator does not suffer exponential amplitude drift due to quantisation round-off errors, since rounding only occurs at the frequency control multiplication involving k and all other computations are exact. Quantisation in the frequency control coefficient k can therefore only cause quantisation in the frequency of oscillation [5]. The oscillator outputs are exactly in phase quadrature although not of equal amplitude.

3.6

Implementation considerations In this section we outline some important considerations for implementing recursive oscillators in digital hardware or software. The choice of a particular recursive algorithm depends on many considerations such as computational overhead, equal amplitude quadrature outputs, phase continuity and frequency control. If computational overhead is not a constraint, the coupled-form oscillator satisfies all requirements and only requires imposition of an amplitude stabilising mechanism. The direct-form oscillator incurs the least computational overhead and produces inherently stable oscillation amplitude. However, it requires computation of new initial conditions at every frequency transition to maintain phase continuity and oscillation amplitude. The modified coupled-form incurs half the computational overhead of the coupledform and produces inherently phase-continuous frequency transitions. For nonquadrature applications it is probably the best compromise in most applications. Table 3.1 summarises the key properties of the recursive oscillators investigated in this chapter.

3.6.1

Initial conditions The coupled-form, modified coupled-form and waveguide-form recursive oscillators all produce phase-continuous, constant amplitude sinusoids following a step transition in the frequency control parameter k. Unlike the direct-form, they do not require new initial conditions to be computed at each frequency transition. In the case of the waveguide-form oscillator, we must apply an amplitude normalising correction

3.6 Implementation considerations

103

Table 3.1 Summary of recursive oscillator properties.

Oscillator type

k

Quadrature?

Equi-amplitude?

Multiply operations

Additions

Direct-form Coupled-form Modified coupled-form Waveguide-form

2 cos(ωT ) sin(ωT ) cos(ωT ) 2 sin(ωT/2) cos(ωT )

No Yes No Yes

Yes Yes Yes No

1 4 2 1

1 2 2 3

following each frequency transition. For an oscillation amplitude A and phase offset θ, the initial conditions for the coupled-form and modified coupled-form oscillators are given by: A sinðθÞ y1 ð0Þ ¼ : ð3:25Þ A cosðθÞ y2 ð0Þ Initialising the waveguide-form with [y1(0) y2(0)]T ¼ [A 0]T produces the output sequences y1(n) ¼ A sin(nωT) and y2(n) ¼ Aγ sin(nωT), where γ ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðcosðωT Þ þ 1Þ=ðcosðωT Þ 1Þ. We observe that as ω ! 0 γ ! ∞ and so amplitude dynamic range is a critical implementation consideration. The direct-form oscillator is attractive in many applications due to its low computational overhead. However, it requires computation of new initial conditions at every frequency transition to maintain oscillation amplitude and phase-continuity. To impose a constant-amplitude, phase-continuous frequency transition from ω to ω0 at sample index m, we require the sinusoid phase at sample index m 1. We define the phase of a particular sample with respect to the most recent zero phase point in the sinusoidal sequence and within the interval [0, 2π). If we denote the discrete-time phase argument (nωT þ θ) in Eq. (3.17) as ϕ(n), and assume a unit amplitude sinusoid (i.e. A ¼ 1), then y(n) ¼ sin(ϕ(n)) and hence ϕ(n) ¼ sin1(y(n)). The trigonometric functions are not one–one on their whole domains. To obtain inverse functions, each trigonometric function is restricted to a subset of the domain where it is one–one. The sine function is one–one on the interval [π/2, π/2] with range [1, 1]. Hence, the inverse sine function maps [1, 1] ! [π/2, π/2] in a one–one manner. To unambiguously determine the phase of a discrete-time sinusoid sample there are four phase quadrants to consider, each with intervals [0, π/2), [π/2, π), [π, 3π/2) and [3π/2, 2π), respectively. Considering the sign of y(n) and the instantaneous slope at y(n) allows the phase interval containing y(n) to be unambiguously determined. For a frequency transition at y(m), the slope λ at y(m 1) is approximately proportional to y(m 1) y(m 2). Hence we define the end-point phase, ϕ(m 1), thus: 8 1 < sin ð yðm 1ÞÞ ð yðm 1Þ > 0Þ∧ðλ > 0Þ ϕðm 1Þ ¼ π sin1 ð yðm 1ÞÞ , ð3:26Þ λ<0 : ð yðm 1Þ < 0Þ∧ðλ > 0Þ 2π þ sin1 ð yðm 1ÞÞ

104


where λ ¼ y(m 1) y(m 2) and ∧ denotes the Boolean AND operator. (Substituting n þ 1 for m in Eq. (3.26) gives a general expression for ϕ(n) as a function of y(n) and y(n 1).) We now present a method for computing initial condition values for the direct-form oscillator that produce a constant amplitude, phase-continuous frequency transition from ω to ω0 . Equation (3.26) gives the sinusoid phase at the last sample m 1 of the ‘first’ recursion. The phase offset value θ used in Eq. (3.18) is then given by: θ ¼ ϕðm 1Þ þ ω0 T ,

ð3:27Þ

where the ω0 T term denotes the phase increment from the last sample at the original frequency ω to the start point of the ‘new’ recursion at frequency ω0 . When substituting θ from Eq. (3.27) into Eq. (3.18) to compute the initial conditions for the new recursion at frequency ω0 , we have to consider three cases depending on the phase interval containing ϕ(m 1). These cases correspond to the three conditions of Eq. (3.26). In all cases we have y0 (1) ¼ (A0 /A)y(m 1), where A and A0 denote the amplitudes of the original and new recursions, respectively. We also observe the special case y0 (1) ¼ y(m 1) for unit amplitude sinusoids when A ¼ A0 ¼ 1. Using the trigonometric identity sin1(x) ¼ cos1(x) þ π/2 we find after some algebraic manipulation that the initial condition y0 (2) takes one of two values depending on the slope of y(n) just before the frequency change. Hence, we have: A0 yðm 1Þ A 8 > 0 0 1 yðm 1Þ > > þ ω cos cos T A > < A y0 ð2Þ ¼ > 0 0 1 yðm 1Þ > > cos cos T A ω > : A

y0 ð1Þ ¼

λ > 0,

ð3:28Þ

λ<0

where λ ¼ (y(m 1) y(m 2))/A. Figure 3.6 illustrates four frequency transitions for the direct-form oscillator using initial conditions obtained from Eqs. (3.28). These transitions are arranged to occur in each consecutive phase quadrant of the y(n) sequence with frequency ω0 and are observed to be both phase-continuous and have constant amplitude. The initial conditions given by Eqs. (3.28) give good results for oversampled signals, that is for frequencies ω << 2π/T. When this condition is satisfied, the initial conditions will provide a constant amplitude, phase-continuous frequency change in any of the four quadrants of the y(n) sequence.

3.6.2

Arithmetic quantisation effects All recursive algorithms exhibit some adverse behaviour with quantised arithmetic and control coefficients. Typically, three types of quantisation error phenomena are observed:

3.6 Implementation considerations

ω⬘

Output sequence y (n)

ω

105

Sample index n Figure 3.6 Constant amplitude, phase-continuous frequency transition in each phase quadrant

using initial conditions obtained from Eqs. (3.28). The transition point is shown circled and is clearly phase-continuous in each case.

variable frequency control resolution over the Nyquist interval; amplitude instability due to arithmetic round-off errors; noise growth due to arithmetic round-off errors. Coefficient quantisation displaces the poles from their intended (desired) positions on the unit circle. Two types of displacement are possible – off the unit circle (i.e. r 6¼ 1) and around the unit circle at a different angular position from that intended, but with r ¼ 1. If the poles do not lie exactly on the unit circle then r 6¼ 1 and a sinusoid with exponentially decaying or growing amplitude is produced. If the poles are displaced around the unit circle, a constant amplitude sinusoid is generated but with a frequency different from that intended. All single multiplier oscillators have their poles located exactly on the unit circle but at different locations from the ideal (i.e. non-quantised) case [3]. For example, with quantised arithmetic the direct-form oscillator has poles which lie exactly on the unit circle but are non-uniformly distributed around it as shown in Figure 3.4. For a given quantisation interval, we observe increased pole separation at low and high frequencies and a corresponding non-uniform frequency control resolution. Amplitude errors due to pole deviation from the unit circle in the coupled-form can be reduced by reinitialising the oscillator at periodic intervals when the amplitude error has exceeded a predefined threshold [6]. The question of how to determine the re-initialisation period can be addressed by considering the amplitude envelope rn. We first define the pole radius using quantised number representation by qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rq ¼ QðsinðωT ÞÞ2 þ QðcosðωT ÞÞ2 , where Q(x) denotes x quantised to a particular quantisation interval. We next define the pole unit-radius deviation error d ¼ j(rq 1)j. For very small d, which applies for most practical quantisation intervals, we observe that the amplitude growth and decay envelopes (i.e. (1 þ d)n and (1 d)n, respectively)

106


are mutually reciprocal, that is (1 þ d )n (1 d )n. Therefore the metric of max(d ) computed over the required frequency range can be used to determine a worst case amplitude envelope (1 þ max(d ))n for a particular quantisation interval and oscillation frequency. The amplitude envelope can then be used to determine the re-initialisation period for a particular amplitude error and frequency range. Assuming data samples are represented to b-bits of precision, each coefficient multiplication produces a 2b-bit product which must be truncated or rounded down to b bits on each recursion. This causes the oscillator output to deviate from the ideal over time. Rounding is preferred to truncation since it makes some use of the discarded information, but essentially the least significant b-bits of information are lost on each multiplication. (The nature of 2’s complement number representation causes the directform 1 multiplication in the direct-from oscillator to be exact.) Addition and subtraction operations with quantised operands produce results which fit within the operand word size, provided arithmetic overflow or underflow is prevented by ensuring suitable headroom. Arithmetic round-off errors can lead to increasing error in the oscillation sequence whose nature depends on the particular algorithm. We model the round-off error as the variance of the output noise caused by arithmetic round-off, similar to that presented in the recursive digital filter literature. The direct-form oscillator round-off error variance over Ns samples is approximated by σ2(Ns) 2bNs/6 sin2(ωT ) when N s >> 2π=ωT [3]. The noise variance (i.e. noise power) increases steadily with Ns and is inversely proportional to sin2(ωT). The direct-form oscillator therefore requires periodic re-initialisation to prevent the build up of round-off noise and signal-to-noise ratio (SNR) falling below an acceptable level. Alternatively, as reported in [3], first- or second-order error can be incorporated inside the direct-form oscillator coefficient loop to significantly reduce the noise variance. The coupled-form oscillator exhibits only amplitude error due to quantisation effects, although re-initialisation to bound the error magnitude is still necessary in practice. The modified coupled-form provides invariant oscillation amplitude with coefficient quantisation, with SNR bound only by sample quantisation noise.

3.6.3

Frequency control All recursive oscillators have control coefficients which are a sine or cosine function of the oscillation frequency ω. The direct-form oscillator provides a linear transfer function between ω and the oscillation frequency that exhibits a variable step size with quantised arithmetic. This assumes that the frequency control coefficient k is generated by a function which computes k ¼ cos(ωT ). This may be implemented in practice by using a lookup table. The coupled-form oscillator provides a linear transfer function between ω and the oscillation frequency that exhibits a fixed step size with quantised arithmetic. Of course, this assumes computation of sin(ωT ) and cos(ωT ) coefficients from an ω argument. Single multiplier oscillators such as the direct-form and waveguide-form exhibit an inverse cosine relationship between the frequency control coefficient k and oscillation frequency. Only if we compute k as a function of ω do we realise a linear

3.7 Summary

107

transfer characteristic. The direct-form oscillator, whose frequency control coefficient is a cosine function of ωT, therefore exhibits reduced frequency control resolution at low frequencies for a given quantisation interval. As ωT tends to zero or π, the slope of the coefficient 2cos(ωT ) also tends to zero and hence progressively more bits are required to represent 2cos(ωT ) to a given accuracy. Conversely, the modified coupledform oscillator, whose frequency control coefficient is a sine function of ωT, exhibits increased frequency control resolution at low frequencies for a given quantisation interval.

3.7

Summary In this chapter we have introduced the second-order recursive sinusoidal oscillator and developed a generic mathematical model based on a matrix rotation of two state variables. This model allows all second-order oscillators to be represented by a fixed signal flow network, where only four parameters specify the type of oscillator. The four rotation matrix elements determine oscillation frequency and the relative phase shift and amplitude between the state variables. We have investigated four popular oscillators reported in the literature and compared their respective attributes against several important performance metrics. These metrics include quadrature outputs, equal amplitude outputs and amplitude stability with quantised arithmetic. Each of these oscillators performs well against some metrics, but no one form satisfies them all. The direct-form oscillator is the simplest in of arithmetic complexity, requiring only a single multiply operation per sample, and provides non-quadrature, equal amplitude outputs with a unit sample delay between them. Amplitude is stable when computed with quantised arithmetic, although there is a growth in quantisation noise over time. Frequency transitions are not phase-continuous. The coupled-form is the most costly oscillator in of arithmetic complexity, requiring four multiply operations per sample, but provides equal amplitude, quadrature outputs. However, the coupled-form suffers from amplitude instability due to quantisation effects. Frequency transitions are always phase-continuous. The so-called modified coupled-form algorithm achieves amplitude stability with quantised arithmetic and requires only two multiplications per sample, although the trade-off is a loss of quadrature outputs. Frequency transitions are always phase-continuous. Finally, the waveguide-form requires only a single multiplication per sample and provides quadrature outputs with unequal amplitude, although amplitude is stable with quantised arithmetic. An additional amplitude normalising multiply operation is required at each change of frequency tuning coefficient. Frequency transitions are phase-continuous. We have reviewed the important implementation considerations common to all recursive oscillator forms. These include arithmetic complexity, frequency control resolution and the initial conditions required to start the recursion process. In all cases, the frequency tuning coefficient is a trigonometric function (i.e. sine or cosine) of the required oscillation frequency. This causes a non-linear relationship between the tuning coefficient(s) and oscillation frequency over the tuning range of the oscillator. Recursive

108


oscillators offer an optimum solution in applications where single or quadrature sinusoids with limited frequency control flexibility are required, for example, multi-level frequency shift keying (FSK) applications. It should also be ed that harmonic distortion performance for all recursive forms is excellent and bound only by arithmetic quantisation effects. If quadrature signals are not required the direct-form can offer an excellent solution, requiring only a single multiplication. Periodic re-initialisation (or initialisation when required for use) mitigates any quantisation noise growth and is easily implemented.

3.8

References 1. C. S. Turner, ‘Recursive discrete-time sinusoidal oscillators’, IEEE Signal Processing Magazine, May, pp. 103–111, 2003. 2. S. J. Orfanidis, Introduction to Signal Processing, Prentice-Hall, Inc, 1996. 3. A. I. Abu-El-Haija, and M. M. Al-Ibrahim, ‘Improving performance of digital sinusoidal oscillators by means of error ’, IEEE Transactions on Circuits and Systems, Vol. CAS-33, No. 4, 1986. 4. J. W. Gordon, and J. O. Smith, A sine generation algorithm for VLSI applications. Proceedings of the 1985 International Computer Music Conference, Vancouver, 1985. 5. J. O. Smith and P. R. Cook, The second-order digital waveguide oscillator. Proceedings of the 1992 International Computer Music Conference, San Jose, 1992. Available online at http://ccrma.stanford.edu/~jos/wgo/. 6. F. Curticapean, K. Palomäki and J. Niittylahti,. Hardware implementation of a quadrature digital oscillator. Proceedings of NORSIG, Kolmården, Sweden, June 2000.

4


In this chapter we investigate DDS sine wave generation as an introduction to a general discussion of DDS arbitrary waveform generation in Chapter 5. We begin by reviewing phase accumulation frequency synthesis, discuss considerations for demonstrating sinusoidal DDS behaviour through computer simulation and finally review several important sinusoidal phase–amplitude mapping techniques. Relative performance is illustrated using simulated SNR, SFDR and amplitude spectra as a function of key control and design parameters. We focus on phase truncated wavetable indexing and introduce linear phase interpolation as an error reduction mechanism that gives nearoptimal performance in most practicable applications (i.e. SNR and SFDR comparable to or better than amplitude quantisation noise). Optimal sinusoidal phase–amplitude mapping with practicable wavetable lengths is accomplished with a technique that we call trigonometric identity phase interpolation. This technique uses the trigonometric angle summation identity to compute a phase– amplitude mapping whose SNR and SFDR are bound only by quantisation noise. Although computationally more costly than linear interpolation, this technique is easily adapted to generate exactly quadrature sinusoids with optimal SNR and SFDR. A reduced multiplication implementation is also possible that trades multiplication for addition operations and is presented in Chapter 8. The principal utility of this technique is in applications which require optimal SNR and SFDR performance simultaneous with phase offset control precision bounded by the phase accumulator resolution.

4.1

Phase accumulation, truncation and arithmetic processing In Chapter 2 we introduced the concept of phase accumulation as a fundamental frequency synthesis process and showed how it follows from the definition of discrete-time instantaneous phase. Phase accumulation may therefore be summarised as the discrete-time integration of a frequency variable (or phase increment) with respect to time to yield phase. In a physical realisation, an M-bit binary accumulator generates a discrete-time phase sequence ϕ(n) whose slope and hence frequency f is a linear function of a phase-increment control parameter φ. We observe that φ should strictly be denoted as a time-varying sequence φ(n) that is pertinent to frequency modulation (FM) or frequency sweep applications that we investigate in Chapter 6.

110


Indeed, there is no reason why any of the typical DDS control parameters (e.g. frequency, phase offset or amplitude) cannot be time-varying sequences provided the Nyquist sampling criterion is observed. However, for brevity within our present discussion, we assume that φ is a fixed control parameter that sets waveform frequency. In this section we investigate phase accumulation in more detail, the phase truncation constraints imposed by practicable phase–amplitude mapping and arithmetic manipulation of the phase sequence to provide static and dynamic phase offset. We conclude by introducing the idea of phase domain processing which describes several techniques that impose further arithmetic processing between the phase accumulator and phase–amplitude mapping stages. These novel techniques enable the generation of harmonic frequency phase sequences, power consumption optimised high speed phase accumulator designs, and suppression of error spurs associated with phase truncation.

4.1.1

Ideal sinusoidal DDS In this section we consider the ideal sinusoidal DDS architecture, which we define as one where there are no errors due to arithmetic approximation in the digital domain.1 The two principal error sources that we consider later are phase truncation (or phase quantisation) and amplitude quantisation. We begin by reviewing the important properties of phase accumulation and consider the ideal phase to amplitude conversion case where there is no phase truncation and all possible accumulator phase states are uniquely mapped into the amplitude domain. Similarly, we assume that the sinusoid amplitude samples are represented with infinite precision and hence there is no quantisation noise. As we shall see later, both of these conditions are impossible to attain, but serve to illustrate an optimal DDS performance baseline. Assuming a sampling frequency fs, the frequency of the phase accumulator output sequence (or equivalently the accumulator overflow rate) is given by f ¼ φfs/2M and indicates that the phase increment parameter φ provides exactly linear frequency control. The frequency control resolution is therefore fs/2M and determined by the sample frequency and accumulator word size alone. The phase accumulator output sequence ϕ(n) can be defined by the modulo bounded difference equation ϕðnÞ ¼ hϕðn 1Þ þ φi2M , or equivan X φðmÞ. lently ϕðnÞ ¼ hnφi2M for constant φ. For time-varying φ, we have ϕðnÞ ¼ m¼1

For a given sample frequency, arbitrarily fine frequency resolution is obtained by appropriate selection of only one design parameter – the accumulator word size M. In principle, the value of M and hence frequency control resolution can be increased without bound and is only constrained by hardware speed. Following a step change in φ, the corresponding change in the slope of ϕ(n) (and therefore instantaneous frequency) occurs with a latency of one sample period and is exactly phase-continuous. 1

‘Analogue’ non-linearity error mechanisms are always present in the DAC and reconstruction filter stages to some degree, and can only be minimised, but never eliminated.

111

4.1 Phase accumulation, truncation and arithmetic processing

Phase accumulators that use unsigned integer arithmetic can only generate integervalued phase sequences with positive slope that overflow and wrap around through zero and are therefore bound on the interval [0, 2M 1]. Such sequences correspond exactly with the definition of positive frequency. Alternatively, phase accumulation using 2’s complement (i.e. signed) integer arithmetic as suggested by Moore [1] yields phase sequences that are bound on the interval [2M1, 2M1 1] with positive or negative slope as determined by the sign of the phase increment φ. Phase sequences with negative slope underflow to positive full-scale, exactly satisfying the definition of a negative frequency, which is important in some frequency modulation applications. For the remainder of this book we assume unsigned phase accumulator arithmetic where φ 2 [0, 2M1 1] and only requires M 1 bits to represent it. Both signed and unsigned phase accumulator arithmetic produce integer-valued phase sequences that do not directly satisfy the radian-valued argument that is required by the sine function which is defined on the phase interval [0, 2π). However, we observe that the unsigned phase accumulator domain interval [0, 2M 1] corresponds exactly with the interval [0, 2π), with a phase resolution of 2π/2M radians. Multiplying ϕ(n) by the scaling factor 2π/2M generates a radian-valued phase sequence that is bound on the interval [0, 2π) (or [π, π) for signed phase accumulator arithmetic). Implementation of this scaling multiplication is unnecessary with wavetable phase–amplitude mapping since it is incorporated as part of the sine function tabulation as defined by Eqs. (2.12) and (2.13). The phase accumulator generates a sawtooth phase sequence ϕ(n) whose slope (and hence frequency) is determined by φ and whose maximum amplitude (and hence the number of possible phase values) is given by 2M. ϕ(n) is characterised by a numerical period P which is defined as the minimum value of P for which ϕ(n) ¼ ϕ(n þ P) and varies with φ for a given value of M. The numerical period is defined by [2]: P¼

2M , ðφ, 2M Þ

ð4:1Þ

where (a, b) denotes the greatest common divisor between the integer arguments a and b. An important result from [2] is that the numerical period of the wavetable amplitude sequence will be identical to that of ϕ(n) and hence the discrete spectrum of the amplitude sequence will comprise exactly P points.2 Phase accumulation is only part of the DDS waveform generation process. To generate a sinusoidal waveform we have to convert the phase sequence ϕ(n) to an amplitude sequence using a phase–amplitude mapping function which is typically a lookup table or wavetable. In the ideal case we have no phase truncation and the wavetable tabulates 2M sine samples represented with full arithmetic precision. The waveform output is then represented by the discrete-time sequence sin(2πϕ(n)/2M). Figure 4.1 illustrates the ideal DDS sine wave generator which includes a phase offset adder (that we discuss further in Section 4.1.5), a 2M sample wavetable and an

2

This result only applies to the number of points in the optimal discrete spectrum of the DDS output.

112


fs

ϕ

φ (n)

M ∑

z-1

M ∑

M

Sine wavetable

∏

DAC

y (t )

M

θ

y (n)

M

A Figure 4.1 The ideal DDS sine wave generator.

amplitude scaling multiplier. The discrete-time sine wave y(n) feeds a DAC and reconstruction filter to produce the continuous-time output signal y(t). For our present discussion, we ignore the effects of finite amplitude quantisation and corresponding quantisation noise. The ideal DDS generator produces a discrete-time sine wave sequence y(n) at the input to the DAC which is given by: φ θ yðnÞ ¼ A sin 2π n M þ M , ð4:2Þ 2 2 with amplitude A, frequency φ and phase offset θ. We observe that this expression is in exact agreement with the definition of an ideal discrete-time sinusoid. In the next section we consider the frequency domain characteristics of ideal phase–amplitude mapping.

4.1.2

Optimal phase–amplitude mapping Optimal phase–amplitude mapping is realised when the wavetable contains 2M tabulated samples and all 2M phase accumulator output states are mapped to a unique amplitude value, assuming sufficiently fine amplitude quantisation. In other words, all M bits of the phase accumulator output sequence ϕ(n) are used to address the wavetable whose length L ¼ 2M. Under these conditions, the wavetable output samples are exactly equivalent to those of a generalised discrete-time sinusoid for all phase-increment values. We now consider the ideal sinusoidal phase–amplitude mapping case as expressed by Eq. (4.2), where no phase truncation is imposed; and for brevity we assume the phase offset θ ¼ 0 and A ¼ 1. We also assume that the tabulated samples are stored with infinite precision allowing us to ignore amplitude quantisation errors and consider the ideal phase–amplitude mapping alone. A 2M sample sinusoidal wavetable, where the element ath location value we denote by S[a], is defined by: a S ½a ¼ sin 2π M , a ¼ ½0, 2M 1: ð4:3Þ 2


113

Since there is no phase truncation all M phase accumulator bits are used to index the wavetable whereupon a ¼ ϕðnÞ ¼ hnφi2M and hence y(n) ¼ S[ϕ(n)]. Our ideal discretetime DDS output sequence y(n) is therefore given by: hnφi M yðnÞ ¼ sin 2π M2 , ð4:4Þ 2 φf with frequency fo ¼ Ms. After digital to analogue conversion we obtain the correspond2 ing continuous-time sinusoid y(t) given by: yðtÞ ¼

n¼∞ X

sinð2πfo nT Þhðt nT Þ,

ð4:5Þ

n¼∞

where h(t – nT) represents the zero-order hold DAC transfer function and T ¼ 1/fs. Subsequent reconstruction filtering realises the band-limited continuous-time sine waveform. The discrete Fourier transform of y(n), denoted by Y^ ð f Þ, is given by the Poisson summation formula [3]: ∞ X

Y^ ð f Þ ¼ fs

Y ð f mf s Þ,

ð4:6Þ

m¼∞

where Y( f ) denotes the spectrum of the periodic continuous-time signal y(t) ¼ sin(2πfot), which represents the ideal DDS output signal assuming an ideal DAC and reconstruction filter. Y( f ) is given by: Yð f Þ ¼

∞ X

ck δð f kf o Þ,

ð4:7Þ

k¼∞

where ck denotes the kth complex Fourier coefficient of y(t) and δ(n) is the unit impulse 1 n¼0 function defined by δðnÞ ¼ . 0 otherwise Since y(t) is periodic with period To ¼ 1/fo, the complex Fourier coefficients are given by: Tðo

ck ¼ fo yðtÞe2πjf o kt dt:

ð4:8Þ

0

Substituting Eq. (4.7) into Eq. (4.6) we obtain the discrete magnitude spectrum of y(n), thus: Y^ ð f Þ ¼ fs

∞ ∞ X X

jck jδð f mf s kf o Þ:

ð4:9Þ

m¼∞ k¼∞

The DAC zero-order hold transfer function appends a shaping function H( f ) to Y^ ð f Þ which is defined by: Hð f Þ ¼ ejπ f T sincð f T Þ,

ð4:10Þ

114


0 − 3.9

Amplitude (dB)

− 10

fo

f

sinc

fs − 20 − 30 − 40 0

0.5

1

2

3

4

5

6

Frequency (cycles/sample) f fs Figure 4.2 Alias images for the ideal sinusoidal DDS showing the sinc function amplitude envelope according to Eq. (4.11). The fundamental signal is at fo.

where sinc(x) ¼ sin(πx)/πx denotes the normalised sinc function. Equation (4.9) now becomes: Y^ ð f Þ ¼ ejπ f T sincð f T Þf s

∞ ∞ X X

jck jδð f mfs kfo Þ:

ð4:11Þ

m¼∞ k¼∞

For y(t) as defined by Eq. (4.5) we have jckj ¼ 1 (i.e. only the fundamental frequency component is present). Equation (4.11) indicates that DDS with optimal phase–amplitude mapping causes all frequency components that compose y(t) to be aliased about every harmonic of the sample frequency fs. If y(t) is an ideal sine wave (i.e. jckj ¼ 1) the discrete spectrum contains only those frequencies in the periodically replicated set {(mfs fo), m ¼ 0, 1, 2, . . .}. The component corresponding to m ¼ 0 is the synthesised sine wave and all others are alias images. We observe that there are only alias images of fo in the spectrum of y(n) as expected. Alternatively, if y(t) is a non-sinusoidal waveform, the corresponding harmonic spectrum would be aliased around integer multiples of the sampling frequency resulting in a significantly different spurious performance. Finally, we observe that the amplitude envelope of the alias spectrum is weighted according to a sinc function sin(πf T )/πf T. This causes a steadily ‘drooping’ -band response that is 3.92dB down at the Nyquist frequency when fT ¼ 0.5. This can be corrected in the design of the reconstruction filter response by introducing a compensating gain peak at the cut-off frequency. Figure 4.2 illustrates this behaviour for the ideal DDS case with a single fundamental sinusoid at fo.

4.1.3

Phase truncation and fractional wavetable addressing To limit wavetable lengths to practicable values when 2M is large (as consistent with fine frequency control resolution) we truncate the M-bit phase accumulator output sequence to I-bits with I < M. This imposes a corresponding wavetable length L ¼ 2I samples.


115

fs

ϕ

M

φ (n) ∑

-1

z

M ∑

M

φI (n) I

Sine wavetable

y (n)

M

θ

F M

φF (n)

Figure 4.3 Partitioning the M-bit phase accumulator output into integer and fraction fields denoted

by ϕI (n) and ϕF (n), respectively. Phase truncated wavetable indexing corresponds with ϕI (n) indexing the wavetable as shown.

This process is generally known as phase truncation or phase quantisation and is illustrated in Figure 4.3, which shows an M-bit phase accumulator whose output is partitioned into integer and fraction components with the integer component indexing the wavetable. We can now interpret ϕ(n) as a fixed-point fractional quantity comprising an I-bit integer field ϕI (n) and an F-bit fraction field ϕF (n), which represents the phase fraction whose unit-normalised value we denote by α(n) 2 [0, 1). Figure 4.4 illustrates a truncated phase representation comprising integer and fraction fields that may be collectively interpreted as a fractional address. In its simplest form, only the I-bit ϕI(n) field is used to index the wavetable and we discard the F-bit fraction field ϕF(n). This specific case is known as phase truncated wavetable indexing in the literature. We observe that the fraction field may be truncated from the available M – I bits to optimise hardware implementation. When we require frequency control resolution consistent with a large value of M, but do not require the full F-bit precision that corresponds to a specific value of I imposed by the wavetable length, we may truncate the F-bit fraction field to F^ -bits. This is effected by discarding the R least significant bits such that F ¼ F^ þ R and so M ¼ I þ F^ þ R. Fraction field truncation is necessary when we need to match the error-bound of a specific phase–amplitude mapping algorithm with an appropriate ^ fractional phase resolution 2π=2IþF to optimise available processing resources (e.g. logic block utilisation in an FPGA implementation). There comes a point with any phase interpolation algorithm, when increasing the phase fraction resolution (i.e. increasing F^ ) contributes no further improvement in the accuracy of the interpolated amplitude value. We now present expressions which define non-truncated, truncated and fractional phase sequences that we use to model the phase accumulation and interpolated phase– amplitude mapping process. These expressions define the phase sequences obtained with phase accumulation frequency synthesis and are the foundation of both sinusoidal and arbitrary waveform generation using DDS. Strictly, there are two distinct phase truncation cases to consider:

116


MSB

2 M −1

2 I −1

2 M −2

2 I −2 I

Integer address φI (n) 1 2−1

φ (n)

M

M

Phase truncation

Fˆ ˆ

2 − F +1

F

Fractional address φFˆ (n) = φF (n) R = 0

ˆ

2− F 21 LSB

R discarded bits

R

20

Figure 4.4 Phase truncated ϕ(n) partitioning showing truncation of the fraction field.

rounded down phase truncation where the phase fraction bits are discarded; rounded to nearest value phase truncation where the phase fraction information is used to round the integer phase to the nearest value above or below the fractional value. The non-truncated M-bit phase accumulator output sequence ϕ(n) with constant phase increment φ, is defined by: ϕðnÞ ¼ hnφ þ ϕð0Þi2M 2 0, 2M 1 , ð4:12Þ where the initial phase ϕ(0) 2 [0, 2M 1] and φ 2 [0, 2M1 1] denotes the phase increment that controls output frequency given by fo ¼ φfs/2M. The I-bit rounded down truncated phase sequence is defined by: ϕI ðnÞ ¼

j ϕðnÞ k 2

F

2 0, 2I 1 ,

ð4:13Þ

where the residual fraction field F is completely discarded with F ¼ M I. The rounded to nearest value I-bit truncated phase sequence is defined by: ϕIr ðnÞ ¼

Dj ϕðnÞ 2

F

þ 0:5

kE 2

I

2 0, 2I 1

ð4:14Þ

and is expressed modulo 2I to preserve the correct domain since the rounding operation includes the output value 2I which is outside the interval [0, 2I 1]. The integer-valued F-bit fraction phase sequence is defined by: ϕF ðnÞ ¼ ϕðnÞ 2F ϕI ðnÞ 2 0, 2F 1 , ð4:15Þ


117

and the corresponding unit-normalised F-bit fixed-point rational fraction value is defined by: αðnÞ ¼

ϕF ðnÞ 2 ½0, 1Þ: 2F

ð4:16Þ

The variable α(n) represents the fractional interpretation of ϕF(n) and is equivalent to the fractional phase between the integer-spaced ϕI(n) and ϕI(n) þ 1 phase values. α(n) is used when we introduce interpolated phase–amplitude mapping in Section 4.1.4. For completeness, we define the truncated fraction field case when R > 0 and we have a reduced F^ -bit fraction field which is defined by: ϕF^ ðnÞ ¼ 2R

j ϕðnÞ 2F ϕ ðnÞ k I 2 0, 2FR 1 R 2

ð4:17Þ

and ^ ðnÞ ¼ α

ϕF^ ðnÞ ^

2F

2 ½0, 1Þ,

ð4:18Þ

^ ðnÞ denote the R-bit truncated forms of ϕF (n) and α(n), respectively. where ϕF^ ðnÞ and α To simplify our present discussion we assume R ¼ 0 and so F^ ¼ F, which gives: ϕðnÞ 2F ϕI ðnÞ þ ϕF ðnÞ 2 0, 2M 1 ð4:19Þ For I < M this phase sequence is interpreted as the ‘I.F-bit’ fixed-point fractional quantity ϕI(n) þ α(n) which fractionally addresses the wavetable through phase– amplitude interpolation or phase interpolation for brevity. We also define the radian phase truncation error sequence ϕε (n) as: 2π ϕε ðnÞ ¼ 2F ϕI ðnÞ ϕðnÞ M , 2

ð4:20Þ

with ϕε(n) 2 [0, 2π/2I). For a round to nearest value phase truncation we replace the ϕI (n) term in Eq. (4.20) with ϕIr (n) and observe that now ϕε (n) 2 [2π/2I þ 1, 2π]. A lower bound of 2π is required to for the specific condition when ϕIr (n) ¼ 0 (having wrapped around through 2I 1) while ϕðnÞ >> 0. As ϕ(n) approaches 2M 1 when ϕIr (n) ¼ 0, so ϕε(n) approaches 2π radians. This condition is prevented by phase unwrapping ϕε (n) by adding 2π to ϕε (n) when the condition ϕIr (n) ¼ 0 and ϕ(n) > 2F 1 is detected. In general, the condition ϕε (n) ¼ 0 only occurs when (φ, 2F) ¼ 2F. We now illustrate the effects of phase truncation by simulating an unsigned 12-bit phase accumulator whose output sequence is truncated to a 4-bit phase sequence that indexes a 16 sample wavetable tabulating a single sine wave cycle. Simulation results are presented in Figures 4.5a to 4.5c, using parameter values contrived to exaggerate the principal error mechanisms for both types of phase truncation. Accordingly, we have M ¼ 12, I ¼ 4 and φ ¼ 217. The small number of possible phase states in the truncated phase sequence helps to visualise phase errors which cause corresponding phase– amplitude mapping errors when compared to the optimum reference case when all M phase bits index a 2M (i.e. 4096) sample wavetable.

118


4096

(a)

φ (n)

2048

0

0

10

20

30

40

50

16

(b)

φI (n) φIr (n)

Round to nearest Round down

8

0 0

10

20

30

40

50

0.5

(c)

Round to nearest Round down

0.25

φε (n) (rads)

0

− 0.25 − 0.5

0

10

20

30

40

50

n Figure 4.5 Illustrative phase sequences from a simple phase accumulator with M ¼ 12 and φ ¼ 217: (a) Non-truncated reference phase sequence; (b) Overlaid rounded down and rounded to nearest value truncated phase sequences with I ¼ 4; (c) Corresponding phase error sequences in radians.

We observe from Figure 4.5c that the rounded down ϕε (n) error sequence is offset with respect to the corresponding rounded to nearest value and is always negative with a mean of 2π/2Iþ1 radians. Conversely, the rounded to nearest ϕε(n) sequence oscillates symmetrically about zero and therefore produces zero mean phase error. We use the following amplitude sequence definitions which are generalised as y(n). In all cases, the output frequency is given by fo ¼ φfs/2M. The ideal reference sinusoid, assuming a 2M sample wavetable, is given by:


yðnÞ ¼ S½ϕðnÞ,

119

ð4:21Þ

where S[a] represents a sine wavetable indexing operation with address a. The rounded down phase truncated sinusoid assuming a 2I sample wavetable is defined by: yðnÞ ¼ S½ϕI ðnÞ:

ð4:22Þ

Finally, the rounded to nearest phase truncated sinusoid assuming a 2I sample wavetable is defined by: yðnÞ ¼ S½ϕIr ðnÞ:

ð4:23Þ

From these expressions we may determine the corresponding amplitude error sequences according to Eq. (2.25), which can be used to visualise the effects of phase truncation. The sinusoidal amplitude sequences corresponding to the ideal, rounded down and rounded to nearest truncated phase sequences are shown in Figures 4.6a, 4.6b and 4.6d, respectively. Figures 4.6c and 4.6e show the respective amplitude error sequences as defined by Eq. (2.25) and illustrate the presence of significant signal distortion due to the discarded phase information. The effects of reduced phase resolution due to phase truncation are indicated by consecutive samples having the same amplitude. This effect is observed for both types of phase truncation. However, the amplitude of the rounded to nearest amplitude error sequence is lower than that for the rounded down case since some of the otherwise discarded phase fraction information is used in determining the truncated phase value, therefore producing a better amplitude approximation to the phase value and reducing the amplitude error magnitude. Closer inspection reveals that the rounded down phase truncated error sequence contains a significant fundamental frequency component due to an effective phase shift of 2π/2Iþ1 radians caused by the rounded down phase truncation. This violates one of the conditions of Eq. (2.25) which requires that the generated and reference signals be exactly in phase for an optimal amplitude error estimate. Adding a 2π/2Iþ1 phase offset to the signal defined in Eq. (4.22) provides the required phase compensation causing the rounded down phase truncated amplitude error to resemble that of the rounded to nearest phase truncated amplitude error shown in Figure 4.6e. To provide an optimal amplitude error estimate as defined by Eq. (2.25), we therefore add a 2π/2Iþ1 phase offset to the rounded down phase–amplitude mapping expression. This ensures that the rounded down phase truncated SNR value is not overly pessimistic by including a significant (non-erroneous) component at the fundamental frequency fo, as illustrated in the amplitude error spectrum of Figure 4.7b. An alternative approach that eliminates relative phase dependencies entirely, computes the magnitude of the amplitude error signal in the frequency domain. Figure 4.7a illustrates the spectrum of the reference sinusoid when all M phase accumulator bits are used in the phase–amplitude mapping process. The spectrum has been computed using a 4096 point FFT (i.e. 2M points) to eliminate bin leakage effects, as every error spur then lies exactly on an FFT bin centre from the discrete spectrum result in Section 4.1.1. Figures 4.7b and 4.7c illustrate the amplitude error sequences

120


1

S[φ (n)]

0

(a)

− 1 0

10

20

30

40

50

10

20

30

40

50

10

20

30

40

50

10

20

30

40

50

10

20

30

40

50

1

S[φI (n)]

0

(b)

− 1 0 0.5

(c) S[φ I (n)] − S[φ (n)]

0

− 0.5

0

1

S[φ Ir (n)]

0

(d)

− 1 0 0.5

(e) S[φ Ir (n)] − S[φ (n)]

0

− 0.5

0

n Figure 4.6 Amplitude sequences corresponding to the phase sequences of Figure 4.5: (a) Reference sinusoid with L ¼ 2M; (b) Rounded down phase truncated sinusoid with L ¼ 16; (c) Corresponding amplitude error sequence; (d) Rounded to nearest phase truncated sinusoid with L ¼ 16; (e) Corresponding amplitude error sequence.


121

Figure 4.7 Reference and phase truncated amplitude error spectra corresponding to Figures 4.6a,

4.6b and 4.6d: (a) Reference sinusoid spectrum with L ¼ 2M; (b) Rounded down phase truncated amplitude error spectrum with I ¼ 4 and L ¼ 16; (c) Rounded to nearest phase truncated amplitude error spectrum with I ¼ 4 and L ¼ 16.

that correspond to the rounded down and rounded to nearest phase truncation cases, respectively. These simulated spectra do not include amplitude quantisation errors and are computed to full floating point precision.3 The reference sinusoid spectrum shows only a single line corresponding to the fundamental frequency. The absence of spurious 3

Arithmetic quantisation noise is therefore better than –300db relative to full-scale and therefore negligible.

122


spectral lines across the Nyquist band confirms the optimality of phase–amplitude mapping with L ¼ 2M. The spurious-free dynamic range is observed down to the noise floor of better than 300 dB corresponding to the floating point arithmetic precision used in the simulation. The two truncated phase amplitude error spectra are identical except for a residual fundamental component in the rounded down truncated phase error spectrum. Amplitude spectrum errors associated with truncated phase–amplitude mapping are manifest in the frequency domain as discrete spectral components that are generally inharmonically related to the fundamental frequency and distributed across the Nyquist interval. The number, amplitude and frequency of these components have been shown analytically to be determined by only three parameters – the accumulator word size M, the number of phase fraction bits F (i.e. the degree of phase truncation) and the phase increment φ [2]. We explore this result further in Section 4.2 when we discuss important theoretical analysis reported in the literature. These results enable the selection of contrived design and control parameter values, which DDS behavioural demonstration and performance simulation.

4.1.4

Linear phase interpolation In Section 4.1.3 we saw how phase truncation errors are manifest as waveform amplitude distortion causing error components in the amplitude spectrum. We may reduce the magnitude of these errors by using the otherwise discarded fractional phase information to fractionally address the wavetable through a process we call phase interpolation. We use this denotation since we are interpolating tabulated phase– amplitude values according to a fractional phase. Linearly interpolated fractional wavetable addressing is the simplest phase interpolation technique and provides a computationally efficient way to significantly reduce phase truncation errors. We consider higher-order phase interpolated fractional addressing more fully in Chapter 5 and recognise that linear interpolation provides sufficient accuracy for most sinusoidal phase–amplitude mapping requirements. The function of an interpolation algorithm is to estimate an amplitude sample lying between the tabulated values according to a fractional address. Phase interpolation using the fractional phase information effectively estimates the amplitude sample that would have been produced by an ideal phase–amplitude mapping using a 2M location wavetable. Linear phase interpolation approximates the underlying continuous sine wave function that is tabulated in the wavetable by piecewise-linear functions that interconnect adjacent tabulated points. For a given fractional address we determine a continuous linear function that connects the tabulated values surrounding the fractional address. We then use this linear approximation function to compute the sample value corresponding to a particular fractional address as illustrated in Figure 4.8. In general, this process is applied to any two adjacent tabulated points that span a fractional address. Figure 4.8 denotes the tabulated values as functions of an arbitrary independent variable xi which only takes on discrete unit-spaced values (i.e. i ¼ 0, 1, 2, . . .) and is analogous to the wavetable address in our present discussion. We denote the

123


y

f (x2) f (x) f ⬘(x) = f (x1) + a ( f (x2) − f (x1)) ≈ f (x)

a ( f (x2) − f (x1))

f (x1)

y = f (x)

f (x1)

a = x − x1 x1

x

x2

x

Figure 4.8 Linear interpolation between two tabulated points f (x1) and f (x2) of an arbitrary

function f.

corresponding tabulated values by f (xi), where the function f represents the underlying function being tabulated in the wavetable. For a sinusoidal wavetable, we have f (x) ¼ sin(x). The slope of the linear segment between the tabulated points f (x1) and f (x2) is given by ( f (x2) f (x1))/(x2 x1), which simplifies to f (x2) f (x1) for a unit-spaced tabulation where xi þ 1 xi ¼ 1, and always applies in the wavetable case. In general the linear segment slope is given by f (xiþ1) f (xi). The linearly interpolated value at some fractional address x which we denote by f 0 (x) is then given by the simple linear function f 0 (x) ¼ f (x1) þ α( f (x2) f (x1)), where α denotes the fractional part of the independent variable and is given by α ¼ x x1. We have introduced the concept of linearly interpolating a tabulated data set to estimate the value of the underlying continuous function at a fractional table location. We may now define linear phase interpolation as applied to sinusoidal DDS phaseamplitude mapping thus: yðnÞ ¼ S½ϕI ðnÞ þ αðnÞ½S½ϕI ðnÞ þ 1 S½ϕI ðnÞ,

ð4:24Þ

where the variables have their normal definitions and we observe two wavetable read operations are required to generate the consecutive samples S[ϕI (n)] and S[ϕI (n) þ 1] needed in the interpolation. Figure 4.9 illustrates a schematic linear phase interpolation signal flow where we assume the hypothetical sine wavetable memory provides both S[ϕI (n)] and S[ϕI (n) þ 1] outputs simultaneously. In Chapter 8 we investigate several memory and arithmetic processing architectures that computationally efficient linear phase interpolation. From a mathematical perspective, linear phase interpolation is a first-order polynomial interpolation. In Chapter 5 we present an outline tutorial on polynomial interpolation and investigate the application of higher-order interpolating polynomials to reduce phase–amplitude mapping errors when fractionally addressing a wavetable tabulating an arbitrary waveform function. However, as we show in Section 4.3, where

124


fs

ϕ

S[φ I (n)]

φ I (n)

M ∑

-1

z

M

I

− Sine wavetable

∑ +

M

φF (n)

F

S[φ I (n) + 1]

∑

y (n)

∏

α (n)

Figure 4.9 Signal flow of DDS linear phase interpolation using the phase fraction component ϕF (n). We assume the sine wavetable produces both samples simultaneously. (The phase offset adder has been omitted for clarity.)

we present simulated performance results, linear phase interpolation combined with relatively small wavetables provides excellent error performance in sinusoidal DDS applications.

4.1.5

Static and dynamic phase offset The partitioned nature of phase accumulating DDS enables precise and independent control of signal phase. In this section we consider the imposition of a fixed phase offset by adding a constant θ 2 [0, 2M 1] modulo 2M to the M-bit phase accumulator sequence that we now denote ϕ0 (n) as depicted in Figure 4.10. If we assume that the wavetable indexed by the phase offset sequence ϕ(n) contains a single-cycle sinusoid (or indeed a single cycle of any periodic waveform function) we impose a phase offset4 of 2πθ/2M radians to the generated signal. The offset phase sequence ϕ(n) is given by ϕðnÞ ¼ hϕ0 ðnÞ þ ϕ0 ð0Þ þ θi2M , and the control resolution of the M-bit phase offset is 2π/2M radians: θ provides a phase offset relative to an arbitrary point in time. If that point is taken to be at n ¼ 0, we must ensure that the phase accumulator is correctly initialised. Imposing the initial condition ϕ0 (0) ¼ 0 ensures that θ provides a phase offset equal to 2πθ/2M radians relative to n ¼ 0. Truncating ϕ(n) to I-bits effectively reduces the phase offset control resolution to 2π/2I radians with θ 2 [0, 2I 1], and assuming phase truncated wavetable indexing, only requires an I-bit phase offset adder. In the subsequent discussion and associated illustrations, we assume an M-bit phase offset adder to for possible interpolated phase–amplitude mapping. In this case, the sine wavetable block is assumed to comprise both wavetable and interpolation processing. If we use the F-bit fractional phase information to linearly (or higher order) interpolate the phase–amplitude mapping process, we observe a phase offset control resolution that is generally better than the 2π/2I value and bounded by the amplitude interpolation error. This, of course, requires that we retain an M-bit phase offset adder to exploit the greater 4

Relative to a fixed time reference point (e.g. the phase accumulator sample clock).

125


fs

ϕ

φ ⬘(n)

M ∑

z-1

M ∑

M

φ (n) = φ ⬘( n) + θ

2M

φ ⬘(0) = 0 M

θ

M

Figure 4.10 Phase accumulator with phase offset adder.

phase offset control resolution if required. The trigonometric identity phase interpolation algorithm described in Section 4.3.5 provides phase–amplitude mapping accuracy consistent with a 2M sample wavetable (i.e. optimal phase–amplitude mapping) but with a significantly reduced memory utilisation of 2M/2þ2 samples. In principle, this approach allows phase offset control with a resolution that approaches the ideal and is bound only by amplitude quantisation noise and DAC phase errors. In this discussion we have assumed that the phase offset is static and θ is constant. However, there is no reason why the phase offset cannot be a time-varying parameter (now denoted as θ(n)), thereby providing dynamic phase offset or phase modulation consistent with the Nyquist bandwidth. We consider this further in Section 4.1.7 and Chapter 6.

4.1.6

Quadrature sine wave generation The inherent DDS capability to impose an exact phase offset to the phase sequence before phase–amplitude mapping enables systematic generation of exactly quadrature sinusoids (i.e. two identical frequency sinusoids with a phase difference of 90 or π/2 radians). Moreover, it is possible to arrange precise ‘detuning’ of the quadrature phase offset with control resolution bound only by the accumulator word size M. Figure 4.11 illustrates a hypothetical arrangement where a single phase accumulator feeds two identical phase–amplitude mapping stages each comprising a wavetable tabulating an identical sinusoid. One of the sine wavetables is preceded by a phase offset adder which adds a fixed offset of 2M2 equivalent to π/2 radians to generate cosine amplitude samples for optimal quadrature operation. Varying this phase offset around the quadrature value provides a precise ‘deviation from quadrature’ adjustment with a control resolution of 2π/2M radians (assuming optimal phase–amplitude mapping). Since this is a hypothetical arrangement to illustrate the underlying concept, we assume that each wavetable is 2M samples long thereby providing optimal phase– amplitude mapping. In practice, each wavetable would comprise a more practicable wavetable length of 2I samples requiring phase truncation to I-bits and possibly

126


I

Sine wavetable

fs

ϕ

yQ (n)

DAC

yQ (t )

DAC

y I (t )

M ∑

z-1

y I (n)

M ∑

I

Sine wavetable

M

θ

M

Figure 4.11 Hypothetical quadrature DDS sine wave generation with adjustable quadrature phase error.

augmented with linear phase interpolation. For simple phase truncation as shown in Figure 4.11, the quadrature deviation control resolution reduces to 2π/2I radians. For applications requiring fixed quadrature sine wave generation we can dispense with the phase offset adder and tabulate sine and cosine (i.e. quadrature) waveform functions in the respective wavetable. Finally, we observe that this technique is not confined to quadrature sinusoids. In principle, any number of so-called polyphase sinusoidal waveforms can be generated with this technique, each with an independently adjustable phase offset from a nominal reference phase. Figure 4.12 illustrates this concept for a hypothetical 3-phase sinusoidal waveform generator, where yA(t) represents the reference phase signal. The utility of polyphase sinusoidal and arbitrary waveforms is considerable since the relative phase of each signal can be independently controlled relative to a reference channel. It is evident that the example architecture illustrated in Figure 4.12 is readily extendable to any number of channels simply by adding more phase offset adders and phase–amplitude mapping sections as necessary. One example of a polyphase signal application is the emulation of 3-phase power signals which have a nominally 120 (2π/3 radians) phase shift between phases. Using DDS we can generate 3-phase test waveforms with independently controllable relative phase and amplitude that simulate specific real-world operating or failure modes. If we extend these test signals to include arbitrary waveforms (which we consider in Chapter 5), we can emulate applicationspecific non-sinusoidal test signals (e.g. sinusoids with a particular harmonic distortion characteristic). In Chapter 5 we discuss the generation of low jitter clock waveforms using ‘hard limited’ sinusoidal DDS. Combining the polyphase concept with hard-limiting of the output sinusoid enables the generation of polyphase digital clock signals that are synchronous to a single reference clock and have independent control of relative timing and absolute frequency. The time difference between a clock edge and the corresponding reference channel edge is linearly proportional to the phase offset. If we assume a phase truncated phase–amplitude mapping with an I-bit wavetable index, the time difference control resolution is θk/( fo2I), where θk 2 [0, 2I 1] and denotes the phase


I

Sine wavetable

y A (n)

127

DAC

y A (t )

DAC

yB (t )

DAC

yC (t )

fs

ϕ

M ∑

z-1

M

y B (n) ∑

I

Sine wavetable

M

θB

M

M

yC (n)

∑

θC

I

Sine wavetable

M

Figure 4.12 Extending the phase offset technique to generate polyphase waveforms. In principle, the number of phase offset channels is unbounded.

offset control value for channel k, and fo is the output frequency. If we tabulate an inverted sine function in the phase offset channel wavetables and baseline our phase offset values to 2I1, we may adjust the relative timing of each channel to lead or lag the reference channel.

4.1.7

Introducing phase domain processing Generalising our earlier discussion of static phase offset control, we now introduce the concept of phase domain processing, which we define as the arithmetic processing of the phase accumulator output sequence ϕ(n) before phase–amplitude mapping. Typically, this processing is used to impose fixed phase offset, phase modulation, specialised frequency control, truncated phase dithering and noise shaping. The last two operations decorrelate phase truncation errors and thereby suppress error spurs in the DDS amplitude spectrum at the expense of a marginally elevated noise floor. Phase dithering effectively ‘spreads’ the discrete spur energy uniformly across the Nyquist bandwidth, hence raising the mean noise level. Noise shaping exhibits a similar spreading effect (thereby eliminating error spurs), but offers an additional benefit of further suppressing the noise floor in the vicinity of the generated signal in a high- manner. We consider phase dithering and noise shaping further in Section 4.3.3 where we present simulated amplitude spectra for some example DDS scenarios.

128


Any arithmetic processing of the phase accumulator output sequence must ensure exact modulo 2M ‘wraparound’ to ensure discontinuity-free phase–amplitude mapping. We are therefore constrained to the following class of arithmetic operations: constant phase offset hϕðnÞ þ θi2M ; dynamic phase offset or phase modulation hϕðnÞ þ θðnÞi2M ; integer phase multiplication hkϕðnÞi2M , k 2 Z, k > 0; truncated phase dithering hϕI ðnÞ þ ϑðnÞi2I , ϑ(n) 2 [0, 2F 1] where ϑ(n) denotes a pseudo-random sequence; ‘delta-sigma’ (ΔΣ) modulation of the phase truncation process.

The latter process, which can be generalised as so-called ‘noise shaping’, involves ΔΣ modulation of the phase error sequence ϕF (n). The modulated error sequence is then added to the truncated phase sequence ϕI (n) modulo 2M. Advanced noise shaping algorithms include a filter in the ΔΣ modulator. The order and noise shaping transfer function of the ΔΣ modulator are determined entirely by the filter transfer function.

4.2

Theoretical analysis of DDS phase truncation errors In this section we summarise a theoretical analysis of DDS errors due to phase truncation and amplitude quantisation. Both of these error mechanisms are the dominant cause of error spurs in the DDS amplitude spectrum, thereby reducing SFDR and SNR. Comprehensive analytical work on sinusoidal DDS behaviour has already been presented in the literature, notably [2] and [4]. An excellent discussion is also provided in [5]. We discuss the important concepts that underpin this work and present the key results that enable us to determine parameter values which expose specific behaviours for illustrative purposes using computer simulation of a mathematical model. In Chapter 5 we extend these models to include DDS arbitrary waveform generation. They also provide useful formulae for initial design investigation and the verification of computer simulations. Nicholas et al. [2] and [4] derive a mathematical algorithm for calculating the exact number, frequency and amplitude of error spectrum spurs for any value of φ, M and F within a sinusoidal DDS model. However, to general sinusoidal and arbitrary waveform DDS computer models, we are only concerned with determining values of φ which produce worst case error spectra and SNR due to phase truncation. These models also allow imposition of real-world hardware constraints such as amplitude quantisation error and phase fraction truncation.

4.2.1

The DDS error model Figure 4.13 illustrates a DDS error model based upon that presented in [2]. The model incorporates several independent error sources introduced into an otherwise ideal system. These error sources comprise:

4.2 Theoretical analysis of DDS phase truncation errors

129

fs

ε s (t ) ϕ

∑

M

ε p (n) φ (n)

∑

z-1

∑

ε q (n) I

Sine wavetable

∞

∑

ε D (t ) b

DAC

∑

y (t )

φI (n) M Figure 4.13 ADDS error model showing four important error sources.

sample clock phase noise or jitter εs (t); phase truncation noise εp (n) due to I < M; amplitude quantisation noise εq (n) due to tabulating samples with finite amplitude precision; DAC conversion errors (e.g. non-linearity and intrinsic noise) εD(t). Refinements of this error model not considered here include: frequency control error due to quantised control with finite resolution according to M; amplitude errors caused by approximation-based wavetable compression (e.g. Taylor series methods); non-linearity errors in the post-DAC reconstruction filter and subsequent analogue processing. The two errors that concern us in this section are the phase truncation and amplitude quantisation noise sequences. We discuss the effects of sample clock phase noise in Chapter 5 when we investigate DDS clock sources. In Chapter 9 we investigate DAC conversion and post-processing errors.

4.2.2

Phase truncation errors Nicholas et al. [2] and [4] derive theoretical expressions for the number of spurs in the phase truncated DDS amplitude spectrum, their amplitude and relative position as a function of M, φ, F and fs. The most important element in deriving the DDS amplitude spectrum is determining the spectrum of the phase error sequence εp(n) which is equivalent to ϕF(n) in a fractional phase representation. In this section we only summarise the analysis presented and the important results. It is instructive to consider the characteristics of the phase error sequence, which we can derive by first defining the phase truncated sinusoidal sequence y(n), thus: 2F nφ yðnÞ ¼ sin 2π M : ð4:25Þ 2 2F

130


Equation (4.25) may be rewritten in an equivalent form where we introduce the phase error sequence εp(n) in the phase argument: 2π ð4:26Þ yðnÞ ¼ sin M nφ εp ðnÞ : 2 Comparing the two phase arguments of Eqs. (4.25) and (4.26) yields an expression for εp(n), thus:

nφ ð4:27Þ εp ðnÞ ¼ nφ 2F F : 2 We observe that εp(n) only depends on φ and F, and is a periodic sawtooth sequence. A critical observation in the analysis is that εp(n) can be modelled as a sampled continuous-time sawtooth waveform which we denote εp(t) with amplitude 2F and frequency φ/2F. Furthermore, the sawtooth waveform is identical to that produced by an F-bit phase accumulator with phase increment hφi2F . Phase truncation errors only occur when (φ, 2M) < 2F. If (φ, 2M) 2F then ϕF (n) ¼ 0 for all φ that satisfy this condition (i.e. the F fraction bits are zero and no phase truncation occurs). The principal result is that the number of spurs in the amplitude spectrum depends on φ through the function (φ, 2F) alone. As a consequence, values of φ that have the same value of (φ, 2F) cause the number of spurs and their respective amplitudes to remain the same. Only the position of each spur (i.e. its frequency) in the error spectrum changes. After considerable analysis it is shown in [2] that the number of spurs in the amplitude spectrum, including the fundamental, is given by: Λ¼

2F : ðφ, 2F Þ

ð4:28Þ

and is a maximum when φ is a prime causing (φ, 2F) ¼ 1. Hence the maximum number of spurs, including the fundamental, is given by Λmax ¼ 2F. (Note that the present use of Λ to denote the number of spurs is slightly different from [2]. In that work, the number of spurs excluding the fundamental is defined as 2Λ 1 where Λ is a variable in the analysis.) An alternative graphical description states that amplitude spectra with equal values of Λ, but different values of φ, are permutations of each other. To maximise the number of spurs in our simulated spectra we therefore choose values of φ which yield (φ, 2F) ¼ 1. This also maximises the noise energy in the error spectrum and therefore gives a worst case SNR. Therefore, all values of φ that yield the same value of (φ, 2F) produce equal SNR. Values of φ which give (φ, 2F) ¼ 2F yield εp(n) ¼ 0 and Λ ¼ 1 and so produce no error spurs in the amplitude spectrum. Figure 4.14 illustrates simulation of Λ and SNR behaviour with φ for a simple DDS with M ¼ 12 and I ¼ 6. The relatively small phase accumulator word size allows all possible 2047 φ values to be simulated and plotted on logarithmic scales. Since F ¼ 6, we observe that Λmax ¼ 64. Figure 4.14a illustrates the behaviour of Eq. (4.28) over this range of φ and shows that Λ can only take on specific values (i.e. 1, 2, 4, 8, 16, 32 and 64). As expected, this corresponds exactly with Figure 4.14b where Λ ¼ 1 and Λ ¼ 2F yield maximum and minimum SNR, respectively. We observe that minimum SNR (i.e. worst


131

100

Number of spurs L

(a)

10

I = 6 M = 12 1 1 >200

10

I = 6 M = 12

100

1000

L =1 ⇒ SNR = ∞

10000

(b)

SNR dB

30

28

26

24 1

10

100 j

1000

10000

Figure 4.14 Simulated variation of Λ and SNR with φ for a simple DDS system with M ¼ 12 and I ¼ F ¼ 6. SNR maxima are evident when Λ ¼ 1 (i.e. only the fundamental frequency line is present in the amplitude spectrum). Observe that values of φ that yield the same value of (φ, 2F) produce equal SNR.

case) occurs for all odd φ values. Maximum SNR when Λ ¼ 1 is bound only by floating point round-off error in the Mathcad simulation (>200 dB). Nicholas et al. [2] and [4] also derive a useful expression for the level of the largest spur in the phase truncated amplitude spectrum relative to the carrier that is given by: ζ max ¼ 6:02I þ 3:92 dBc:

ð4:29Þ

This result represents the minimum (i.e. worst case) SFDR relative to the carrier. Vankka [6] reports maximum and minimum phase truncated SFDR approximations based on a different analytical approach, thus:

132


SFDRmax 6:02I þ 3:92 dB, SFDRmin 6:02I dB:

ð4:30Þ

Vankka [6] also reports similarly derived maximum and minimum phase truncated SNR approximations, thus: SNRmax ¼ 6:02I 3:92 dB, SNRmin ¼ 6:02I 5:17 dB:

ð4:31Þ

The exact SFDR or SNR figure is a function of φ. A further result presented in [4] is based upon the observation that the minimum worst case spur amplitude always corresponds with odd values of φ. This result is used to develop a simple modification to the phase accumulator that produces a significant improvement in ζmax by forcing the phase accumulator output sequence to belong to a class for which (φ, 2Mþ1) ¼ 1 for all φ. Under this condition, the largest spur amplitude asymptotically approaches a value of 2FM ¼ 2I as F increases and so ζmax ¼ 6.02I dBc, representing an improvement of exactly 3.92 dBc that is independent of φ. This modification is easily implemented by dividing the sample clock by two to generate an alternating single bit sequence that is fed into the carry input of the phase accumulator adder. This effectively emulates an (M þ 1)-bit phase accumulator where the least significant bit of the phase increment is always a 1. The modified phase accumulator simulates a doubling of frequency control resolution by adding an extra bit to its word length while simultaneously halving the frequency control resolution by only allowing φ to take on odd values.

4.2.3

Wavetable sample quantisation errors In this section we consider the effects of wavetable sample quantisation on the SNR of the synthesised signal. Quantisation of the tabulated amplitude sample introduces noiselike signal impairments which are distinct and independent of those due to phase truncation. The corresponding error signal is generally known as quantisation distortion or quantisation noise in the literature and is well described for continuously sampled signals. Its magnitude is a function of the number of bits (and hence discrete amplitude quantisation levels) that represent the waveform samples and the particular characteristics of the signal being quantised. This discussion is pertinent to both sinusoidal and arbitrary waveform DDS techniques. An important result from [2] is that the sequence of amplitude quantisation errors is periodic according to the numerical period P of the phase accumulator output sequence as defined by Eq. (4.1). The effects of amplitude quantisation alone may then be included in the ideal sinusoidal DDS output sequence, thus: yðnÞ ¼

n¼∞ X

sinð2πf o nT Þ þ q hniP ,

ð4:32Þ

n¼∞

where fo ¼ φfs/2M and q(n) represents the periodic quantisation error sequence for a particular value of φ and phase accumulator initial condition value [5]. Hence we obtain:


φ yðnÞ ¼ sin 2π M n þ q hniP : 2 n¼∞ n¼∞ X

133

ð4:33Þ

The q(n) values are considered as random error quantities, and when P >> 1 are considered as uniformly distributed on the interval [q/2, q/2], where q denotes the fixed quantisation interval that is equivalent to the least significant bit (LSB) amplitude value. When P ¼ 2M, which occurs when φ and 2M are relatively prime (i.e. (φ, 2M) ¼ 1) and M is large, the q(n) sequence can be considered as statistically independent and therefore uniformly distributed on [q/2, q/2] [5]. The noise spectrum under this condition contains equal amounts of amplitude modulation (AM) and phase modulation (PM) noise, similar to wideband noise [5]. Analysis presented in [5] takes Eq. (4.33) and determines an expression for the discrete noise power spectral density Sn( f ), thus: 2 σ 2 sinðπfk T Þ , ð4:34Þ S n ð f k Þ ¼ e P πfk T where fk ¼ k/PT with k 2 [0, P) and σ 2e is the quantisation error variance that we consider shortly. The noise spectrum is therefore a ‘sinc-squared’ weighted line spectrum comprising P equally spaced lines, each having an amplitude proportional to σ 2e . Tabulating a waveform (e.g. a sinusoid) necessarily involves amplitude quantisation according to the number of bits b that represent the wavetable amplitude samples. We therefore define the SNR due to amplitude quantisation noise as: 2 σ SNR ¼ 10 log x2 , ð4:35Þ σe where σ 2x and σ 2e represent the signal and quantisation error variances, respectively. For an ideal quantiser, which we denote by the function Q(x), with equal quantisation intervals q, input range xmax and word-length b bits, we have σ 2e ¼ q2 =12 where q ¼ 2xmax/2b. If we now assume that xmax ¼ 1, Q(x) is defined thus:

x x ð4:36Þ ¼ 21b 1b : QðxÞ ¼ q q 2 We now define the waveform crest factor C as the ratio of peak to RMS waveform value and hence C ¼ xmax/σx ¼ 2b1 q/σx. We may then express the signal and quantisation error variances as σ 2x ¼ x2max =C 2 and σ 2e ¼ q2 =12 ¼ x2max 22b =3, respectively [7]. Finally, we may express SNR in of C and b alone, thus: ! 2 3 22b C dB: ð4:37Þ ¼ 6:02b 10 log SNR ¼ 10 log 3 C2 pffiffiffi A sinusoidal signal has C ¼ 2 and gives the well-known result SNR ¼ 6.02b pffiffiffi þ 1.76 dB. However, a non-sinusoidal signal such as the triangle wave has C ¼ 3 and gives SNR ¼ 6.02b dB, slightly less than the sinusoidal value. Rectangular pulse-like signals with reducing duty-cycle D5 have increasing crest factor according to 5

Duty-cycle is defined as the ratio of waveform ‘on’ time to period.

134


pffiffiffiffiffiffiffiffiffi C ¼ pffiffi1=D ffi , and hence steadily degrading SNR. When P is large, all signals with C > 2 that are amplitude quantised and tabulated in a wavetable give a reduced SNR compared to the sinusoidal value. In general, when tabulating non-sinusoidal arbitrary waveforms we must consider crest factor when determining SNR.

4.3

Sinusoidal phase–amplitude mapping In this section we investigate several sinusoidal phase–amplitude mapping algorithms that use both wavetable lookup and direct computation of the sine function from a phase argument. Given its wide utilisation, we investigate compression of the sinusoidal wavetable by exploiting the quadrant symmetry of the sine function. We focus on algorithms that use wavetable lookup as they underpin the application of DDS to the generation of non-sinusoidal arbitrary waveforms that we investigate in Chapter 5. Where appropriate, we present computer simulations of the amplitude spectrum, SNR and SFDR performance metrics to allow a comparative assessment between algorithms. These simulations use design and control parameter values that are chosen to demonstrate important behaviours or performance variation. Unless stated otherwise, all simulation figures presented in this section have been computed to full floating-point precision and are therefore effectively free from quantisation noise and demonstrate errors due to phase truncation only. We begin by reviewing the effects of amplitude quantisation and oversampling on sinusoidal DDS signal to noise ratio.

4.3.1

SNR and oversampling In Section 4.2.3 we discussed quantisation errors associated with finite amplitude quantisation of the wavetable samples in of a corresponding SNR metric. We now introduce two additional design parameters which affect the overall SNR figure – DAC full-scale headroom and oversampling ratio. These are strictly ‘system level’ design considerations and common to any digital waveform generation technique. However, we include them here as their principal utility is to allow optimisation of SNR in both sinusoidal or arbitrary waveform generators. We define the DAC full-scale headroom as the fraction of full-scale amplitude αF at which we operate the output DAC. Setting αF < 1 provides an amplitude margin or headroom before DAC saturation and hence waveform distortion. Such a margin might be required if we are applying amplitude control in the digital domain where the signal amplitude is occasionally set above some baseline value. The corresponding reduction in SNR is simply 20 log (αF), observing that αF is always bound on the interval [0, (2b1 1)/2b1] assuming a normalised full-scale of 1. The second parameter is the oversampling ratio βR which is defined as the ratio between the ‘processing’ (e.g. DDS phase accumulator) sample frequency fs and an equivalent sample frequency corresponding to twice the analogue bandwidth of the post-DAC reconstruction filter B (i.e. the analogue output bandwidth), and so βR ¼ fs/2B. In non-oversampled or critically sampled systems, βR is close to unity and can only take

4.3 Sinusoidal phase–amplitude mapping

135

on values greater than unity. To understand the principal advantage of oversampling we must that quantisation noise power is normally spread uniformly across the entire Nyquist band. Limiting our operating bandwidth to less than the Nyquist bandwidth therefore provides a predictable noise reduction in accordance with the oversampling ratio. The corresponding increase in SNR is simply 10 log (βR) and can only take on positive values since βR 1. We now combine these results with Eq. (4.37) to define an overall SNR expression due to amplitude domain error mechanisms, thus: 2 C þ 20 logðαF Þ þ 10 logð βR Þ dB: SNR ¼ 6:02b 10 log ð4:38Þ 3 This expression is applicable to both sinusoidal and arbitrary waveforms and defines SNR as a function of four key design and waveform parameters:

the the the the

number of bits b used to represent the wavetable amplitude samples; crest factor C of the waveform function tabulated in the wavetable; fraction of full-scale αF at which we operate the output DAC; oversampling ratio βR.

In a typical implementation, only C is a function of the waveform tabulated in the wavetable andpall ffiffiffi other parameters are fixed by the design. For sinusoidal waveforms, we have C ¼ 2 and so the corresponding SNR term is 1.76 dB as expected.

4.3.2

Phase truncated wavetable indexing We begin by considering the simplest phase–amplitude mapping algorithm based upon rounded down phase truncation as introduced in Section 4.1.3. The wavetable is indexed by the phase truncated sequence ϕI(n) to produce an amplitude sample that we denote by S[ϕI (n)] and which approximates the ideal sample SM[ϕ(n)] (i.e. where L ¼ 2M). Hence SM[ϕ(n)] S[ϕI (n)]. For a given sample word size and hence quantisation noise level, there are only two design parameters to consider – M and I. Once these have been defined according to the required frequency control resolution and wavetable length constraints, the size of the fraction phase field F is fixed. To demonstrate error spur behaviour in the phase truncated sinusoidal DDS amplitude spectrum caused by small changes in φ we now present simulated spectra for a simple system with M ¼ 12 and I ¼ 6. We recall from Section 4.2.2 that the number of error spurs Λ is bound according to Λ 2F and so will always be small (i.e. Λmax ¼ 64 when M ¼ 12 and I ¼ 6), helping to visualise permutation of spur positions in the error spectrum. For all prime values of φ we observe from Eq. (4.1) that P ¼ 2M and so we can compute the exact discrete amplitude spectrum with a relatively short (and therefore fast) 2M point FFT. To demonstrate more realistic DDS behaviour with larger values of M, we present simulated amplitude spectra for M ¼ 16 and M ¼ 32. The M ¼ 16 spectra have been computed with a 64k point FFT and so are exact representations of the discrete DDS


Amplitude (dBFS)

0

ϕ = 241 I = 6 Λ = 64 M = 12

(a)

− 10 − 20 − 30 − 40 − 50 − 60 − 70

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 251 I = 6 Λ = 64 M = 12

(b)

− 10 − 20 − 30 − 40 − 50 − 60 − 70

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 257 I = 6 Λ = 64 M = 12

(c)

− 10 − 20 − 30 − 40 − 50 − 60 − 70

0

0.1

0.2

0.3

0.4

0.5

0

Amplitude (dBFS)

136

ϕ = 263 I = 6 Λ = 64 M = 12

(d)

− 10 − 20 − 30 − 40 − 50 − 60 − 70

0

0.1

0.2

0.3

0.4

0.5

Normalised frequency f f s Figure 4.15 Permutation of amplitude spectrum error spurs with variation in φ for a simple

phase truncated sinusoidal DDS. φ values have been chosen to ensure that each spectrum has Λ ¼ 64.

137


Amplitude (dBFS)

0

ϕ = 262 I = 6 Λ = 32 M = 12

(a)

− 10 − 20 − 30 − 40 − 50 − 60 − 70

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 268 I = 6 Λ = 16 M = 12

(b)

− 10 − 20 − 30 − 40 − 50 − 60 − 70

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 280 I = 6 Λ = 8 M = 12

(c)

− 10 − 20 − 30 − 40 − 50 − 60 − 70

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 304 I = 6 Λ = 4 M = 12

(d)

− 10 − 20 − 30 − 40 − 50 − 60 − 70

0

0.1

0.2

0.3

0.4

0.5

Normalised frequency f f s Figure 4.16 Amplitude spectra for a simple phase truncated DDS with φ chosen to illustrate four

values of Λ.

138


amplitude spectrum. The M ¼ 32 spectra have been computed with a non-radix-2 length FFT chosen to minimise bin leakage. Figure 4.15 shows four amplitude spectra with M ¼ 12, I ¼ 6 and prime number values of φ which all yield Λ ¼ 64. These spectra demonstrate the error spur permutation according to the φ value for constant Λ. Figure 4.15 dramatically illustrates the change in spectrum for a relatively small change in frequency according to φ. The number of spurs is fixed at 64, but their relative positions are permuted across the four spectra. In some cases (e.g. Figure 4.15c), spurs are grouped in closely spaced pairs and are almost coincident. In other cases (e.g. Figure 4.15a), they are evenly spaced across the Nyquist interval. Figure 4.16 shows four amplitude spectra for a simple sinusoidal DDS with M ¼ 12 and I ¼ 6 where non-prime values of φ have been chosen to give spectra with Λ ¼ 32, Λ ¼ 16, Λ ¼ 8 and Λ ¼ 4 according to Eq. (4.28). Since the maximum number of spurs is 2F ¼ 64 and relatively small, the error spurs are always clearly visible. Figure 4.16 illustrates the change in spectrum as Λ reduces, where we observe that the spectrum lines are always fairly evenly distributed across the Nyquist interval. In all of these spectra, error spurs are generally non-harmonically related to the fundamental and are located above and below the synthesised frequency. Figures 4.17 and 4.18 show a collection of amplitude spectra over variation in I for M ¼ 16 and M ¼ 32 with prime values of φ to ensure a worst case error spur count. The M ¼ 16 spectra have been computed using a 64k point FFT and are therefore exact. In Section 4.3.4 we present analogous spectra for the linear phase interpolated case. For the M ¼ 32 spectra, we observe that the number of error spurs is greatly increased since F is now much larger (e.g. for I ¼ 12 and φ ¼ 519227 we have Λ ¼ 220). In general, we observe that the amplitude of the error spurs reduces with increasing I and each spectrum shows a different error spur distribution. For clarity, in Figure 4.18 we have omitted the circular spectrum line markers. Figure 4.19 shows the variation in SNR and SFDR with I for a phase truncated DDS with M ¼ 32. We use a prime number value of φ to ensure Λ ¼ 2F in all cases, and hence the maximum error spectrum energy for each value of I. In both cases the error spectrum power has been computed in the frequency domain with any residual fundamental component removed. We observe that both SNR and SFDR steadily improve with increasing I at around 6 dB/bit. We observe that I ¼ 17 (i.e. a 131 072 sample wavetable length) provides phase truncation SNR comparable with 16-bit amplitude quantisation noise.

4.3.3

Phase dithered wavetable indexing and noise shaping We now develop the ideas of phase dithering and noise shaping that were introduced in Section 4.1.7. Both of these operations modify the phase accumulator output sequence so as to decorrelate phase truncation errors from the fundamental signal. During wavetable lookup phase–amplitude mapping this decorrelation acts to significantly improve SFDR by suppressing DDS error spurs. We begin by considering phase dithering which is the simplest technique to implement arithmetically.

139


Amplitude (dBFS)

0

ϕ = 73 I = 10 M = 16

(a)

− 20 − 40

ϕ

− 60

2M

− 80 − 100 − 120 − 140

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 73 I = 12 M = 16

(b)

− 20 − 40

ϕ

− 60

2M

− 80 − 100 − 120 − 140

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 73 I = 14 M = 16

(c)

− 20 − 40

ϕ

− 60

2M

− 80 − 100 − 120 − 140

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 73 I = 16 M = 16

(d)

− 20 − 40

ϕ

− 60

2M

− 80 − 100 − 120 − 140

0

0.1

0.2

0.3

0.4

0.5

Normalised frequency f f s Figure 4.17 Phase truncated DDS amplitude spectra for four values of I with M ¼ 16 and a

prime value of φ to ensure Λ ¼ 2F in each case. We observe an optimal amplitude spectrum with no error spurs when I ¼ M and hence L ¼ 2M.


Amplitude (dBFS)

0

ϕ = 519227 I = 10 M = 32

(a)

− 20 − 40 − 60 − 80 − 100 − 120 − 140

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 519227 I = 12 M = 32

(b)

− 20 − 40 − 60 − 80 − 100 − 120 − 140

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 519227 I = 14 M = 32

(c)

− 20 − 40 − 60 − 80 − 100 − 120 − 140

0

0.1

0.2

0.3

0.4

0.5

0

Amplitude (dBFS)

140

ϕ = 519227 I = 16 M = 32

(d)

− 20 − 40 − 60 − 80 − 100 − 120 − 140

0

0.1

0.2

0.3

0.4

0.5

Normalised frequency f f s Figure 4.18 Phase truncated DDS amplitude spectra for four values of I with M ¼ 32 and a prime value of φ to ensure Λ ¼ 2F in each case. (The circular marker is only assigned to the fundamental signal for clarity.)

SNR (dB)

120

120

100

100

80

80

60

60

40

40

ϕ = 519227 M = 32

20 6

7

8

9

10

11

12

13

14

15

16

17

18

19

SFDR (dB)

141


20 20

φI (n) bits I Figure 4.19 Variation in SNR and SFDR with I for a phase truncated DDS.

fs

φ (n)

M

ϕ

∑

M

z-1

∑

I

Sine wavetable

DAC

y (t )

M F fs

Pseudo-random noise generator

ϑ (n)

Figure 4.20 Phase-dithered sinusoidal DDS. An F-bit pseudo-random sequence is added to ϕ(n) before truncation. Phase truncation now occurs at the output of the M-bit dither offset adder.

Truncation of the phase accumulator output sequence ϕ(n) from M to I bits introduces periodicities into the phase truncation error sequence that results in erroneous spurs in the DDS output spectrum whose amplitude and distribution are a function of M, I and φ as reported in [2]. Phase dithering adds a small pseudo-random sequence to ϕ(n) before the truncation operation and subsequent phase–amplitude mapping. We may represent the phase-truncated DDS sinusoid as an approximation to SM [ϕ(n)], thus:

2π F φn SM ½ϕðnÞ S M 2 þθ : ð4:39Þ 2 2F If we now add a uniformly distributed random sequence ϑ(n) to ϕ(n) before phase truncation as illustrated in Figure 4.20, the phase-truncated DDS sinusoid may be expressed as:

2π φn ϑðnÞ SM ½ϕðnÞ S M 2F F þ F þ θ , ð4:40Þ 2 2 2


Amplitude (dBFS)

0

ϕ = 67867967 I = 10 M = 32

(a)

− 20

fo =

− 40

ϕ 2M SFDR = -60 dB

− 60 − 80 − 100

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 67867967 I = 10 M = 32

(b)

− 20

fo =

− 40

ϕ 2M

− 60

SFDR = -75 dB

− 80 − 100

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 67867967 I = 12 M = 32

(c)

− 20

fo =

− 40

ϕ 2M

− 60

SFDR = -72 dB

− 80 − 100

0

0.1

0.2

0.3

0.4

0.5

0

Amplitude (dBFS)

142

ϕ = 67867967 I = 12 M = 32

(d)

− 20

fo =

− 40

ϕ 2M

− 60

SFDR = -86 dB

− 80 − 100

0

0.1

0.2

0.3

0.4

0.5

Normalised frequency f f s Figure 4.21 Amplitude spectra of normal and phase-dithered sinusoidal DDS for two values of I and a prime value of φ which gives the maximum Λ value in each case. Circular markers indicate the significant error spurs.

143


120

SNR (dB)

100 80 60 40 20

j = 519227 6

7

8

9

10

11

12

13

14

15

16

17

M = 32 18

19

20

fI (n) bits I Figure 4.22 Simulated SNR variation with I for the phase dithered sinusoidal DDS architecture shown in Figure 4.20.

and it is shown in [8] that the residual phase truncation errors are now completely decorrelated with the phase increment φ and take on a quasi-noise form. The phase dithered DDS sinusoid may now be expressed as:

2π SM ½ϕðnÞ ¼ S M φn þ θ þ εðnÞ , ð4:41Þ 2 which describes an ideal discrete-time sinusoid with an additional phase error term ε(n) that is uniformly distributed on the interval [Δ/2, Δ/2) where Δ ¼ 2π/2I. Accordingly, the F-bit pseudo-random dither sequence ϑ(n) is uniformly distributed on [Δ0 /2, Δ0 /2) where Δ0 ¼ 2I. Figure 4.21 shows simulated amplitude spectra before and after the application of phase dithering for a phase truncated sinusoidal DDS as shown in Figure 4.20. We show two I values with prime values of φ to give the maximum spur count Λ in each case. Elimination of the discrete amplitude error spurs leading to improved SFDR and decorrelation of the original discrete error spectrum are dramatically illustrated. The phase dithered spectra show a pseudo-random residual noise floor and a significant improvement in SFDR of around 15 dB, which is independent of the two I values used. We observe that the mean noise floor level after phase dithering increases slightly in both cases as expected. Summarising analysis reported in [6], the maximum and minimum SNR of the phase dithered DDS sinusoid is given by: SNRmax ¼ 6:02I 6:93 dB, SNRmin ¼ 6:02I 8:18 dB:

ð4:42Þ

Equation (4.42) is in exact agreement with the simulated phase dithered SNR variation with I illustrated in Figure 4.22. We now consider so-called noise shaping as reported in [5], which incorporates a digital high- filter within the phase truncation operation. Figure 4.23 illustrates a typical noise shaping sinusoidal DDS architecture that includes a first-order noise shaper between the phase accumulator and wavetable. The noise shaper takes the form of a

144


fs

ϕ

φ (n)

M ∑

M

z-1

φˆ(n) ∑

M

I

φˆ (n)

Sine wavetable

DAC

y (t )

I

M F

F z-1

φˆF (n)

fs Figure 4.23 A sinusoidal DDS with first-order noise shaping.

second M-bit accumulator fed from the output of the frequency synthesising phase ^ accumulator ϕ(n). The output of the noise shaping accumulator ϕðnÞ is truncated into ^ ^ integer and fractional phase components ϕ I ðnÞ and ϕ F ðnÞ, respectively. The fractional ^ component ϕ^F ðnÞ is fed back and accumulated with ϕ(n) modulo 2M to compute ϕðnÞ, ^ with the integer component ϕ I ðnÞ indexing the wavetable. The first-order noise shaper implements a digital high- filter that suppresses any low frequency phase truncation noise present in the truncated phase sequence. This processing decorrelates phase truncation errors that cause discrete error spurs in the amplitude spectrum and suppresses phase noise impairments close to the programmed frequency in a high- manner. Figures 4.24a and 4.24c illustrate typical DDS amplitude spectra without noise shaping when synthesising low and medium frequency sinusoids. Figures 4.24b and 4.24d illustrate the corresponding noise shaped spectra. The low frequency noise shaped spectrum clearly shows high- noise suppression in the vicinity of the synthesised signal. The high- noise suppression is reduced although still evident when synthesising a higher frequency sinusoid as shown in Figure 4.24d. Both noise shaped spectra clearly demonstrate the complete suppression of discrete error spurs and thereby a significant improvement in SFDR at the expense of a small elevation in the mean noise floor. Higher-order sinusoidal DDS noise shaping is reported in [9].

4.3.4

Linear phase interpolated wavetable indexing In Section 4.1.4 we introduced the concept of linearly interpolated fractional addressing and outlined its application to sinusoidal DDS as shown in Figure 4.9. A wavetable with L ¼ 2I tabulated sinusoid values is indexed by the phase truncated sequences ϕI (n) and ϕI(n) þ 1 to produce the amplitude samples that we denote by S ϕI ðnÞ and S hϕI ðnÞ þ 1i2I . The ideal sample (i.e. where L ¼ 2M) that we denote by SM[ϕ(n)] is therefore approximated by the linear phase interpolation given by: ð4:43Þ SM ϕðnÞ S ϕI ðnÞ þ α S hϕI ðnÞ þ 1i2I S ϕI ðnÞ ,


Figure 4.24 Amplitude spectra of normal and noise shaped sinusoidal DDS using two prime values of φ corresponding to low and medium frequencies. Circular markers indicate the significant error spurs in the non-noise-shaped spectra.

145


Amplitude (dBFS)

0

j = 262 I = 6 Λ = 32 M = 12

(a)

− 20 − 40 − 60 − 80 − 100 − 120

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

j = 268 I = 6 Λ = 16 M = 12

(b)

− 20 − 40 − 60 − 80 − 100 − 120

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

j = 280 I = 6 Λ = 8 M = 12

(c)

− 20 − 40 − 60 − 80 − 100 − 120

0

0.1

0.2

0.3

0.4

0.5

0

Amplitude (dBFS)

146

j = 304 I = 6 Λ = 4 M = 12

(d)

− 20 − 40 − 60 − 80 − 100 − 120

0

0.1

0.2

0.3

0.4

0.5

Normalised frequency f /fs Figure 4.25 Amplitude spectra for a simple linear phase interpolated DDS with φ chosen to illustrate four values of Λ. These spectra are analogous to those presented in Figure 4.16 for the phase truncated case.


147

Figure 4.26 Amplitude spectra for a linear phase interpolated DDS with M ¼ 16 and two values of I. These spectra correspond with those shown in Figure 4.17 for the phase truncated case, and reveal significantly improved performance as measured by error spur amplitude and hence SFDR.

where α ¼ ϕF (n)/2F and is the fractional phase address ϕF(n) interpreted as a rational number bound on the interval [0, 1). The modulo operator in the wavetable function argument is necessary since the wavetable address is only defined on the interval [0, 2I 1]. The wraparound behaviour of an unsigned binary adder used to offset the ϕI (n) term in a hardware implementation imposes this operation. It is evident that linear phase interpolation indexing operations associated with requires two wavetable obtaining the S ϕI ðnÞ and S hϕI ðnÞ þ 1i2I operands and one multiplication operation. The number of addition and subtraction operations varies between two and three depending on the implementation method. The signal-flow corresponding to this expression is illustrated in Figure 4.9, where it is assumed that the wavetable can supply these operands simultaneously when indexed by ϕI (n). We consider detailed implementation of linear phase interpolated wavetable indexing in Chapter 8. Figure 4.25 shows a collection of linear phase interpolated amplitude spectra with M ¼ 12 and I ¼ 6. Non-prime values of φ have been chosen to give spectra with Λ ¼ 32, Λ ¼ 16, Λ ¼ 8 and Λ ¼ 4 according to Eq. (4.28). Since 2F ¼ 64, i.e. relatively small, the error spurs are few in number and therefore clearly visible. These spectra correspond exactly with the phase truncated amplitude spectra of Figure 4.16.

160

160

140

140

120

120

100

100

80

ϕ = 519227 M = 32

60 6

7

8

9

10

11

12

SFDR (dB)


SNR (dB)

148

80 60 13

φI (n) bits I Figure 4.27 Variation in SNR and SFDR with I for a linear phase interpolated DDS.

We observe a significant reduction in error spur magnitude and therefore a corresponding improvement in SFDR compared to the phase truncated case. Figure 4.26 shows two linear phase interpolated amplitude spectra with M ¼ 16 that have been computed with 64k point FFTs and are therefore exact representations of the discrete spectrum. The prime value of φ corresponds to a low frequency sinusoid. Figure 4.26a shows the amplitude spectrum for I ¼ 10 and Figure 4.26b for I ¼ 12. These spectra correspond exactly with those for the phase truncated case shown in Figure 4.17a and 4.17b and reveal significantly lower error spur amplitude, which improves with increasing I as expected. For I ¼ 10, error spur amplitude is approximately 60 dB lower than the corresponding phase truncated case, improving to approximately 85 dB lower when I ¼ 12. Figure 4.27 shows the variation in SNR and SFDR with I for a linear phase interpolated DDS with M ¼ 32. We use a prime number value of φ to ensure Λ ¼ 2F and hence the maximum error spectrum energy for each value of I. In both cases the error spectrum power has been computed in the frequency domain with any residual fundamental component removed. Figure 4.27 corresponds with Figure 4.19 for the phase truncated case. We observe that both SNR and SFDR steadily improve with increasing I at around 12 dB/bit. We now only require I ¼ 9 (i.e. a 512 sample wavetable length) to provide phase truncation SNR comparable with 16-bit quantisation noise.

4.3.5

Trigonometric identity phase interpolation In this section we investigate use of trigonometric identities to significantly reduce wavetable memory requirement while providing optimal sinusoidal phase–amplitude mapping which uses all 2M phase accumulator states. Observing that the phase sequences ϕI(n) and ϕF(n) combine according to Eq. (4.19) to form the non-truncated sequence ϕ(n) motivates consideration of the angle summation trigonometric identities to implement an optimally interpolated phase–amplitude mapping operation.


149

The angle summation identities for two angles A and B are given by: sinðA þ BÞ sinðAÞ cosðBÞ þ cosðAÞ sinðBÞ,

ð4:44Þ

cosðA þ BÞ cosðAÞ cosðBÞ sinðAÞ sinðBÞ:

ð4:45Þ

From Eqs. (4.13) and (4.15) we decompose the phase accumulator sequence ϕ(n) expressed in radian form, thus: j k 2π j k 2π 2π F ϕðnÞ F ϕðnÞ þ M ϕðnÞ 2 ϕðnÞ ¼ M 2 2M 2 2F 2 2F ¼

2π 2π I ϕI ðnÞ þ M ϕF ðnÞ: 2 2

ð4:46Þ

We can now define an optimal sinusoidal phase–amplitude mapping function by making the substitutions (A þ B) ¼ (2π/2M)ϕ(n), A ¼ (2π/2I)ϕI (n) and B ¼ (2π/2M)ϕF (n) into Eqs. (4.44) and (4.45) to obtain: 2π 2π 2π ϕI ðnÞ cos ϕF ðnÞ sin M ϕðnÞ ¼ sin 2 2I 2M 2π 2π þ cos ϕ ðnÞ sin ϕ ðnÞ , I F 2I 2M

2π 2π 2π cos M ϕðnÞ ¼ cos ϕI ðnÞ cos ϕF ðnÞ 2 2I 2M 2π 2π sin ϕ ðnÞ sin ϕ ðnÞ : I F 2I 2M

ð4:47Þ

ð4:48Þ

This mapping is exact since the identities are themselves exact (by definition) and no phase information is discarded. The left-hand sides of Eqs. (4.47) and (4.48) represent ideal discrete-time quadrature sinusoid signals with phase argument ϕ(n) defined in of ϕI (n) and ϕF (n). Figure 4.28 illustrates the corresponding arithmetic process model where four wavetables indexed by ϕI (n) and ϕF (n) generate the sine and cosine . Arithmetic overhead comprises four wavetable lookup operations, four multiplications, one addition and one subtraction to compute the quadrature sinusoid samples. We observe that a single sinusoid requires the same four wavetable lookup operations, two multiplications and one addition operation. The four wavetable functions are defined thus: 9 2π > W1 ½a ¼ cos a > > > = 2I a 2 ½0, 2I 1, ð4:49Þ 2π > > > a W2 ½a ¼ sin > ; 2I

150


Cosine wavetable W1

∏

φI (n)

I

Sine wavetable W2

∑

⎛ 2π ⎞ sin ⎜ M φ (n) ⎟ ⎝2 ⎠

∑

⎛ 2π ⎞ cos⎜ M φ (n) ⎟ ⎝2 ⎠

∏

φ (n)

F

∏

Cosine wavetable W3

+ −

φF (n)

∏

Sine wavetable W4

Figure 4.28 Arithmetic process model for quadrature trigonometric phase mapping as defined by Eqs. (4.47) and (4.48).

9 2π > > a > > = 2M 2π > > W4 ½a ¼ sin a > > M ; 2

W3 ½a ¼ cos

a 2 ½0, 2F 1:

ð4:50Þ

Wavetables W1 and W2 tabulate exactly one cycle of the cosine and sine functions over 2I samples, respectively. However, wavetables W3 and W4 tabulate the cosine and sine functions on the phase interval [0, 2π(2F 1)/2M] radians, respectively (i.e. only 2I of one cycle). Total wavetable memory requirement is therefore 2Iþ1 þ 2Fþ1 samples representing a significant reduction on the ‘brute force’ implementation requiring 2M samples, particularly when M is large. For example, with M ¼ 32, the brute force approach requires a wavetable with 232 samples, whereas this approach requires only 218 samples. Optimum wavetable memory saving occurs when the phase word is partitioned equally and all four lookup tables are each M/2 samples long. The total memory requirement is then 22þM/2 samples representing a reduction of 22M/2 compared to the brute force approach and improves exponentially as M increases. For large M, the total wavetable memory requirement becomes impractically large and our only option is to truncate ϕ(n) by R bits to M R bits and assign the ϕI (n) and ϕF (n) fields equally with I ¼ F ¼ (M R)/2. The value of R is chosen according to applicationspecific hardware constraints.


151

Figure 4.29 Amplitude spectrum for a trigonometric identity phase interpolation with M ¼ 32. Amplitude samples and signal processing paths have been quantised to 24-bits.

Figure 4.30 Variation in SNR and SFDR with R for trigonometric identity phase interpolation.

Figure 4.29 shows the amplitude spectrum corresponding to a trigonometric identity phase interpolation with M ¼ 32 and a prime φ value where the wavetable samples and amplitude signal processing paths have been quantised to 24-bits. The amplitude spectrum has been computed with a 64k point FFT and is consistent with 24-bit quantisation noise with no phase truncation spurs present. Figure 4.30 shows the variation in SNR and SFDR with R for trigonometric identity phase interpolation with M ¼ 32 and a prime value of φ. We therefore have I ¼ F ¼ (M R)/2 and hence Λ ¼ 2R. The simulation has been performed with full floating point precision to reveal SNR degradation due to phase truncation errors alone. For R ¼ 0, SNR is comparable with the floating point noise floor at around 350 dB. Since the angle summation formulae are mathematical identities and therefore absolutely exact, we conclude that trigonometric identity phase interpolation provides optimum SNR and SFDR bound only by sample quantisation noise and arithmetic round-off errors. Performance is therefore defined entirely by the DAC and subsequent

152


analogue processing stages (i.e. digital arithmetic errors are negligible at all frequencies). However, this technique only provides optimum SNR and SFDR when all M phase bits are used and so R ¼ 0. M is always constrained to be sufficiently small so that the corresponding total wavetable memory requirement of 22þM/2 samples is practicable in a particular application technology. When R > 0, linearly interpolated phase–amplitude mapping using an equivalent wavetable length 2(M R)/2 provides very similar performance to the trigonometric identity phase interpolation case. We conclude that trigonometric identity phase interpolation is only of utility when R ¼ 0 and we require absolutely exact discrete-time quadrature sinusoids. In Chapter 8 when we consider hardware implementation, we present a reduced-multiplier form of the trigonometric identity phase interpolation algorithm that incurs no loss of accuracy. In Section 4.3.6 we outline techniques for reducing wavetable memory overhead when tabulating sinusoidal functions. These techniques are based upon a completely lossless technique that exploits the quadrant symmetry of the sine function and reduces wavetable memory fourfold in its simplest form.

4.3.6

Sinusoidal wavetable compression The sine function is defined on the phase domain [0, 2π) and is periodic with a period of 2π radians. It exhibits an exact quarter-wave symmetry allowing a complete cycle to be ‘constructed’ by reflecting and translating only the first quarter cycle or quadrant corresponding to the phase interval [0, π/2). For a discrete value x, we can therefore compute sin(x) for any x 2 [0, 2π) without any loss of precision by using simple arithmetic and a wavetable which tabulates the first quadrant on [0, π/2) to a particular level of phase quantisation. The method by which we implement this lossless compression technique in hardware is very simple. We first partition the phase truncated sequence ϕI (n) into a 2-bit ‘quadrant index’ and an I 2 bit wavetable phase index, which spans the interval [0, 2I 2 1] and corresponds to the radian phase interval [0, π/2). The two most significant bits (MSB) of ϕI(n) provide the quadrant index. The MSB denotes the sign of the sinusoid and the second MSB denotes whether the sine amplitude is increasing or decreasing with phase index (i.e. positive or negative amplitude slope). The remaining I 2 ϕI (n) least significant bits define the wavetable phase index. Figure 4.31 shows a schematic of the signal flow where the ϕI (n) MSB controls the arithmetic inversion of the wavetable output samples and the second MSB controls the inversion of the I 2 bit wavetable phase index to set amplitude output slope. If the first quadrant wavetable is not tabulated correctly there is a subtle error mechanism that causes significant distortion in the synthesised sine wave, particularly if the wavetable length is small. Figure 4.32a shows the full cycle phase progression for a hypothetical 16 point sinusoid tabulation (i.e. I ¼ 4) where the circular arrangement represents one full cycle of 2π radians. This corresponds to an uncompressed sine wavetable representation where a complete cycle is tabulated. We observe that all four quadrants are symmetric with respect to each other and there is a regular phase spacing

153


MSB 2 −1 I

MSB − 1

0

I −2

φ I (n)

φI − 2 ( n )

2I −2 − 1 0

1's complement

2I −2 − 1 0

I −2

First quadrant sine wavetable

b −1

2's complement

1 0

b

y (n)

1

−1

Figure 4.31 Sine wavetable compression exploiting quarter-wave symmetry.

between all phase points. However, Figure 4.32b shows the phase progression that is produced when only the first four phase points are tabulated and the others around the circle are formed by appropriate reflection and translation operations. We tabulate the first quadrant sine wavetable with the address a now spanning the reduced interval a 2 [0, 2I2 1]. Two errors are immediately apparent – the 0 and π phase points are repeated and there are no distinct π/2 or 3π/2 phase points. The corresponding effect on the amplitude waveform is shown in Figure 4.32c where a zero-crossing discontinuity is evident and there are no amplitude points for phase values of π/2 or 3π/2. If uncorrected, both of these conditions cause distortion of the resultant sine signal leading to error spurs in the amplitude spectrum. The zero-crossing distortion leads to a significant 2nd harmonic spur. These phase–amplitude mapping errors are completely eliminated if we add a ½ LSB offset (i.e. 2π/2Iþ1) to the argument of the sine wavetable tabulation as reported in [4] and developed further in [10]. The corresponding phase progression is illustrated in Figure 4.32d and indicates reflective symmetry between all quadrants as required with regularly spaced phase points. However, we now have a fixed 2π/2Iþ1 radian phase offset imposed on the synthesised sinusoid and no distinct tabulation of the 0, π/2, π and 3π/2 phase points. In a typical hardware implementation, signal samples are represented using a 2’s complement signed format. The quarter-wave tabulated sinusoid is unsigned (i.e. positive only) and its amplitude samples are represented with b 1 bits assuming a final signed 2’s complement representation of b-bits. The architecture depicted in Figure 4.31 requires two controlled complementors – one to control wavetable indexing and the other to invert the sine amplitude sample during the negative half of the cycle. The signed 2’s complement output samples are therefore represented with b bits. Assuming the phase index ϕI(n) is unsigned, the wavetable indexing complementor can be a simple 1’s complementor comprising only exclusive-OR gates which are simple to implement in hardware. However, the wavetable output complementor must handle 2’s complement representation, which requires an inversion and add operation. Nicholas et al. [4] also report that adding a ½ LSB offset to the sine amplitude values before quantisation

154


(a)

(b) 4

5

4

3

π

6

5

2

2

7

π

8

0

9

11

0

9

14

12

1

π

7

15

0

14

3π 2

10

13

13 12

11

4

3

(c)

8

15

3π 2

10

0

2

2

6

1

3

π

5

2 1

6

0

7

8

15 14

9 13

10 11

12

(d) 4 5

3 2

π

6

1

2

7

0

π

π 16

0

8

→

2π 2 I +1

15

3π 2

9 10 11

14 13 12

Figure 4.32 Full cycle and quadrant wavetable indexing representations: (a) Ideal full cycle tabulation; (b) Quadrant indexing with non-optimal tabulation; (c) Corresponding amplitude signal; (d) Optimal quadrant indexing. (Shaded points indicate tabulated values.)


155

and tabulation in the wavetable allows the output 2’s complementor in Figure 4.31 to be replaced by a simple 1’s complementor without introducing an error. Several techniques for compressing the first quadrant wavetable itself are reported in the literature. Reference [10] provides a useful summary of wavetable compression techniques and several design case studies of sinusoidal DDS ASIC implementations. The principal motivator is optimisation of on-chip lookup table memory utilisation with error spectrum performance. All of the reported techniques are not lossless and exploit an underlying approximation which allows a trade-off between wavetable memory utilisation and error performance at the expense of further arithmetic processing. A typical optimisation is to ensure that phase truncation errors are comparable with amplitude quantisation noise for a given size of wavetable memory.

4.3.7

Direct computation phase–amplitude mapping – the CORDIC algorithm Finally, we investigate an important direct computation phase–amplitude mapping algorithm that is not based upon a wavetable, although a small coefficient lookup table is required. The CORDIC (COordinate Rotation DIgital Computer) uses a convergent iteration process to compute the rotation of a vector in a Cartesian coordinate system. Among many other arithmetic processes, the CORDIC can simultaneously compute the sine and cosine of a phase argument in exact quadrature. The technique was first presented by Volder [11] in connection with efficient bit-serial airborne computation and later unified by Walther [12]. The principal advantage of the CORDIC algorithm is the simplicity of its constituent arithmetic processes, which lend themselves to efficient hardware implementation. Being a fundamentally iterative process, the algorithm incurs an increase in processing time. However, in a hardware implementation this is mitigated by fast arithmetic stages within a pipelined architecture optimised for latency and power consumption performance. The CORDIC method is based on the simple observation that a unit length vector ½ 1 0 T rotated by an angle θ has an end point defined by the vector ½ cosðθÞ sinðθÞ T . The CORDIC transformation is computed over m iterative steps, each involving a ‘partial rotation’ by some fraction of the argument θ. In general, the rotation of a vector ½ x0 y0 T by an angle θ in Cartesian coordinates produces after m iterations the vector ½ xm ym T , and can be represented by the matrix operation:

cosðθÞ sinðθÞ x0 xm ¼ : ð4:51Þ ym y0 sinðθÞ cosðθÞ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Using the trigonometric identity cosðθÞ ¼ 1= 1 þ tan2 ðθÞ, Eq. (4.51) can be expressed in an alternative form, whose relevance will become apparent shortly:

1 1 tanðθÞ x0 xm ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi : ð4:52Þ 1 ym y0 1 þ tan2 ðθÞ tanðθÞ In the CORDIC algorithm, rotation by θ is implemented by a number of partial rotations each of which we denote by αi, where i ¼ 0, 1, 2, . . . m. Any angle θ within

156


a defined interval can be represented to a particular accuracy by a weighted sum of m partial angles αi each with unitary weights σi 2 {1, 1}, thus: θ¼

m1 X

σ i αi :

ð4:53Þ

i¼0

The magnitude of the αi decreases with increasing index i. The initial αi values are weighted positively until the sum exceeds θ, whereupon the αi values are negatively weighted until the sum falls below θ. This process is repeated for m iterations in a convergent manner until a specified accuracy threshold is reached. The sign of the difference between θ and the sum given by Eq. (4.53) controls the value of σi. Clearly, selection of the αi values is central to the CORDIC algorithm. The partial angles αi are chosen according to the relationship: tanðαi Þ ¼ 2i ,

i ¼ 0, 1, 2, 3, . . . m 1,

ð4:54Þ

and hence αi ¼ tan1 (2i). An auxiliary variable zi represents the accumulated partial angles and is used to control the value of σi. As m increases, zi converges to 0. For z0 ¼ θ we therefore have the difference equation and conditional definition of σi: ziþ1 ¼ zi σ i tan1 ð2i Þ, þ1 zi 0, σi ¼ 1 zi < 0

ð4:55Þ

where i ¼ 0, 1, 2, . . . m. In a hardware implementation, the zi difference equation is part of the iterative arithmetic control mechanism. The CORDIC rotation is not a pure rotation but a rotation–extension since the magnitude (i.e. length) of the rotated vector increases as the iterative rotation proceeds. This requires introduction of a scaling factor to keep the vector at constant magnitude. Equation (4.52) can now be written as the matrix difference equation:

xiþ1 1 σ i 2i xi ¼ ki , ð4:56Þ yiþ1 yi σ i 2i 1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi where the scaling factor ki is given by k i ¼ 1= 1 þ 22i and can be generalised for m iterations to a fixed value given by: k¼

m1 Y i¼0

1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi, 1 þ 22i

ð4:57Þ

and we observe that k approaches a limiting value of approximately 0.607253 as m ! ∞. We can therefore move the ki scaling operations to the end of the iteration process, combining them into a single multiplication by k according to Eq. (4.57). The CORDIC algorithm may now be expressed by the difference equations (without the ki scaling term), thus:


xiþ1 ¼ xi σ i 2i yi , yiþ1 ¼ yi þ σ i 2i xi , ziþ1 ¼ zi σ i tan1 ð2i Þ,

157

ð4:58Þ

where i ¼ 0, 1, 2, . . . m, and z0 ¼ θ, the input phase argument. We observe that Eqs. (4.58) only require add, subtract and arithmetic bit shift operations. A small tablelookup operation provides each tan1(2i) value. The principal advantage of the CORDIC algorithm arises from the fundamental simplicity of these operations, particularly when considering VLSI or FPGA implementation. After m iterations, the xm and ym values given by Eqs. (4.58) must be multiplied by k to give the correct result, thereby involving a costly multiply operation. Alternatively, selecting the initial condition values x0 ¼ k, y0 ¼ 0 and z0 ¼ θ, eliminates this multiply operation, yielding xm ¼ cos(θ) and ym ¼ sin(θ) after m iterations. This process is illustrated in Figure 4.33, which shows a simulated computation of θ ¼ sin(π/8) using a CORDIC algorithm over 12 iterations. The error sequence is also shown on a logarithmic scale showing that the error decreases exponentially with i. The CORDIC algorithm remains convergent on the interval θ 2 [r, r], where ∞ X r¼ tan1 ð2i Þ 1:743286 . . . radians. For arithmetic convenience, we take the i¼0

region of convergence as [π/2, π/2], observing that the CORDIC algorithm can process negative phase arguments. The CORDIC vector rotation maps from the phase to the amplitude domain with an accuracy determined only by the number of iterations (assuming we for arithmetic word growth and quantisation effects in the implementation). Since tan1(2i) ! 2i as i ! ∞, we conclude that b bits of amplitude precision can be obtained in b iterations. The CORDIC algorithm is not a ‘synthesis from scratch’ technique and requires prior computation of a truncated phase argument ϕI(n) using a phase accumulator to effect frequency synthesis. The input argument is the initial condition z0 and assumes a radian scaling on the interval [π/2, π/2] by default. Phase–amplitude mapping is therefore accomplished in a similar manner to the quarter-wave indexing described in Section 4.3.6 and illustrated in Figure 4.31. In essence, the CORDIC algorithm replaces the first quadrant sine wavetable in Figure 4.31 and the surrounding index and amplitude sample complementing blocks remain unchanged. If we assume an unsigned input phase sequence ϕI (n), the CORDIC algorithm is initialised with the I 2 LSBs of ϕI (n) which span the interval [0, 2I2 1] and correspond to the phase interval [0, π/2) radians. Equation (4.55) must now be modified to ensure that ϕI (n) ¼ 2I2 1 corresponds to π/2, thus: I 2 tan1 ð2i Þ, ziþ1 ¼ zi σ i 2π ð4:59Þ þ1 zi 0 , σi ¼ 1 zi < 0 with z0 ¼ ϕI(n). The z term in Eqs. (4.58) must also be modified accordingly.

158


0.75

xi +1 = xi − σ i 2 −1 yi yi +1 = yi + σ i 2 −1 xi

0.5

yi 0.25

0 0

1

2

3

4

5

6

7

8

9

10

11

12

0.5

zi +1 = zi − σ i tan −1 (2 − i ) 0.25

zi

0 − 0.25 − 0.5 0

1

2

3

4

5

6

7

8

9

10

11

12

1

⎛

ε i = log ⎜⎜ xi − sin

0.1

εi

⎝

π ⎞ ⎟ 8 ⎟⎠

0.01

0.001

0.0001 0

1

2

3

4

5

6

7

8

9

10

11

12

i Figure 4.33 An example of the CORDIC algorithm computing sin(π/8) over 12 iterations. The plot shows the x value converging to sin(π/8) and the auxiliary z variable converging to zero as the iteration proceeds.

The ½ LSB phase offset (i.e. 2π/2Iþ1) described in Section 4.3.6 to eliminate the quadrant mapping errors illustrated in Figure 4.32 is imposed by setting the CORDIC initial conditions accordingly. The initial conditions are defined by: ðx0 , y0 Þ ¼ ðk cosðθ0 Þ, k sinðθ0 ÞÞ,

ð4:60Þ

where θ0 denotes the initial phase when ϕI(n) ¼ 0 and k is predefined according to the number of iterations to be used in the implementation. Setting θ0 ¼ 2π/2Iþ1 provides the required ½ LSB phase offset.

4.4 Summary

159

Goldberg [13] reports that the principal advantage of CORDIC phase–amplitude mapping over wavetable techniques is its inherent quadrature outputs. Madisetti, Kwentus and Willson [14] describe a novel quadrature DDS which uses CORDIC phase–amplitude mapping based upon a sequential pipelined architecture. Additional background and tutorial material can be found in [15].

4.4

Summary In this chapter we have investigated sinusoidal DDS, beginning with the ideal case where all phase accumulator states are uniquely mapped to a sine wave amplitude value. Assuming a wavetable based phase–amplitude mapping operation, this corresponds to a wavetable comprising 2M locations. Neglecting amplitude quantisation effects, this condition generates ideal discrete-time sinusoids with no error spurs in the amplitude spectrum due to the phase accumulation process. SNR and SFDR are determined entirely by quantisation noise. Although this method is practicable for small values of M (e.g. M ¼ 16 implies a relatively small wavetable of 65 536 samples), it becomes increasingly impracticable as M becomes large. For a given sample frequency, large values of M enable high resolution frequency control. We have investigated the concept of phase truncation (or, equivalently, phase quantisation) to reduce the wavetable size to practicable levels at the expense of introducing a new error mechanism. Accordingly, the phase–amplitude mapping ‘space’ now comprises considerably less than 2M states, and so some phase states must be approximated to the same amplitude value. This introduces distortion in the synthesised waveform and hence corresponding error spurs in the amplitude spectrum. We have graphically illustrated both the time and frequency domain characteristics of the phase truncation error using a simple DDS architecture contrived to highlight the principal effects. The size of the truncated phase–amplitude mapping space, and hence wavetable length, is determined by the number of bits truncated from the phase accumulator output word. The nature of phase truncation suggests a fractional phase representation and the idea of fractionally addressing a wavetable through phase interpolation. The phase accumulator output is now viewed as a fixed-point fractional quantity comprising an integer and fraction field. After reviewing linear interpolation of a tabulated data set to estimate a non-tabulated value at a fractional location, we outline its specific application to sinusoidal DDS wavetable indexing. Hardware implementation is discussed in Chapter 8. We have discussed both static and dynamic phase offset in a DDS system and presented techniques for generation of quadrature and polyphase sine signals with adjustable phase error. The concept of phase domain processing has been introduced, and the permissible arithmetic operations and their bounding conditions have been summarised. In the context of this chapter, phase domain processing generalises the specific phase–amplitude mapping processes of phase dithering and noise shaping. Both of these error-mitigation measures are applied entirely in the phase domain and provide improved SFDR compared to simple phase truncated wavetable indexing.

160


In Section 4.2 we have summarised important theoretical analysis of sinusoidal DDS phase truncation errors reported in the literature and presented a generalised DDS error model that sets the various error mechanisms in context. This model formalises the principal error mechanisms from the DDS phase increment ‘input’ parameter to the continuous-time, sine wave output from the post-DAC reconstruction filter. The key results of this analysis allow selection of design and control parameter values that visualise particular properties or worst case behaviour through computer simulation. Finally, we have summarised DDS SNR due to two ‘amplitude-specific’ parameters – the number of bits used to represent the amplitude samples pffiffiffi and waveform crest factor. In the sinusoidal case, the crest factor is fixed at 2 and so quantisation SNR is determined solely by the number of amplitude bits. However, this consideration is important when we investigate generation of non-sinusoidal arbitrary waveforms whose pffiffiffi crest factor can be considerably greater than 2. The effects of DAC full-scale headroom and oversampling ratio on SNR have been discussed, as these are fundamental to all phase–amplitude mapping algorithms. In the case of oversampling, we have shown that a significant improvement in SNR can be realised at the expense of reduced synthesis bandwidth compared to the critically sampled case. Oversampling provides a simple and effective trade-off during system optimisation at the expense of reduced synthesis bandwidth. In Section 4.3 we have presented simulated performance results for several sinusoid phase–amplitude mapping algorithms under various conditions. The amplitude spectrum, SNR and SFDR metrics allow a qualitative comparison of performance to be made. The results confirm that increasing wavetable size yields improved performance in all cases. Linear phase interpolation is shown to provide significantly improved performance compared to simple phase truncated wavetable indexing for the same wavetable length. Phase dithering and noise shaping provide improved SFDR performance compared to simple phase truncated wavetable indexing for the same wavetable length, and require simpler arithmetic operations than linear phase interpolation. However, SNR performance is essentially unchanged due to the additive dither signal and decorrelation of the error spurs into pseudo-noise typical of noise shaping. The novel concept of trigonometric identity phase interpolation has been introduced and shown to provide optimal phase–amplitude mapping with significantly reduced memory overhead compared to the brute force case. However, practicable application of this technique is still constrained by the size of M. A simulated implementation of this algorithm using 24-bit fixed-point arithmetic and M ¼ 32, reveals SFDR and SNR comparable with the quantisation noise limit with no phase truncation spurs evident in the amplitude spectrum. We have reviewed a lossless wavetable compression technique that exploits the inherent quarter wave symmetry of the sine wave and is applicable to all sinusoidal wavetable applications to reduce memory overhead. Wavetable length is now reduced by 75% compared to a full cycle tabulation, at the expense of some relatively simple arithmetic operations. Of course, wavetable lookup is not the only sinusoidal phase– amplitude mapping technique. Direct computation is also practicable using a variety of algorithms of which one of the most widely reported is the CORDIC algorithm that has

4.5 References

161

been described in some detail. Useful literature references for other direct computation techniques have also been provided. This chapter has focused on sinusoidal DDS where the phase–amplitude mapping operation is based upon wavetable indexing and augmented by phase dithering or linear phase interpolation. In addition to being useful in its own right, this material provides suitable preparation for the general case of arbitrary waveform DDS that we consider in Chapter 5.

4.5

References 1. F. R. Moore, Elements of Computer Music. Prentice-Hall, Inc, 1990. 2. H. T. Nicholas and H. Samueli, An analysis of the output spectrum of DDFS in the presence of phase-accumulator truncation, 41st Annual Frequency Control Symposium, pp. 495–502, 1987. 3. S. J. Orfanidis, Introduction to Signal Processing. Prentice-Hall, Inc, 1996. 4. H. T. Nicholas, H. Samueli and B. Kim, The optimization of DDFS performance in the presence of finite word length effects, 42nd Annual Frequency Control Symposium, pp. 357–363, 1988. 5. J. A. Crawford, Frequency Synthesizer Design Handbook, Artech House, Inc, 1994. 6. J. Vankka, Direct Digital Synthesisers: Theory, Design and Applications, PhD Thesis, Helsinki University of Technology, 2000. 7. U. Zőlzer, Digital Audio Signal Processing, Wiley, 1997. 8. L. Schuchman, ‘Dither signals and their effects on quantisation noise’, IEEE Transactions on Communications, Vol. COM-12, pp. 162–165, December 1964. 9. J. Vankka, ‘Direct digital synthesiser with tunable phase and amplitude error structures’, IEE Proceedings Circuits, Devices and Systems, 151, (6), pp. 529–535, 2004. 10. J. Vankka, ‘Methods of mapping from phase to sine amplitude in direct digital synthesis’, IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 44, No. 2, pp. 526–534, March 1997. 11. J. Volder, ‘The CORDIC trigonometric computing technique’, IRE Transactions on Electronic Computing, Vol. EC-8, September 1959. 12. J. Walther, A unified algorithm for elementary functions, t Computer Conference Proceedings, Vol. 38, pp. 379–385 Spring 1971. 13. Bar-Giora Goldberg, Digital Frequency Synthesis Demystified – DDS and Fractional-N PLLs. LLH Technology Publishing, 1999. 14. A. Madisetti, A. Y. Kwentus and A. N. Willson, ‘A 100-MHz, 16-bit direct digital frequency synthesiser with a 100-dBc spurious-free dynamic range’, IEEE Journal of Solid-State Circuits, Vol. 34, No. 8, August, 1999. 15. V. F. Kroupa, Direct Digital Frequency Synthesizers, IEEE Press, 1999.

5


5.1

From sinusoidal to arbitrary waveforms In Chapter 4 we investigated sinusoidal DDS and developed the concept of phase– amplitude mapping using a wavetable. In sinusoidal DDS, the wavetable is a lookup table that tabulates one cycle of a sine function and translates from the phase domain to the amplitude domain. In this chapter we extend this idea to the generation of nonsinusoidal waveforms where a single-cycle, periodic arbitrary waveform function is now tabulated in the wavetable. We call this method DDS arbitrary waveform generation or DDS AWG. DDS AWG is a generalisation of sinusoidal DDS that generates arbitrary waveforms with fixed waveshape and independently controlled frequency, phase offset and amplitude. Furthermore, DDS also allows independent dynamic modulation of these parameters according to a modulation waveform. However, the signal processing structure of DDS AWG is easily modified to provide smooth, parametrically controlled (i.e. time-varying) waveshape and corresponding spectrum. We consider dynamic waveshape control further in Chapter 6. Before proceeding, several fundamental problems become evident when we move from generation of sinusoidal to arbitrary waveforms using DDS principles. These may be summarised as: specification and tabulation of an arbitrary waveform function that is compatible with DDS requirements, as introduced in Chapter 2; an increase in the magnitude of the amplitude error signal εa(n) as a function of waveform harmonic content, the amount of phase truncation (i.e. the number of F bits) and the phase increment φ; the additional computational complexity of linear and higher-order phase interpolation that is required to reduce the magnitude of εa(n) and hence increase waveform SNR and SFDR; the susceptibility to harmonic alias images in the Nyquist band when the upper waveform harmonics exceed the Nyquist frequency; the necessity for pre-tabulation band-limiting of a wavetable function specified in the time domain (i.e. by shape) to mitigate harmonic aliasing caused by the high frequency content of any waveform discontinuities. As introduced in Chapter 2, a wavetable function is a periodic function tabulated at discrete phase and amplitude values. Assuming the tabulated function is exactly

5.1 From sinusoidal to arbitrary waveforms

163

periodic, a wavetable of length L samples can then only contain harmonic (i.e. integer) multiples of a fundamental frequency that comprises L samples per cycle. A wavetable cannot tabulate non-harmonic multiples of the fundamental frequency as this introduces an amplitude and phase discontinuity between the end and beginning of the wavetable, leading to distortion upon regeneration. If the wavetable is indexed such that there are exactly L samples per cycle the amplitude spectrum will always be exactly harmonic with a fundamental at fs/L, and contain no error spurs aside from those attributable to amplitude quantisation effects. Fractionally addressing the wavetable to regenerate the tabulated function at a specific frequency necessarily requires resampling the wavetable and interpolation of amplitude values at a fractional address lying between adjacent tabulated phase points. It is the process of fractionally addressing a multi-harmonic wavetable function and the inherently approximating nature of phase interpolation that introduces error spurs into the amplitude spectrum. We begin by considering the consequences of simple phase truncated indexing of non-sinusoidal wavetables as a precursor to fractional wavetable addressing through linear and higher-order phase interpolation.

5.1.1

Phase truncation and the need for interpolation Before proceeding to the general case of multi-harmonic wavetables, we summarise phase truncation effects in sinusoidal DDS as presented in Chapter 4. It is evident from the analytical treatment presented in [1] and the amplitude spectra and SNR simulations presented in Section 4.3 that there is a strong correlation between the number of phase truncation bits F and waveform SNR.1 A similar result is evident for waveform SFDR. A key result from this analysis is that prime values of φ yield the maximum number of amplitude spectrum spurs equal to 2F. Since these spurs are only permuted in frequency for different prime values of φ, we conclude that the SNR must remain constant and at a minimum for all prime values of φ. Therefore, for a given phase accumulator word size M and prime φ value, we conclude that shorter length wavetables (and hence a reducing I value) yield a lower SNR since F is increasing. As a precursor to the general case of multi-harmonic wavetables, let us now imagine a 2I sample wavetable indexed by the I most significant bits of an M-bit phase accumulator output sequence. We therefore have F ¼ M I phase fraction bits and the simplest rounded down phase truncated wavetable indexing. If this wavetable tabulates one sinusoid cycle, the output frequency is given by fo ¼ φfs/2M. If we now tabulate exactly two sinusoid cycles, the output frequency will exactly double for the same value of φ. We can achieve the same result with a single-cycle wavetable of length 2I1 samples (i.e. half the original length) and a phase increment of 2φ. However, we have now effectively increased F by one bit thereby increasing the number of error spurs.

1

According to the definition presented in Section 2.6, we recall that an increase in SNR corresponds to a reduction in noise power relative to the signal.

164


If we assume an integral number of sinusoid cycles per wavetable, which we denote by Nc, computer simulation confirms that the amplitude spectrum always contains 2F/(φ, 2F) spurs and is independent of Nc. For the special case when Nc takes on radix-2 values, the amplitude spectrum for a given value of φ is in exact agreement with that obtained from a shorter single-cycle wavetable indexed by a truncated phase sequence whose phase increment is Ncφ. For this specific case, the single-cycle index word length I 0 is given by I 0 ¼ I log2(Nc). For values of Nc that are not radix-2 (e.g. 3, 5, 6, etc.), we can determine a wavetable length with I 0 I that yields an amplitude spectrum with the same number and frequency of spurs as that obtained from a shorter single-cycle wavetable indexed by a truncated phase sequence whose phase increment is Ncφ. However, the spur amplitudes are generally different between the two spectra and always lower in the single-cycle spectrum. When Nc is odd we have I 0 ¼ I and when Nc is even we have I 0 < I. In general, simulated amplitude spectra confirm that as Nc increases so do the error spur amplitudes. Since Nc is equivalent to harmonic number, this finding combined with the superposition principle, indicates that higher harmonics generally contribute more noise due to phase truncation effects than lower harmonics in a multi-harmonic tabulated waveform function. Equation (2.14) shows that it is possible to tabulate any integer number of sinusoid cycles in a given length wavetable (i.e. harmonic multiples of a fundamental frequency fs/L where one cycle exactly fills the wavetable) provided the Nyquist sampling criterion is satisfied. The key result is that harmonic sinusoids are effectively stored in progressively shorter wavetables with increasing harmonic number leading to reduced SNR. Let us now imagine a 2I wavetable tabulating Nh harmonic sinusoids whose respective amplitude weightings Ak, k 2 [0, Nh] specify some arbitrary waveshape according to the IDFT defined in Eq. (2.14). For the purposes of this illustrative discussion we assume that the phase offset of each harmonic is zero. The kth harmonic will therefore have exactly k cycles per wavetable length. From our previous argument it is apparent that the kth harmonic effectively occupies a shorter wavetable than the fundamental and will therefore have reduced SNR due to increased phase quantisation for a given phase increment φ. We can simulate the SNR of a single harmonic by first modifying Eq. (2.14) to define a wavetable that tabulates only the kth harmonic sinusoid according to Wk[a] ¼ sin(2πka/2I), where a 2 [0, 2I 1] and Wk[a] denotes a wavetable tabulating the kth unit-amplitude sine wave harmonic. We then index this wavetable with a truncated phase sequence ϕI (n) and compute the amplitude error function εa(n) relative to an ideal kth harmonic reference signal, where effectively all phase accumulator states index a 2M location wavetable. Figure 5.1 illustrates the simulated variation in SNR as a function of harmonic number k using a prime φ value, M ¼ 32 and several values of I. We observe that SNR reduces with increasing k for a given wavetable length and increases with wavetable length for a specific value of k. We conclude that DDS AWG based upon a wavetable tabulating a weighted harmonic series will have reduced SNR when compared to the single sinusoid case. The SNR reduction is a function of the number of harmonics Nh, their relative amplitudes


165

100

SNR(dB)

j = 519227

I = 16

80

M = 32

I = 14

60

I = 12 40

I = 10

20 0 1

10

100

1000

k Figure 5.1 SNR variation with harmonic number k 2 [0, 512] for several wavetable lengths L ¼ 2

I

and M ¼ 32. We use a prime value of φ to maximise the amplitude spectrum spur count.

and the amount of phase truncation. There are three methods to mitigate SNR reduction due to increasing waveform harmonic content: use longer wavetables relative to 2M (or, equivalently, reduce the amount of phase truncation for a given value of M ); fractionally address the wavetable using phase interpolation to utilise the otherwise discarded fractional phase ϕF (n); exploit the real-time IDFT model where each harmonic is optimally computed and which we investigate further in Chapters 6 and 7.

5.1.2

Introducing Lagrange polynomial interpolation In this section we present an outline tutorial on Lagrange polynomial interpolation that underpins the fractional indexing of a tabulated signal abstracted as a unit-spaced data set. An order-N Lagrange interpolation polynomial is defined so as to through N þ 1 tabulated data points and thereby locally approximate the underlying function that generated them. Since the polynomial is a continuous function, it can be used to interpolate or approximate values lying between the data points at fractional indices. Let us now consider a well-behaved continuous function f (x) that is tabulated at only N þ 1 discrete ordered points (x0, y0), (x1, y1), . . ., (xN1, yN1), (xN, yN), or equivalently, the set of points (xi, f (xi)} where i ¼ 0,. . ., N. To simplify our analysis, we assume unit-spaced values of x and so xiþ1 xi ¼ 1. This is a valid simplification in wavetable tabulations since they are inherently unit-spaced. To fractionally index this data set we must find the unique order-N polynomial that es through (i.e. interpolates) all N þ 1 data points and therefore allows a value of y to be computed at any x value within the interval x 2 [x0, xN]. Any order-N interpolating polynomial PN (x) may be expressed as a power series, thus: PN ðxÞ ¼ a0 þ a1 x þ a2 x2 þ a3 x3 þ . . . þ aN x N ,

ð5:1Þ

166


where the ak denote the polynomial coefficients with k 2 [0, N ]. Equation (5.1) and the set of tabulated data values can be used to establish a system of N þ 1 linear equations with N þ 1 unknowns: f ðx0 Þ ¼ a0 þ a1 x0 þ a2 x20 þ a3 x30 þ . . . þ aN xN0 , f ðx1 Þ ¼ a0 þ a1 x1 þ a2 x21 þ a3 x31 þ . . . þ aN xN1 , .. .. .. . . .

f ðxN Þ ¼ a0 þ a1 xN þ a2 x2N þ a3 x3N þ . . . þ aN xNN :

ð5:2Þ

We can express this system of equations in matrix form and solve for the polynomial coefficients using the Vandermonde matrix representation, thus: 0

a0 B a1 B B a2 B B .. @ . aN

1

0

1 C B B C B1 C B1 C¼B C B. A @. .

x0 x1 x2 .. .

x20 x21 x22 .. .

1

xN

x2N

11 0 1 xN0 f ðx0 Þ f ðx1 Þ C xN1 C C B C C B N C B f ðx2 Þ C x2 C B C: .. C .. C B .. @ . A . . A N f ðxN Þ x

ð5:3Þ

N

For large N, the Vandermonde matrix becomes ill-conditioned and therefore sensitive to computational rounding errors (e.g. quantisation errors) and can easily produce inaccurate results for only small changes in the coefficients. However, it serves to illustrate the underlying principle of polynomial interpolation. The Lagrange interpolation polynomial formulation that we now describe provides higher computational efficiency compared to the power series form and is generally less susceptible to computational rounding errors. The Lagrange polynomial PN (x) approximates f (x) on the interval x 2 [x0, xN] and can be expressed as a linear combination of order-N ‘basis polynomials’ pk(x) with k 2 [0, N ]. We may express this linear combination as the summation [2]: PN ðxÞ ¼

N X

pk ðxÞf ðxk Þ,

ð5:4Þ

k¼0

where pk ðxÞ ¼

N Y ðx xj Þ ðx x0 Þ ðx xk1 Þðx xkþ1 Þ ðx xN Þ ¼ , f (xk) ðxk x0 Þ ðxk xk1 Þðxk xkþ1 Þ ðxk xN Þ j ¼ 0 ðxk xj Þ j 6¼ k

denotes the tabulated data points and k 2 [0, N ]. Inspecting the numerator of pk(x) we observe that it is an order-N polynomial with zeros at all data points except the kth. The denominator of pk(x) is a constant which normalises pk(x) to unity at xk. Thus we have pk(xj) ¼ 1 for k ¼ j and pk(xj) ¼ 0 for k 6¼ j from which we deduce that PN (xk) ¼ pk(xk) f (xk) ¼ f (xk) and so the interpolating polynomial es through the data points as required. By substituting for pk(x) in Eq. (5.4) we obtain a concise definition of the Lagrange interpolating polynomial that we now use to define wavetable phase interpolation:


2 PN ðxÞ ¼

N 6 X k¼0

167

3

6f ðxk Þ 4

N Y

ðx xj Þ 7 7: ðxk xj Þ5 j 6¼ 0

ð5:5Þ

j 6¼ k

Equation (5.5) may be used to determine an order-N Lagrange interpolation polynomial that interpolates N þ 1 tabulated data points f (xk). Application of Eq. (5.5) may be illustrated with an example. With N ¼ 3 we have the cubic Lagrange interpolation polynomial given by: f ðxÞ

ðx x1 Þðx x2 Þðx x3 Þ ðx x0 Þðx x2 Þðx x3 Þ y þ y ðx0 x1 Þðx0 x2 Þðx0 x3 Þ 0 ðx1 x0 Þðx1 x2 Þðx1 x3 Þ 1 ðx x0 Þðx x1 Þðx x3 Þ ðx x0 Þðx x1 Þðx x2 Þ y2 þ y : þ ðx2 x0 Þðx2 x1 Þðx2 x3 Þ ðx3 x0 Þðx3 x1 Þðx3 x2 Þ 3

ð5:6Þ

Since xiþ1 xi ¼ 1 we can immediately simplify the denominator in Eq. (5.6) to constants, thus: 1 1 f ðxÞ ðx x1 Þðx x2 Þðx x3 Þy0 þ ðx x0 Þðx x2 Þðx x3 Þy1 6 2 1 1 ðx x0 Þðx x1 Þðx x3 Þy2 þ ðx x0 Þðx x1 Þðx x2 Þy3 : 2 6

ð5:7Þ

We now consider an important question when optimising the implementation of Lagrange polynomial interpolation – for a given order interpolation polynomial, how does the interpolation error vary with the independent variable x? Clearly, the interpolation error is zero when x is an integer and therefore indexes a tabulated point. However, when x takes on fractional values, the interpolation error must increase. To investigate this question we need to define a suitable error metric. The interpolation error ε(x) is defined by [3] as: εðxÞ ¼ f ðxÞ PN ðxÞ,

ð5:8Þ

where f (x) represents the exact function being interpolated by the polynomial PN (x) on the interval x 2 [x0, xN]. An analytic expression for the error function is also given by [3]: εðxÞ ¼ LN ðxÞf ðN þ1Þ ðξÞ,

ð5:9Þ

where f (Nþ1)(x) denotes the (N þ 1)th derivative of f(x), ξ depends on x with ξ 2 [x0, xN] and: LN ðxÞ ¼

ðx x0 Þðx x1 Þ ðx xN 1 Þðx xN Þ : ðN þ 1Þ!

ð5:10Þ

We can therefore define an upper bound on the magnitude of ε(x), thus [3]: jεðxÞj jLN ðxÞj max j f ðN þ1Þ ðξÞj: x0 ξxN

ð5:11Þ

The second term in the right-hand side of Eq. (5.11) is constant on the whole domain (i.e. ξ 2 [x0, xN]) and so the behaviour of the upper bound on jε(x)j is determined by LN (x) alone. Figure 5.2 illustrates the behaviour of the LN (x) polynomial for N 2 [1, 5]

168


0.2 0.1 L1(x)

0 −0.1 −0.2

0

0.5

1

0

1

2

0.08 0.04 L2(x)

0

−0.04 −0.08 0.06 0.03 L3(x)

0

−0.03 −0.06

0

1

2

3

0.04 0.02 L4(x)

0

−0.02 −0.04

0

1

2

3

4

0.03 0.015 L5(x)

0

−0.015 −0.03

0

1

2

3

4

5

x Figure 5.2 Behaviour of the LN (x) polynomial for N 2 [1, 5] and unit-spaced tabulation.


169

P3(x) f (x2)

f (x)

f (x1)

f (x0) f (x−1)

x−2

x−1

x0

x

x1

x2

x3

Figure 5.3 Optimum sub-interval allocation for the cubic interpolating polynomial P3(x) assuming

unit-spaced x values.

and unit-spaced tabulation. We observe that LN (x) exhibits minimum amplitude on the middle sub-interval of the range [x0, xN] for odd N and on the two middle intervals centred about the middle sample for even N. In general, this observation is true for all Lagrange interpolation polynomials [3]. For odd N, the fractional address should therefore be placed in the middle interval of the interpolation data set for minimum error bound. For even N, either of the two central sub-intervals produces a minimum error bound. Returning to our cubic interpolation polynomial example and assuming unit-spaced x values, Eq. (5.7) places x in the first sub-interval [x0, x1] of the data set { f(x0), f (x1), f(x2), f (x3)}, leading to a non-optimal error bound. Introducing an offset to the x subscripts in Eq. (5.7) so that the ith subscript becomes x(i⌊N1/2⌋), places x in the optimal middle sub-interval [x0, x1] of the data set { f(x1), f (x0), f (x1), f (x2)}, as illustrated in Figure 5.3, and therefore yields the minimum interpolation error bound. As N ! ∞ and assuming xiþ1 xi ¼ 1, Smith [4] reports that the Lagrange polynomials pk(x) converge to shifts of the sinc function, thus:2 pk ðxÞ ¼

sinðπðx kÞÞ , πðx kÞ

ð5:12Þ

where the index k 2 Z spans an infinite number of data points either side of the x value that we wish to interpolate. Equation (5.12) therefore represents an infinite series of and so in practice we truncate the sinc function to a finite length using a window function in a process known as band-limited interpolation [4]. 2

Strictly, this observation applies for any equally spaced data set. Equation (5.12) refers to unit-spaced data sets and a more general form is given in [4].

170


In Section 5.2 we apply Lagrange polynomial interpolation to the problem of fractional wavetable addressing through phase interpolation. We begin by considering first-order (i.e. linear) interpolation and then proceed to higher-order interpolation polynomials.

5.1.3

The harmonic aliasing problem We have so far only considered the effects of phase truncation in sinusoidal DDS and investigated its detrimental effects on the amplitude spectrum, SNR and SFDR of the generated signal. In this section we investigate harmonic aliasing, a fundamental error mechanism that becomes important when multi-harmonic (i.e. arbitrary) waveforms are tabulated in the wavetable. Harmonic aliasing is simply a manifestation of undersampling when the bandwidth of a signal is greater than the Nyquist frequency. Since we are tabulating single-cycle periodic waveforms in the wavetable, it is appropriate to measure the tabulated waveform bandwidth by the highest harmonic number. Harmonic aliasing occurs when the alias images of higher waveform harmonics fall below the Nyquist frequency and are therefore observed as ‘real’ error spurs within the Nyquist region of the amplitude spectrum. Figure 5.4 illustrates the harmonic aliasing phenomenon and shows two simulated amplitude spectra for a 32 harmonic sawtooth waveform. Figure 5.4a shows the spectrum of a waveform arranged to have a fundamental frequency low enough to prevent aliasing of the higher harmonics. The harmonic spectrum clearly sits well inside the Nyquist region and so all of the alias images lie above the Nyquist frequency and are therefore removed by the reconstruction filter. Figure 5.4c shows the spectrum of a waveform arranged to have a fundamental frequency that ensures several of the higher harmonics lie above the Nyquist frequency and so alias or ‘fold back’ into the Nyquist region. These alias images are clearly evident and have been marked accordingly. The respective time domain waveforms in Figures 5.4b and 5.4d show a clean sawtooth waveform corresponding to the nonaliased spectrum, but significant amplitude modulation (AM) distortion in the aliased case. The non-aliased waveform also reveals the Gibbs phenomenon or ‘ringing’ that follows the sawtooth discontinuities. Gibbs phenomenon occurs as a result of a truncated Fourier series representation of a discontinuity [5]. We investigate methods for reducing this effect in Section 5.1.4 when we discuss arbitrary waveform specification methods. Because of the nature of harmonic aliasing, we can only prevent its occurrence and not reduce its effects once it has occurred. The reason is simple – alias images and the desired waveform harmonics coexist within the Nyquist bandwidth. To understand how we might prevent its occurrence, we must remind ourselves of the nature of wavetable tabulation. Any periodic, single-cycle signal tabulated in a wavetable can be represented by the sum of an amplitude and phase weighted series of harmonic sinusoids. This representation therefore has a maximum harmonic number Nh, which we define as the largest value of harmonic index k for which the corresponding harmonic amplitude Ak > 0. Therefore, no harmonic will alias if the


Amplitude (dBFS)

0

ϕ = 743 I = 16 M = 16 N h = 32 − 6 db/oct

(a)

− 10 − 20 − 30 − 40 − 50

0

0.1

0.2

0.3

0.4

0.5

1

Amplitude

0.5

0 − 0.5

(b) −1

0

128

256

384

512

Amplitude (dBFS)

0

ϕ = 1801 I = 16 M = 16 N h = 32 − 6 db/oct

− 10

Aliased harmonics − 20 − 30 − 40 − 50

(c) 0

0.1

0.2

0.3

0.4

0.5

1

Amplitude

0.5

0 − 0.5

(d) −1

0

128

256

384

512

Normalised frequency / Time index Figure 5.4 An illustration of harmonic aliasing using a sawtooth waveform whose harmonic

amplitudes reduce at 6 dB/octave. Marked spurs indicate the aliased harmonics which are manifest as AM distortion in the corresponding waveform.

171

172


inequality φN h =2M < 12 is satisfied, where fo/fs ¼ φ/2M. In turn, there are three practical interpretations of this inequality: M for a specified maximum fundamental frequency, fo(max) ¼ φmax fs/2 , and fixed sample frequency, we constrain Nh according to Nh < fs/2fo(max); for a specified maximum value of Nh and fixed sample frequency, we constrain the fundamental frequency fo according to fo < fs/2Nh; for specified maximum values of Nh and fo, we constrain the sampling frequency fs according to fs > 2Nh fo.

We observe that there are only three design variables to optimise if we wish to prevent harmonic aliasing – the maximum fundamental frequency fo(max), the sample frequency fs and the maximum harmonic number Nh. Each of these inequalities constrains one of these variables as a function of the other two. Although the most costly in of hardware processing speed, DAC performance requirements and power consumption, the last approach offers the most flexibility and performance. The second option can be recast to effectively specify an oversampling system where fs 2Nh fo(max).

5.1.4

Time domain specification of an arbitrary waveform In Chapter 2 we outlined several methods for specifying an arbitrary waveform according to waveshape, spectral composition or simply capture from a digital storage oscilloscope. In this section we focus on the first of two important methods differentiated according to a time or frequency domain specification. Which method we use depends upon whether control of the synthesised signal’s waveshape or spectrum is important in a particular application. If accuracy of waveshape is important then we should specify our waveform using a time domain method. This usually arises when relative timing of waveform features with some external event is critical. Alternatively, if spectrum accuracy is important then we should specify our waveform using a frequency domain method. This often arises when the location and confinement of a signal’s spectrum within some operating bandwidth interval is critical. We begin by investigating methods for specifying a waveform in the time domain using a piecewise linear (PWL) method. Fundamentally, a wavetable performs a conversion from the phase to the amplitude domain. Accordingly, when we consider the resolution with which we can specify ‘waveshape features’ there are two dimensions to consider – phase and amplitude. This is most important when waveshape precision is paramount and we wish to use a time domain waveform specification as introduced in Section 2.3.3. The wavetable can be abstracted as a memory comprising L storage locations, which determines the phase resolution of 2π/L radians and therefore the corresponding time resolution with which arbitrary waveform features can be localised in time. Each storage location comprises a fixed number of bits b, which determines the amplitude quantisation and hence the precision with which arbitrary waveform features can be localised in amplitude. Alternatively, if we consider a frequency domain waveform specification according to a weighted harmonic series, the length of the wavetable governs the highest frequency harmonic available. For a length L wavetable the highest harmonic number is L/2.


173

A PWL specification partitions the definition of a waveform function into a contiguous set of linear segments, each segment describing the instantaneous amplitude as a function of phase over a sub-interval of one cycle. The phase of a particular amplitude point in the waveform specification can be considered relative to a full-scale point (i.e. 2π) that represents a ‘normalised period’. Accordingly, use of phase as the independent variable enables us to specify waveshape independently of absolute time. Only upon waveform regeneration at a particular frequency does the waypoint phase become analogous to time. The complete waveform cycle is specified as a list of arbitrary ‘coordinates’ in phaseamplitude space, which are connected (or interpolated) by linear segments to define the continuous waveform function we denote by w(ϕ), where ϕ 2 [0, 2π). This enables the shape of complex waveform functions to be approximated using relatively few data in a piecewise-linear fashion. Figure 5.5 illustrates an example sawtooth-like PWL waveform function which includes several step discontinuities and requires only eight phaseamplitude coordinates to specify. To regenerate this waveform requires only four additional parameters: amplitude, frequency, phase offset and DC offset. We observe that when using a PWL specification it is possible to specify stepdiscontinuities with theoretically infinite slope as evident in the example of Figure 5.5, which clearly contains four per cycle. The function discontinuities require an infinite harmonic series to represent them in the frequency domain, and these harmonics will alias into the Nyquist band upon regeneration. Band-limiting the waveform function before tabulation mitigates this problem by reducing the number of harmonics needed to represent the waveform at the expense of increasing the transition time of the +FS PWL interpolation between waypoints

(φ8 , A8 )

Amplitude A

(φ4 , A4 )

(φ3 , A3 )

(φ6 , A6 )

(φ7 , A7 )

2π

π

0

(φ2 , A2 )

Phase φ

(φ5 , A5 )

Waypoint

(φ1 , A1 )

-FS

Regenerated waveform

Wavetable ‘phase–amplitude space’

t

Figure 5.5 Piecewise-linear (PWL) specification of an arbitrary waveform function as a set of

waypoint phase–amplitude coordinates. The regenerated waveform is also shown.

174


discontinuities. Step-discontinuities are now represented by well-behaved monotonic curves consistent with the reduced bandwidth. A one–one mathematical function may also be used to specify a phase–amplitude waveform function exactly. The sine function is a simple example which maps a phase argument on the interval [0, 2π) to a corresponding amplitude value on the interval [1, 1]. More complex and useful functions may be composed in a piecewise or segmented manner by defining a so-called hybrid function comprising multiple concatenated subfunctions whose arguments are defined on sub-intervals of [0, 2π). An example hybrid function is defined in Eq. (5.13) and partitions the waveform function w(ϕ) into four concatenated sub-functions w1(ϕ), w2(ϕ), w3(ϕ) and w4(ϕ), each defined on the subintervals [0, ϕ1), [ϕ1, ϕ2), [ϕ2, ϕ3) and [ϕ3, 2π), respectively:3 8 w1 ðϕÞ z1 , ϕ 2 ½0, ϕ1 Þ > > < w2 ðϕÞ z2 , ϕ 2 ½ϕ1 , ϕ2 Þ ð5:13Þ wðϕÞ ¼ : w ðϕÞ z3 , ϕ 2 ½ϕ2 , ϕ3 Þ > > : 3 w4 ðϕÞ z4 , ϕ 2 ½ϕ3 , 2πÞ If the sub-functions are simple linear expressions of the form fk(ϕ) ¼ mϕ þ c, where m and c are constants, we have a hybrid function implementation of the PWL specification method. This method has been used to generate the example waveform shown in Figure 5.5. The zk (k ¼ 1, 2, 3, 4) subtract an offset correction constant from each subfunction to ensure discontinuity-free concatenation over the whole domain. If the zk are set to zero, the four sub-functions are concatenated with amplitude stepdiscontinuities at the transition points whose magnitude depends on the end and start values of adjacent sub-functions. If we require discontinuity-free concatenation the zk for Eq. (5.13) are defined thus: z1 ¼ 0, z2 ¼ w2(ϕ1) w1(ϕ1), z3 ¼ w3(ϕ2) w2(ϕ2) þ z2 and z4 ¼ w4(ϕ3) w3(ϕ3) þ z3. In general, for k 2 [1, m] the kth sub-function is defined on [ϕk1, ϕk] and zk ¼ (wk(ϕk1) wk1(ϕk1)) þ zk1, where ϕ0 ¼ 0, ϕm ¼ 2π and z1 ¼ 0. The example PWL waveform shown in Figure 5.5 is a modified sawtooth function, obtained by setting the sub-functions and the phase interval boundary values, thus: 8 ϕ=2π, ϕ 2 ½0, 2π=3Þ > > < ðϕ þ 1Þ=2π, ϕ 2 ½2π=3, πÞ ð5:14Þ wðϕÞ ¼ 2 1: ðϕ 1Þ=2π, ϕ 2 ½π, 4π=3Þ > > : ϕ=2π, ϕ 2 ½4π=3, 2πÞ Equation (5.14) defines a waveform whose amplitude is bound on 1 which corresponds to the DAC full-scale upon regeneration. In general, a PWL waveform specification requires the application of further arithmetic processing operations before we can tabulate the waveform function. These operations comprise: unit-amplitude normalisation; band-limiting to limit the harmonic bandwidth of the waveform; phase and amplitude quantisation (since w(ϕ) is a continuous function of ϕ).

3

We assume here that the waveform phase is measured in radians and so 2π corresponds to one full cycle.


175

To maximise amplitude dynamic range and hence signal to quantisation noise ratio, the waveform function is normalised to unit-amplitude (where we define the DAC full-scale as unit amplitude for simplicity). This ensures that the peak waveform amplitude corresponds to full-scale in the wavetable and so the amplitude dynamic range is fully utilised. PWL specification mitigates this problem directly if the full-scale amplitude is bound on 1 and takes of the slightly asymmetrical dynamic range with 2’s complement amplitude sample representation. For a hybrid waveform function specification, amplitude normalisation can be implemented by defining the sub-functions so that the overall function is amplitude normalised, or computing a normalising constant 1/maxjw(ϕ)j for ϕ 2 [0, 2π) after the waveform function has been specified. The waveform function is then scaled by the normalising constant before phase and amplitude quantisation and finally tabulation in the wavetable. The bandwidth of a periodic waveform function that is defined according to its waveshape is strictly unbounded and determined by the fastest rate of change in the phase–amplitude curve (e.g. a step amplitude discontinuity). Computing the discrete Fourier transform4 of the tabulated (i.e. discrete) waveform function according to a specific wavetable length L and hence phase quantisation 2π/L, determines the highest significant harmonic frequency relative to the wavetable frequency and hence bandwidth. If the wavetable function comprises significant harmonic energy at or near the L/2 Nyquist maximum, aliasing occurs when the wavetable is undersampled during DDS regeneration at any frequency above fs/L. Filling a length L wavetable requires sampling and amplitude-quantising the waveform function at regularly spaced phase intervals of 2π/L to produce a length L sample vector that is written into the wavetable. The tabulation process is then described by the expression a W½a ¼ Q w 2π , ð5:15Þ L where a 2 [0, L 1] and Q(x) denotes a uniform quantiser function as defined by Eq. (2.11). Typically, the quantised samples will require conversion into a binary format suitable for storing in the wavetable, such as fractional 2’s complement. The tabulation process can be likened to a sampling operation where the effective sampling frequency is exactly L samples/cycle and causes all alias frequencies to be exact harmonics of the waveform. If the wavetable is indexed (i.e. resampled) with a unit phase increment and sampling frequency fs, the resulting signal will have an exactly harmonic spectrum (neglecting amplitude quantisation noise) with fundamental frequency fs/L. At this point, we should that some waveform specification methods produce discrete waveform functions (i.e. quantised in phase and amplitude), for example, the DSO capture method. However, as we have outlined, this method generally requires resampling of the captured waveform to produce correctly spaced samples for tabulation in the wavetable.

4

Since our waveform is specified as exactly one cycle (by definition) its discrete Fourier transform contains exactly harmonic frequencies at the output spectrum bin centres (i.e. integer multiple of the fundamental frequency).

176


The sampling theorem requires that the highest frequency harmonic in our tabulated waveform always be sampled at more than 2 samples/cycle when the wavetable is undersampled (i.e. samples are skipped) during phase accumulated indexing. Therefore, an L point wavetable can contain up to L/2 harmonics, which places an upper-bound on the waveform frequency of fs/L to prevent aliasing of the highest harmonics. In practice, the highest frequency harmonic in the tabulated waveform must somehow be limited to less than L/2 to prevent harmonic aliasing at high waveform frequencies when the wavetable is undersampled. We call this process waveform band-limiting and it must be considered for any time domain waveform specification. In essence, band-limiting any waveform function requires application of an ‘in-place’ digital low- filter to the waveform function before tabulation in the wavetable. As we are working with a vector of signal samples, the filtering operation can be efficiently implemented using an FFT/IFFT block convolution.5 This approach is particularly convenient if the FFT input record and waveform sample vector lengths are made equal, which is easy to arrange. In turn, this causes harmonics of the input waveform to align exactly with the FFT bin centres and so each FFT bin corresponds to a unique harmonic. Let us assume that our unfiltered ‘input’ wavetable sample vector is represented by the length-L sequence W[a] ¼ w(2πa/L)6 and the corresponding band-limited ‘output’ vector is represented by the sequence Wb[a], with a 2 [0, L 1] the vector index. We may then define Wb[a], thus: Wb ½a ¼ F 1 ðH a F ðW½a ÞÞ,

ð5:16Þ

where F and F 1 denote the forward and inverse discrete Fourier transforms, respectively, and Ha denotes a length-L/2 vector of harmonic magnitude coefficients (i.e. a discrete frequency response). We observe that W[a] and Wb[a] are only quantised in phase and require amplitude quantisation according to Eq. (2.11) before tabulation in the wavetable. For L real data values (i.e. our wavetable samples), the DFT produces a length-L/2 complex output vector that represents a harmonic amplitude and phase spectrum. The filter magnitude response is a length-L/2 real-valued vector which multiplies the complex DFT output vector to produce a length-L/2 complex-valued input vector to the IDFT as required. The IDFT in turn produces a real-valued length-L output vector which is our filtered waveform function suitable for tabulation in the wavetable after amplitude quantisation. Each element in Ha represents a scaling coefficient applied to the respective wavetable harmonic amplitude. Since it always takes on real values, it does not affect harmonic phase and hence preserves the general waveshape. Typically, Ha follows a low- response from a ¼ 0 to Nh (the highest harmonic we wish to

5

6

Digital filtering is a time domain convolution operation that is implemented more efficiently for long sequences by using an FFT-based convolution rather than a conventional tapped delay line FIR filter. We use square bracket notation to denote a finite length sequence.


177

include in the band-limited waveform), and is zero elsewhere up to a ¼ L/2 1. We therefore define Ha according to: 8 a 2 ½0, N h > < f ðaÞ L Ha ¼ 0 ð5:17Þ a 2 ðN h , 1 , > : 2 where f (a) defines a typically low- frequency response function on the interval a 2 [0, Nh] and effectively describes an amplitude scaling of a truncated Fourier series. We could define f (a) as a simple rectangular window function to implement a ‘brickwall’ filter response. However, this introduces ringing artefacts due to the Gibbs phenomenon that are coincident with any step discontinuity in the waveform function. The filter response should follow a smooth transition from -band to stop-band to eliminate ringing artefacts in the output waveform. To define f (a) the Lanczos sigma factor [6] may be used to mitigate waveform artefacts due to the Gibbs phenomenon. The Lanczos sigma factor is a linear weighting of a Fourier summation that reduces the ‘ringing’ symptomatic of Gibbs phenomenon following a discontinuity. We may define f (a) in of the Lanczos sigma factor, thus: Nh aπ f ðaÞ ¼ , ð5:18Þ sin Nh aπ where a 2 [0, Nh]. Figure 5.6 illustrates this frequency response function against normalised frequency a/L for several values of Nh and L ¼ 4096. Figure 5.6a shows the frequency response curves over the whole Nyquist bandwidth and Figure 5.6b shows the same response curves over the reduced bandwidth a/L 2 [0, 0.05]. Figure 5.7 illustrates examples of a band-limited waveform function using the Lanczos sigma factor to limit the number of harmonics. Our test waveform function is a modified sawtooth that contains step discontinuities to highlight the effects of bandwidth reduction, which are manifest as an increase in discontinuity transition time and shape. The filter Ha is defined by Eq. (5.17) where we use several values of Nh to show the effects of reducing harmonic count and hence bandwidth. For a length-L wavetable we can express Nh as an equivalent normalised bandwidth fh ¼ Nh/L 2 [0, 0.5]. Figure 5.7 demonstrates the increase in discontinuity transition time observed with reducing Nh as expected. However, with Nh ¼ 64 we obtain a reasonable representation of the original waveform function with negligible ringing or overshoot at the discontinuities. As Nh reduces, we observe a progressive increase in the discontinuity transition time, and with Nh ¼ 8 the central step discontinuity is reduced to an almost a sinusoidal perturbation. Figure 5.8 shows the corresponding amplitude error functions εa(n) as Nh reduces. The peaks of the amplitude error function coincide with the waveform discontinuities and do not vary significantly with reducing Nh. The waveshape error is proportional to the area under the error function curve, which is shown shaded, and as Nh reduces, the waveshape error clearly increases across the whole waveform.

178


1

L = 4096 a L ∈ [0, 0.5]

0.8

(a)

0.6

Ha

0.4

N h = 512

0.2 0 0

0.1

0.2

0.3

0.4

0.5

1

L = 4096 a L ∈ [0, 0.05]

0.8

(b)

0.6

Ha

0.4

N h = 64

0.2

N h = 32

N h = 128 N h = 96

0 0

0.01

0.02

0.03

0.04

0.05

Normalised frequency a L Figure 5.6 Examples of wavetable band-limiting filter responses according to Eq. (5.18) for several

values of Nh and two spans of normalised frequency a/L.

Finally, it is now apparent that if a waveform is synthesised7 in real time from an amplitude and phase weighted harmonic series using the IDFT, band-limiting may be controlled by limiting the number of harmonics included in the IDFT summation according to the fundamental frequency. This observation is important in Chapter 7 when we investigate real-time implementation of the IDFT as a DDS phase–amplitude mapping algorithm.

5.1.5

Frequency domain specification of an arbitrary waveform In this section we consider arbitrary waveforms that are defined according to a frequency domain specification. This specification comprises a harmonic spectrum of amplitude and phase values that we denote by the vectors Ak 2 [0, 1] and θk 2 [0, 2π), respectively. We observe that A0 defines the waveform DC component only when θ0 ¼ 0 and that waveforms generated from a harmonic spectrum are always periodic. In Section 2.3.4 we saw how the inverse discrete Fourier transform (IDFT) may be used to compute a wavetable vector from a harmonic spectrum specification. We now present a modified form that reduces the effects of the Gibbs phenomenon by incorporating 7

We use the term synthesis here as opposed to generation as this most accurately describes the IDFT operation which combines a set of distinct amplitude-weighted harmonics to form the resultant signal.

179


1

W[a ]

0

Nh = ∞

−1 0

1024

2048

3072

4096

1

Wb [a ]

0

N h = 64

−1 0

1024

2048

3072

4096

1

Wb [a]

0

N h = 32

−1 0

1024

2048

3072

4096

3072

4096

1

N h = 16

Wb [a]

0

Nh = 8 −1 0

1024

2048

Wavetable sample index a Figure 5.7 Band-limiting a waveform function to a specific number of harmonics using the

Lanczos sigma factor. We observe significantly reduced ringing in the vicinity of the waveform discontinuities.

180


1

N h = 64 0.8

ε a (a )

0.6 0.4 0.2 0 0

1024

2048

3072

4096

1

N h = 32 0.8

ε a (a )

0.6 0.4 0.2 0 0

1024

2048

3072

1

4096

N h = 16

0.8

ε a (a)

0.6 0.4 0.2 0 0

1024

2048

3072

1

4096

Nh = 8

0.8

ε a (a )

0.6 0.4 0.2 0 0

1024

2048

3072

4096

Wavetable sample index a Figure 5.8 Amplitude error functions corresponding to Figure 5.7. The area under each curve is shown shaded to highlight the increasing waveshape error with reducing Nh.


181

a harmonic scaling function Hk that is based upon the Lanczos sigma factor introduced in Section 5.1.4. Expressing the IDFT in a non-complex form and incorporating the quantiser function yields the wavetable tabulation expression, thus: ! Nh X a W½a ¼ Q ð5:19Þ Ak H k cos 2πk þ θk , L k¼0 where L is the wavetable length in samples, a 2 [0, L 1], Nh 2 [1, L/2 1] and Q denotes the amplitude quantiser function. The harmonic scaling function Hk is defined according to the Lanczos sigma factor given by Eq. (5.7). Specifying a spectrum that would tend to introduce a discontinuity into the corresponding waveform will now have reduced ringing following the discontinuity due to the filtering effect of the Hk coefficient vector as illustrated in the example waveforms of Figure 5.9. Figures 5.9a and 5.9c show sawtooth and square waveforms computed from a truncated Fourier series where Gibbs ringing artefacts are clearly evident. Figures 5.9b and 5.9d show the same waveforms, but with their respective spectra weighted by the Lanczos sigma factor according to Hk. The number of samples per cycle in the fundamental is simply L, hence harmonic number h will have L/h samples per cycle. Therefore, the highest harmonic multiplier Nh is bound according to Nh < L/2 to satisfy the Nyquist sampling criterion. The frequency domain specification defined by Eq. (5.19) allows arbitrary bandlimited spectra to be synthesised. It is not always appropriate for synthesising a particular waveshape from scratch, which is often best handled by the PWL time domain specification method discussed earlier. However, we may determine a ‘baseline’ amplitude and phase spectrum from a reference waveform (e.g. captured from a DSO) using the FFT, and then explore the effect of spectrum modification on the resynthesised waveshape. Similarly, if a waveform’s spectrum is defined by a mathematical function, as with the sawtooth waveform for example, this method provides a way of exactly specifying a band-limited form of that waveform.

5.1.6

Defining DDS AWG simulation parameters In this section we outline considerations for selection of design and control parameters to performance simulation of DDS AWG algorithms using the metrics of amplitude spectrum SNR and SFDR. We present the results of these simulations in Section 5.2. To illustrate the effects of phase truncation and interpolation alone, we compute these simulations using amplitude samples represented to full floating point precision, thereby eliminating amplitude quantisation noise whose effects are well defined. The Mathcad models that we use to compute these simulations allow imposition of fixed-point amplitude quantisation according to a specified number of bits. There are several fundamental parameters common to all DDS AWG simulations: M – the phase accumulator word size (ϕ(n)); I – the truncated phase integer component word size (ϕI (n)) where L ¼ 2I; F – the truncated phase fraction component word size (ϕF (n));

182


2

(a) 1

0

−1 −2 0

1024

2048

3072

4096

1024

2048

3072

4096

1024

2048

3072

4096

1024

2048

3072

4096

2

(b) 1

0

−1 −2 0 2

(c) 1

0 −1 −2 0 2

(d) 1

0 −1 −2

0

Figure 5.9 Illustrating the effect of Hk on reducing the Gibbs phenomenon in two simple

waveforms with discontinuities.


183

φ – the phase increment, which controls frequency; Nh – the number of harmonics that specify the tabulated waveform; Ak – the wavetable harmonic amplitude vector with k 2 [1, Nh]; θk – the wavetable harmonic phase vector with k 2 [1, Nh]; Hk – the wavetable band-limiting filter response coefficients; Ns – the number of waveform samples computed in the simulation.

We choose M according to the required frequency control resolution. Optimum computation of the amplitude spectrum using an FFT requires that Ns ¼ 2M samples. This causes the signal and error spurs to always lie exactly on an FFT bin centre. The amplitude spectrum is then exact and there is no FFT ‘bin leakage’. However, large values of M consistent with high frequency control resolution require very long FFT records and hence impractically long execution times. In the simulations whose results we present here, we generally choose M ¼ 16 and Ns ¼ 2M when we wish to compute exact amplitude spectra. For SNR and SFDR simulations we choose M ¼ 32 and Ns ¼ 216, as FFT bin leakage does not cause significant errors here. The value of I is a key design parameter that we vary to investigate the corresponding effect on amplitude spectrum, SNR and SFDR. For a given value of M, F varies directly with I and so I indirectly determines the amount of phase truncation and hence the amplitude of ϕF (n). In Section 4.2.2 we introduced the metric Λ as the number of spurs in the sinusoidal DDS amplitude spectrum. Equation (4.28) defined Λ as a function of only two variables – the phase increment φ and the amount of phase truncation as measured by the number of phase fraction bits F. For any prime value of φ, we have (φ, 2F) ¼ 1 for all F whereupon Eq. (4.28) reduces to Λ ¼ 2F and therefore defines the maximum amplitude spectrum spur count. In sinusoidal DDS, the amplitude spectrum spur count is a useful error metric, where all but one spur (the fundamental) is erroneous. Hence we observe that there are Λ 1 error spurs in the sinusoidal DDS amplitude spectrum. We now consider the general case of an arbitrary waveform composed of multiple harmonics. We have already seen how DDS AWG can be viewed in the frequency domain as a linear combination of harmonic sinusoids according to the IDFT. Assuming fixed φ, F and hence I values, computer simulation of the DDS amplitude spectrum for various integral numbers of tabulated sinusoids Nc, reveals that Λ remains constant at 2F. With increasing Nc, the magnitude of the sine error spurs also increases and their respective frequencies change. Accordingly, the SNR must reduce with Nc and this result is consistent with the simulation results presented in Figure 5.1. Using results from Section 5.1.1, we deduce that the amplitude error signal due to phase truncation can be represented as a superposition of the individual harmonic amplitude errors due to phase truncation. As each harmonic contributes Λ 1 error spurs we expect up to Nh(Λ 1) error spurs8 in the amplitude spectrum. When simulating worst case DDS AWG performance, we therefore choose prime φ values. A test waveform can be tabulated using the IDFT as defined by Eq. (2.14) and requires three parameters – the number of harmonics Nh, the amplitude vector Ak and 8

This figure is an upper bound, as some error spurs may overlap depending on parameter values.

184


the phase vector θk where k 2 [1, Nh]. For the purposes of investigating error spectrum behaviour due to phase truncation, we can ignore the θk phase (setting them to zero) and only need consider the amplitude Ak. We generate the vector Ak of Nh harmonic amplitudes according to a simple piecewise-linear envelope comprising two variable slope segments with an arbitrary breakpoint harmonic kb between them. Two variables r1 and r2 define the spectrum slopes before and after the breakpoint harmonic, respectively. We have: 8 0 1r1 > > 1 > > A@ A k 2 ½1, k b Þ > > < k 0 1r1 r2 0 1r2 ð5:20Þ Ak ¼ , > > 1 1 > > > k 2 ½k b , N h A@ A @ A > : kb k where Ak represents the kth harmonic amplitude and A represents the fundamental amplitude. The spectrum slopes are given by 6r1 and 6r2 db/octave and can be set positive or negative. For example, setting r1 ¼ 0 and r2 ¼ 1 generates a low- spectrum that is flat (i.e. 0 dB/octave) to kb and rolls off at 6 dB/octave thereafter. In the simulations which follow, we choose simple test spectra that continuously roll-off at 3 or 6 dB/octave starting at the fundamental with no breakpoint.

5.1.7

Optimal phase–amplitude mapping Before proceeding further, it is instructive to consider the output spectrum of a 2M location wavetable W containing a single-cycle, periodic band-limited signal, whose ath value we represent by W[a]. This represents the optimal phase–amplitude mapping condition. W tabulates the weighted sum of Nh harmonics (a truncated Fourier series with DC term), thus: W½a ¼

a Ak cos 2πk M , 2 k¼0

Nh X

ð5:21Þ

where a 2 [0, 2M 1], k 2 [0, Nh], Nh 2 [1, 2M1 1] and Ak 2 [0, 1]. The waveform DC term is represented by A0. Optimal phase–amplitude mapping requires that the wavetable is indexed by all M bits of the phase accumulator output sequence giving the amplitude sequence y(n) ¼ W[ϕ(n)], thus: hnφi2M yðnÞ ¼ Ak cos 2πk M , 2 k¼0 Nh X

ð5:22Þ

with frequency fo ¼ φfs/2M. Following a similar argument to the sinusoidal case presented in Section 4.1.2, we obtain: yðtÞ ¼

Nh X k¼0

Ak cosð2π fo kt Þ hðt nT Þ,

ð5:23Þ


185

where y(t) represents the continuous-time signal at sampling instants t ¼ nT to give y(nT). Following similar reasoning to the sinusoidal case, the discrete Fourier transform of y(n) is given by: Y^ ð f Þ ¼ fs

∞ X

Y ð f mf s Þ,

ð5:24Þ

m¼∞

where Y( f ) denotes the spectrum of the periodic continuous-time signal y(t) which represents the ideal DDS AWG output signal assuming an ideal DAC and reconstruction filter. Y( f ) is given by: ∞ X

Yð f Þ ¼

ck δð f kfo Þ,

ð5:25Þ

k¼∞

where ck denotes the kth complex Fourier coefficient of y(t). The complex Fourier coefficients are defined by: Tðo

ck ¼ f o

yðtÞe2πj fo kt dt:

ð5:26Þ

0

Substituting for y(t) in Eq. (5.26) and ignoring phase, we obtain jckj ¼ Ak and hence the magnitude spectrum of y(t) is given by: Yð f Þ ¼

Nh X

Ak δð f kfo Þ:

ð5:27Þ

k¼N h

The discrete spectrum Y^ ð f Þ is obtained by substituting for Y( f ) from Eq. (5.27) into Eq. (5.24), thus: Y^ ð f Þ ¼ fs

Nh ∞ X X

Ak δð f nfo kfs Þ:

ð5:28Þ

n¼∞ k¼N h

Equation (5.28) shows that under the optimal phase–amplitude mapping conditions all harmonics of y(nT) are aliased about every integer multiple of the sample frequency fs with no other frequency components present. As with the sinusoidal case, we apply the shaping function H( f ) ¼ ejπf T sinc( f T ) that represents the frequency response of the zero-order hold implicit on conversion into the continuous-time domain. Thus, we finally obtain: Y^ ð f Þ ¼ ejπf T sincð f T Þ fs

Nh ∞ X X

Ak δð f nfo kfs Þ:

ð5:29Þ

n¼∞ k¼N h

Figure 5.10 illustrates the spectrum Y^ ð f Þ under optimal phase mapping conditions where L ¼ 2M, and indicates that only the wavetable spectrum and its alias images are present. The example wavetable spectrum in this simulation comprises four equal amplitude harmonics.

186


Amplitude (dB)

0 − 3.9

⎛ f ⎞ sinc⎜⎜ ⎟⎟ ⎝ fs ⎠

− 10

fo − 20 − 30 − 40 0

0.5

fs

2

4

6

Frequency (cycles/sample) f f s ^ ð f Þ from a four-harmonic wavetable with harmonic amplitudes Figure 5.10 Resynthesised spectrum Y set to unity to illustrate how alias images conform to the zero-order hold frequency response H( f ).

5.2

Interpolated phase–amplitude mapping In this section we present simulated performance results for several arbitrary waveform phase–amplitude mapping algorithms. Each simulation illustrates the behaviour of the amplitude spectrum, SNR and SFDR performance metrics over variation of important design and control parameters (e.g. wavetable harmonic profile, wavetable length and phase interpolation order). In all simulations, the phase increment φ is set to a suitable prime value to ensure worst case error spectrum spur count and non-aliasing of the highest harmonic in the wavetable (i.e. Nhφ << 2M1). The amplitude spectra have been computed using an FFT record length of 2M samples to ensure that every spectrum line (spur) lies exactly on a bin centre to prevent spectral leakage across FFT bins. This allows us to illustrate exact spectral composition and examples of harmonic aliasing. We set M ¼ 16 giving 64k FFT sample records in the amplitude spectrum simulations. In most simulations we use a sawtooth waveform computed from a specific number of harmonics as our periodic wavetable function. Harmonic amplitude therefore reduces at 6 dB/octave.

5.2.1

Phase truncated wavetable indexing We define the optimal DDS AWG wavetable indexing case as a wavetable comprising 2M samples that is indexed by an M-bit non-truncated phase accumulator sequence ϕ(n). The resulting ideal waveform sequence is therefore devoid of phase truncation errors and may be approximated by using an interpolated phase–amplitude mapping algorithm that indexes a smaller wavetable with a phase truncated sequence ϕI (n). We begin our investigation by considering the simplest case that uses phase truncated wavetable indexing alone, which can be considered as zero-order interpolation. An ideal DDS AWG waveform sequence is then approximated by the phase truncated wavetable indexing operation: WM ½ϕðnÞ W½ϕI ðnÞ ,

ð5:30Þ

5.2 Interpolated phase–amplitude mapping

187

where WM[x] denotes the optimal wavetable containing 2M samples, W[x] denotes the phase truncated wavetable comprising 2I samples and ϕI (n) denotes the I-bit phase truncated sequence as defined by Eq. (4.13). Figure 5.11 illustrates four phase truncated amplitude spectra corresponding to a 32 harmonic approximation of a sawtooth waveform synthesised at a low frequency with φ/2M 0.001 and four values of I. The harmonic roll-off is therefore 6 dB/octave in each simulation. We observe the closely-spaced waveform harmonics grouped at the left hand side of the spectrum and the remainder of the Nyquist bandwidth occupied by tightly grouped erroneous spur clusters whose distribution varies with wavetable length L ¼ 2I. These spur clusters are DDS aliases of the waveform harmonics. As L increases and the corresponding I value approaches M, we observe that the number of error spurs reduces. When I ¼ M we have the optimal phase–amplitude mapping condition and no erroneous spurs are evident. Figure 5.12 illustrates a similar simulation across the same four values of I, but now at a higher frequency where φ/2M 0.007. Once again, the waveform harmonics are clearly evident on the left-hand side of the spectrum and are now spaced further apart. We observe a steadily reducing number of error spurs with increasing wavetable length, with some spurs lying between the waveform harmonics, which is typical of DDS AWG behaviour. As before, when I ¼ M we have the optimal phase–amplitude mapping condition and no error spurs are evident. Figure 5.13 illustrates SNR and SFDR variation with I for two tabulated waveform spectra. The first spectrum describes a 256 harmonic sawtooth waveform whose harmonic amplitudes reduce at 6 dB/octave, and the second a similar spectrum whose harmonic amplitudes reduce at 3 dB/octave. The latter spectrum therefore contains more energy in the upper harmonics, leading to increased error spur magnitude and hence reduced SNR and SFDR. In all cases we use M ¼ 32 and a prime value of φ. We observe that both SNR and SFDR improve linearly with increasing wavetable length, although SFDR does not change significantly with waveform harmonic roll-off rate. However, SNR does exhibit a significant dependence on harmonic roll-off rate for a specific value of I. For the sawtooth waveform spectrum, wavetable lengths of the order of 256k samples (i.e. I ¼ 18) are needed to achieve SNR comparable with 14-bit quantisation noise. We estimate that a wavetable length of 1M sample (i.e. I ¼ 20) would be required to achieve SNR comparable with 16-bit quantisation noise. More practicable wavetable lengths of around 4k samples (i.e. I ¼ 12) can only achieve SNR compatible with around 8-bit quantisation noise under the same conditions. We conclude that phase truncated wavetable indexing is only of utility when the long wavetable lengths (and hence corresponding fill-time) that provide high SNR are acceptable.

5.2.2

Phase dithered wavetable indexing We can apply the principles of phase dithered sinusoidal wavetable indexing introduced in Section 4.3.3 to the general DDS AWG case, whereupon similar improvements in error spur suppression are observed. We use an F-bit pseudo-random dither sequence ϑ(n) 2 [0, 2F 1] that is added to the phase accumulator sequence ϕ(n) modulo


Amplitude (dBFS)

0

ϕ = 73 I = 10 M = 16 N h = 32 − 6 dB/oct

(a)

− 20 − 40 − 60 − 80 − 100 − 120

0

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ϕ = 73 I = 12 M = 16 N h = 32 − 6 dB/oct

(b)

− 20 − 40 − 60 − 80 − 100 − 120

0

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Amplitude (dBFS)

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ϕ = 73 I = 14 M = 16 N h = 32 − 6 dB/oct

(c)

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Amplitude (dBFS)

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ϕ = 73 I = 16 M = 16 N h = 32 − 6 dB/oct

(d)

− 20 − 40 − 60 − 80 − 100 − 120

0

0.1

0.2

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0.4

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Normalised frequency f f s Figure 5.11 Simulated low frequency phase truncated amplitude spectra over four values of I and hence wavetable length L ¼ 2I. The optimal phase–amplitude mapping condition when L ¼ 2M is also shown.

189


Amplitude (dBFS)

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ϕ = 443 I = 10 M = 16 N h = 32 − 6 dB/oct

− 20 − 40 − 60 − 80 − 100 − 120

(a) 0

0.1

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ϕ = 443 I = 12 M = 16 N h = 32 − 6 dB/oct

− 20 − 40 − 60 − 80 − 100 − 120

(b) 0

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Amplitude (dBFS)

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ϕ = 443 I = 14 M = 16 N h = 32 − 6 dB/oct

− 20 − 40 − 60 − 80 − 100 − 120

(c) 0

0.1

0.2

0.3

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0.5

Amplitude (dBFS)

0

ϕ = 443 I = 16 M = 16 N h = 32 − 6 dB/oct

− 20 − 40 − 60 − 80 − 100 − 120

(d) 0

0.1

0.2

0.3

0.4

0.5

Normalised frequency f f s Figure 5.12 Simulated high frequency phase truncated amplitude spectra over four values of I and hence wavetable length L ¼ 2I. The optimal phase–amplitude mapping condition when L ¼ 2M is also shown.


120

120

ϕ = 519227 M = 32 N h = 256 − 6 db/oct

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(a)

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11

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ϕ = 519227 M = 32 N h = 256 − 3 db/oct

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SNR (dB)

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SNR (dB)

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40 20 20

φI (n) bits I Figure 5.13 Simulated phase truncated SNR and SFDR variation with I, where wavetable length L ¼ 2I. Two waveform spectra are simulated. One whose harmonics fall off at 6 dB/octave (i.e. sawtooth) and the other whose harmonics fall off at 3 dB/octave.

2M before truncation to form ϕI (n). Adopting the same denotations as used in Section 5.2.1, we can approximate the ideal DDS AWG waveform sequence by the phase dithered wavetable indexing operation: hϕðnÞ þ ϑðnÞi2M WM ½ϕðnÞ W , ð5:31Þ 2F where M ¼ I þ F and L ¼ 2I. Figure 5.14 illustrates four phase dithered amplitude spectra corresponding to a 32 harmonic approximation of a sawtooth waveform synthesised using two values of I at low and high frequencies with φ/2M 0.001 and φ/2M 0.007, respectively. These simulation conditions correspond exactly with those used in the phase truncated simulations to allow direct comparison of the two cases. We observe that the error spurs are suppressed at the expense of an elevated noise floor that is nominally flat across the Nyquist bandwidth and whose mean level reduces

191


Amplitude (dBFS)

0

ϕ = 73 I = 10 M = 16 N h = 32 − 6 dB/oct

(a)

− 20 − 40 − 60 − 80 − 100

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 73 I = 12 M = 16 N h = 32 − 6 dB/oct

(b)

− 20 − 40 − 60 − 80 − 100

0

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0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 443 I = 10 M = 16 N h = 32 − 6 dB/oct

− 20 − 40 − 60 − 80 − 100

(c) 0

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0.5

Amplitude (dBFS)

0

ϕ = 443 I = 12 M = 16 N h = 32 − 6 dB/oct

− 20 − 40 − 60 − 80 − 100

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Normalised frequency f f s Figure 5.14 Simulated phase dithered amplitude spectra corresponding to the phase truncated simulations reported in Figures 5.11 and 5.12.

192


as F reduces and I increases. SNR and SFDR behaviour are now bound by the noise floor level corresponding to the pseudo-random phase dither and are nominally invariant with φ.

5.2.3

Linear phase interpolated wavetable indexing In Section 4.1.4 we introduced the concept of linear phase interpolation as a solution to the problem of fractionally addressing a sinusoidal wavetable. We can apply linear phase interpolation to the general DDS AWG case by modifying Eq. (4.24), thus: WM ½ϕðnÞ W½ϕI ðnÞ þ αðW½hϕI ðnÞ þ 1i2I W½ϕI ðnÞ Þ,

ð5:32Þ

where α ¼ ϕF (n)/2F 2 [0, 1) and the other denotations have their usual meanings. Equation (5.32) describes a linear phase interpolated wavetable indexing operation where the wavetable now tabulates a band-limited periodic function with arbitrary waveshape. Figure 5.15 illustrates four simulated linear phase interpolated amplitude spectra across four values of I. All spectra correspond to a 32 harmonic approximation of a sawtooth waveform synthesised at low frequency with φ/2M 0.001. We observe the closely-spaced waveform harmonics grouped at the left-hand side of the spectrum and the remainder of the Nyquist bandwidth occupied by tightly grouped erroneous spur clusters whose distribution varies with I and therefore wavetable length L ¼ 2I. The amplitude of the error spur clusters is generally between 30 and 50 dB lower than the corresponding phase truncated case shown in Figure 5.11, depending on I value. As L increases and the corresponding I value approaches M, we again observe that the number and amplitude of the error spurs reduce. In the limit, when I ¼ M we have the optimal phase–amplitude mapping condition and no error spurs are evident. Figure 5.16 illustrates synthesised waveform amplitude spectra at a higher frequency when φ/2M 0.007 across the same four values of I. Once again, the waveform harmonics are clearly evident on the left hand side of the spectrum and are now spaced further apart. The amplitude of the error spur clusters is always between 30 and 40 dB lower than the corresponding phase truncated case shown in Figure 5.12. We observe a steadily reducing number of error spurs with increasing wavetable length, with spurs lying between the waveform harmonics, which is typical of DDS AWG behaviour. As before, when I ¼ M we have the optimal phase–amplitude mapping condition and no error spurs are evident. Figure 5.17 illustrates SNR and SFDR variation with I using linear phase interpolation for two tabulated waveform spectra. The first test spectrum describes a 256 harmonic sawtooth waveform whose harmonic amplitudes reduce at –6 dB/octave and the second a similar spectrum whose harmonic amplitudes reduce at –3 dB/octave. The latter spectrum therefore contains more energy in the upper harmonics leading to reduced SNR and SFDR. In a similar manner to the simple phase truncated case, we observe that SNR and SFDR increase linearly with wavetable length. Furthermore, SFDR does not change significantly with waveform harmonic roll-off rate. However, SNR does exhibit a

193


Amplitude (dBFS)

0 − 20

ϕ = 73 I = 10 M = 16 N h = 32 − 6 dB/oct

(a)

− 40 − 60 − 80 − 100 − 120 − 140 − 160

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0 − 20

ϕ = 73 I = 12 M = 16 N h = 32 − 6 dB/oct

(b)

− 40 − 60 − 80 − 100 − 120 − 140 − 160

0

0.1

0.2

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0.4

0.5

Amplitude (dBFS)

0 − 20

ϕ = 73 I = 14 M = 16 N h = 32 − 6 dB/oct

(c)

− 40 − 60 − 80 − 100 − 120 − 140 − 160

0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0 − 20

ϕ = 73 I = 16 M = 16 N h = 32 − 6 dB/oct

(d)

− 40 − 60 − 80 − 100 − 120 − 140 − 160

0

0.1

0.2

0.3

0.4

0.5

Normalised frequency f f s Figure 5.15 Simulated low frequency linear phase interpolated amplitude spectra over four values of wavetable length L ¼ 2I. The simulation parameters correspond exactly to the phase truncated amplitude spectra simulations presented in Figure 5.11.


Amplitude (dBFS)

0

ϕ = 443 I = 10 M = 16 N h = 32 − 6 dB/oct

− 20 − 40 − 60 − 80 − 100 − 120 − 140 − 160

(a) 0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 443 I = 12 M = 16 N h = 32 − 6 dB/oct

− 20 − 40 − 60 − 80 − 100 − 120 − 140 − 160

(b) 0

0.1

0.2

0.3

0.4

0.5

Amplitude (dBFS)

0

ϕ = 443 I = 14 M = 16 N h = 32 − 6 dB/oct

− 20 − 40 − 60 − 80 − 100 − 120 − 140 − 160

(c) 0

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0.3

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0.5

0

Amplitude (dBFS)

194

ϕ = 443 I = 16 M = 16 N h = 32 − 6 dB/oct

− 20 − 40 − 60 − 80 − 100 − 120 − 140 − 160

(d) 0

0.1

0.2

0.3

0.4

0.5

Normalised frequency f f s Figure 5.16 Simulated high frequency linear phase interpolated amplitude spectra over four values

of wavetable length L ¼ 2I. The simulation parameters correspond to the phase truncated amplitude spectra simulations reported in Figure 5.12.

195


160

ϕ = 519227 M = 32 N h = 256 − 6 db/oct

120

120

100

100

80

80

60 40 10

(a) 11

12

13

14

15

16

SNR (dB)

60 40 18

17

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160

ϕ = 519227 M = 32 N h = 256 − 3 db/oct

140

120

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100

80

80

60

60

40 20 10

SFDR (dB)

140

(b) 11

12

13

14

15

16

17

SFDR (dB)

SNR (dB)

140

160

40 20 18

φI (n) bits I Figure 5.17 Simulated linear phase interpolated SNR and SFDR variation with I and hence wavetable length L ¼ 2I. The simulation parameters correspond to the phase truncated SNR and SFDR simulations reported in Figure 5.13.

significant dependence on harmonic roll-off rate for a specific value of I. For the same wavetable function, linear phase interpolation provides steadily increasing SNR improvement with I when compared to the phase truncated case. For example, with a 1k sample wavetable (i.e. I ¼ 10) we observe around 20 dB improvement in SNR between the linearly interpolated and truncated cases, whereas with a 256k sample wavetable (i.e. I ¼ 18) the improvement in SNR is around 70 dB. For our example sawtooth waveform spectrum, wavetable lengths of the order of 4 k and 16 k samples (i.e. I ¼ 12 and I ¼ 14) are needed to achieve SNR comparable with 14-bit and 16-bit quantisation noise, respectively.

5.2.4

Lagrange polynomial phase interpolated wavetable indexing In this section we investigate fractional wavetable addressing by use of Lagrange polynomial phase interpolation. The tutorial presented in Section 5.1.2 outlined the theoretical basis of Lagrange polynomial interpolation as applied to the interpolation of

196


a well-behaved continuous function f (x) tabulated at discrete values of x by constructing a so-called interpolating polynomial. This polynomial locally approximates f (x) on a particular interval and therefore allows us to estimate f (x) at any value of x lying between the tabulated points (i.e. at a fractional table index). In a similar manner, interpolating fractional (i.e. non-tabulated) wavetable values requires construction of an interpolating polynomial that es through each sample within a localised subset of the tabulated samples in the vicinity of the sample to be interpolated. The order-N interpolating polynomial therefore locally approximates the underlying continuous periodic function that is tabulated in the wavetable at N þ 1 discrete phase points that surround the fractional address. This requires a fractional phase representation as defined in Section 4.1.3 and depicted in Figure 4.4 that controls the wavetable addressing and subsequent interpolation computations. Recalling the tutorial of Section 5.1.2, we may now define x in of a phase accumulator output sequence ϕ(n) partitioned into an I-bit integer field ϕI (n) ¼ ϕ(n)/2F and an F-bit fraction field α(n) ¼ ϕ(n)/2F ϕ(n)/2F . Hence we obtain x ¼ ϕ(n)/2F ¼ (ϕI (n) þ α(n)), where ϕI (n) 2 [0, 2I 1] and α(n) 2 [0, 1), which we use to formulate a general expression for phase interpolated wavetable indexing. (For clarity in the subsequent discussion we drop the sequence time-indices, and use ϕI and α to denote the sequences ϕI (n) and α(n), respectively.) Phase interpolated wavetable indexing requires that the order-N Lagrange polynomial defined by Eq. (5.5) and which we now denote by PN (ϕI þ α), takes on an analogous form that is pertinent to DDS AWG: 2

3 N 6 N X Y αj 7 6W½hϕI þ ki I 7: PN ðϕI þ αÞ ¼ 2 4 kj 5 k¼0

ð5:33Þ

j¼0 j 6¼ k

We observe that Eq. (5.33) places the fractional address x ¼ (ϕI þ α) in the first subinterval [ϕI, ϕI þ 1) of the interpolation sample set leading to a non-optimal error magnitude bound as illustrated in Figure 5.2. Accordingly, the address fraction component α spans the sub-interval [ϕI, ϕI þ 1) and assuming a unit-spaced tabulation, sets xj ¼ ϕI þ j in the numerator of Eq. (5.5). Since x ¼ (ϕI þ α), the ϕI cancel leaving (α j) as the numerator term. Optimal positioning of the interpolation sample set with respect to the fractional address interval requires each wavetable index

that we offset and address fraction term in Eq. (5.33) by (N 1)/2 . This always places the fractional address x ¼ (ϕI þ α) in the middle sub-interval of the interpolation sample set for all odd values of N and in the lower sub-interval from the middle sample for all even values of N. Observing modulo 2I indexing, theh optimal phase interpolated

i wavetable read operation is now strictly denoted by W ϕI bðN 1Þ=2c þ k 2I , with k 2 [0, N ]. For a unit-spaced wavetable tabulation, the (xk xj) denominator in Eq. (5.5) reduce to constant integer values (i.e. xk xj k j). Hence, an order-N interpolation polynomial with optimal error bound is given by:


197

13 0 N 1 α þ j N 6 N B X Y C7 N 1 2 B C7: ð5:34Þ 6 þk P N ðϕ I þ α Þ ¼ @ A5 4W ϕI 2 k j I 2 j¼0 k¼0 2

j 6¼ k

Equation (5.34) reduces to linear phase interpolation as given by Eq. (5.32) when N ¼ 1 and rounded down phase truncation when N ¼ 0. The order-N interpolated output sample is therefore given by y(n) ¼ PN (ϕI (n) þ α(n)), where we temporarily use the full discrete-time denotation to aid clarity. To assist the design partitioning of hardware processor implementations in Chapter 8, we may simplify Eq. (5.34) by defining an interpolation coefficient βk(α) that weights each summation term, thus: 1 0 N 1 j N B αþ Y C 2 B C, βk ðαÞ ¼ ð5:35Þ @ A ðk j Þ j¼0 j 6¼ k

where k 2 [0, N ]. We may now express any Lagrange interpolating polynomial as a linear combination of N þ 1 wavetable samples that span the fractional address, each having a unique weighting factor that is a function of the address fraction component α, thus: N X N 1 þk : ð5:36Þ PN ðϕI þ αÞ ¼ βk ðαÞW ϕI 2 2I k¼0 We illustrate application of these expressions by considering the cubic Lagrange interpolation polynomial and hence set N ¼ 3. This interpolates the fractionally addressed wavetable sample at (ϕI þ α) using the four sample set {W[ϕI 1], W[ϕI], W[ϕI þ 1], W[ϕI þ 2]}. (Strictly speaking, the wavetable is indexed modulo 2I and so W[ϕI a] is properly denoted as W½hϕI ai2I , where a is an integer offset. However, we further relax denotation rigour in the interests of clarity and use the W[ϕI a] form where the modulo indexing is assumed.) Figure 5.18 illustrates the optimal placement of the fractional address interval relative to the wavetable sample set for the cubic Lagrange interpolation polynomial. We therefore have four that are linearly combined according to the address fraction component α: P3 ðϕI þ αÞ ¼ β0 ðαÞW½ϕI 1 þ β1 ðαÞW½ϕI þβ2 ðαÞW½ϕI þ 1 þ β3 ðαÞW½ϕI þ 2

ð5:37Þ

From Eq. (5.35) the four interpolation coefficients βk(α) are each cubic polynomials in α alone and defined by β0 ðαÞ ¼ 16 αðα 1Þðα 2Þ, β1 ðαÞ ¼ 12ðα þ 1Þðα 1Þðα 2Þ, β2 ðαÞ ¼ 12 αðα þ 1Þðα 2Þ and β3 ðαÞ ¼ 16 αðα þ 1Þðα 1Þ. In general, an order-N interpolation polynomial has N þ 1 linearly combined , each corresponding to a unique wavetable read operation and interpolation coefficient. The interpolation coefficients are each a unique Nth-order polynomial in α and must be computed for each value of α (i.e. each new fractional address). This represents a

198


P3 (φ ) W[φI + 2] f (φ )

W[φ I + 1] f (φI + α )

W[φ I ] W[φI − 1]

α φI − 2

φI (φ I + α ) φI + 1

φI − 1

⎢ φ ( n) ⎥ F ⎣ 2 ⎥⎦

φI ≡ φ I ( n) = ⎢

α ≡ α ( n) =

φI + 2

φI + 3

φ F ( n) 2F

Figure 5.18 Optimal placement of the fractional address (ϕI þ α) for the cubic interpolation polynomial. The underlying third-order interpolating polynomial is denoted by P3(ϕ).

significant computation burden as measured by the number of multiply operations. Alternatively, a unique lookup table for each βk term may be used. Each lookup table is indexed by ϕF (n) and so requires 2F locations. Odd-order interpolation is generally preferred as the corresponding even number of wavetable read operations is easier to implement in high speed parallel memory architectures. We consider interpolation processing overhead and hardware implementation in Chapter 8 where we present a novel parallel memory structure that s high speed wavetable phase interpolation. We now present simulated performance results for several orders of polynomial phase interpolation. Figure 5.19 illustrates simulated amplitude spectra for odd orders of phase interpolation with I ¼ 10. Figures 5.19a and 5.19b include amplitude error spectra for the I ¼ 12 case where we observe a reduction of around 20dB in the peak amplitude of the error spurs when compared to the I ¼ 10 case. The test spectrum corresponds to a 256 harmonic approximation of a sawtooth waveform (i.e. –6 dB/octave harmonic roll-off) synthesised at low frequency with φ/2M ¼ 7/216. We observe error spur groupings across the entire Nyquist band which are images of the waveform fundamental harmonics and whose amplitude reduces with increasing interpolation order. Setting I ¼ 12 with cubic phase interpolation suppresses amplitude error spurs (i.e. increases SFDR) to a level comparable with 24-bit quantisation noise. Figures 5.20 and 5.21 illustrate the SNR and SFDR variation with interpolation order and I for two harmonic roll-off slopes. These simulations use a more representative phase accumulator word size of M ¼ 32 and a 256 harmonic wavetable spectrum. As in the M ¼ 16 case, a 64k (i.e. 216) sample FFT is used to compute the amplitude spectrum.

199


Amplitude (dBFS)

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Normalised frequency f f s Figure 5.19 Simulated amplitude spectra for several odd orders of Lagrange polynomial phase interpolation. Plots (a) and (b) show overlaid amplitude error spectra for I ¼ 12.


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Interpolation order N Figure 5.20 Simulated SNR variation with interpolation order N and I for four wavetable spectra. (Numerical denotation against each trace indicates the value of I.)


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6

Interpolation order N Figure 5.21 Simulated SFDR variation with interpolation order and I for four wavetable spectra. (Numerical denotation against each trace indicates the value of I.)


We observe that SNR improves at an approximately fixed rate with interpolation order and the slope of the SNR/N plot increases with I. Figure 5.22 illustrates simulated contours of constant SNR over variation in I and phase interpolation order for a 256 harmonic wavetable function with 6 dB/octave roll-off. We observe that a required SNR specification can be achieved by trading I with phase interpolation order N. For example, an SNR of 140 dB (i.e. comparable with 24-bit quantisation noise) can be achieved using linear phase interpolation and I ¼ 17 or cubic phase interpolation and I ¼ 13. Increasing to an order-5 phase interpolation only produces a one bit reduction in I. In general, we deduce that as the phase interpolation order increases, SNR variance with I reduces. For order-5 phase interpolation, SNR values from 180 dB to approximately 70 dB occur with I ranging from 10 to 13 (i.e. wavetable lengths of 1k to 8k samples). In contrast, for linear phase interpolation, similar SNR variation occurs with I ranging from 10 to 20 (i.e. wavetable lengths of 1k to 1M samples). Similar behaviour is observed with SFDR variation. Finally, we demonstrate how SNR varies with the number of equal amplitude harmonics in the wavetable spectrum (i.e. 0 dB/octave harmonic roll-off rate). This represents a severe waveform test spectrum since the higher harmonics contribute

20

ϕ = 519227 M = 32 N h = 256 − 6 db/oct 19 18 17

Integer phase bits I

202

16 15 180

160

14 120

140

13 100

80

12 60

11 40

10 0

1

2

3

4

5

6

7

Interpolation order N Figure 5.22 Simulated contours of constant SNR over variation in I and phase interpolation order N for a 256 harmonic wavetable function with 6 dB/octave harmonic roll-off.

5.3 Analogue waveshaping

203

increased magnitude error spurs in the amplitude spectrum. Figure 5.23 illustrates the simulated variation of SNR with the total number of wavetable harmonics Nh over four values of I and with phase interpolation order N ranging from 1 to 5. We observe that phase interpolation order makes little difference for large Nh when wavetable length is small. However, as wavetable length increases, SNR improves significantly with N for all values of Nh. For example, when Nh ¼ 256 and I ¼ 16 we obtain SNR comparable with 16-bit quantisation noise using only linear phase interpolation. For any value of Nh, the SNR improvement obtained by increasing N increases dramatically with I and hence wavetable length. In this section we have investigated several important phase interpolation algorithms from simple phase truncated (i.e. zero-order) interpolation to high-order Lagrange polynomial interpolation. For completeness, we have also included phase dithered amplitude mapping. In all cases we have demonstrated the effectiveness of interpolated or dithered phase–amplitude mapping with multi-harmonic waveforms when compared to the purely phase truncated case. We summarise the following important results from the simulations presented: when I ¼ M and hence F ¼ 0, we have optimal phase–amplitude mapping irrespective of the wavetable spectrum; truncated phase–amplitude mapping (i.e. I < M ) causes error spurs in the amplitude spectrum and hence non-optimal SNR and SFDR; the fractional phase representation that is implicit with phase truncation enables interpolation of the phase–amplitude mapping process thereby reducing the magnitude of error spurs in the amplitude spectrum; for a given phase interpolation order N, SNR and SFDR increase with I and hence wavetable length; for a given value of I and hence wavetable length, SNR and SFDR increase with interpolation order N; both the SNR–N and SFDR–N relationships are approximately linear with slope that increases with I; the change in SNR and SFDR with I is approximately 6(N þ 1) dB/bit for any phase interpolation order and wavetable spectrum; the slope of both the SNR–N and SFDR–N relationships increases as Nh reduces; generally, SNR and SFDR always reduce with increasing Nh.

5.3

Analogue waveshaping In this section we outline the generation of two classic piecewise linear ‘analogue function’ waveforms using phase accumulating frequency synthesis combined with integration of an amplitude compensating control current. We only present outline conceptual designs that are sufficient to enable the suitably experienced reader to develop these into hardware or software implementations against specific requirements. In this application, we view the phase accumulator as a programmable digital frequency


150

3

SNR (dB)

130

ϕ = 519227 I = 10 M = 32 0 db/oct

5

4

2

110 90

1

70 50 30

(a)

10 0

32

64

96

128

160

192

224

256

150

5

SNR (dB)

130

4

110

3

90

2

70

1

50

(b)

30

ϕ = 519227 I = 12 M = 32 0 db/oct

10 0

32

64

96

128

160

192

224

256

150

3

SNR (dB)

130 110

2

90

1 70 50

(c)

30

ϕ = 519227 I = 14 M = 32 0 db/oct

10 0

32

64

96

128

160

192

224

150

256

2

130

SNR (dB)

204

110

1

90 70 50

(d)

30 10

0

ϕ = 519227 I = 16 M = 32 0 db/oct 32

64

96

128

160

192

224

256

Number of harmonics N h Figure 5.23 Simulated variation of SNR with Nh over four values of I. All harmonics in the

wavetable spectrum have equal amplitude, representing a worst case test spectrum. Plot numerical identifiers denote the phase interpolation order N.


205

synthesiser ‘block’ that generates a pulse waveform whose frequency is effectively a fractional division of the sample frequency. Unlike our preceding discussions, there is no explicit use of phase information to map to the amplitude domain. After reviewing the phase accumulator as a fractional divider, we investigate methods for generating sawtooth and triangle function waveforms using the phase accumulator carry9 output pulse as a timing reference. This analogue waveshaping technique exploits two fundamental properties of the phase accumulating frequency synthesiser – exact linearity and wide dynamic range. In general, this approach offers several advantages when compared to the all-digital method, which include: simpler waveshaping hardware; sawtooth and triangle waveforms can be generated directly with very high slope linearity and in continuous time; no Nyquist constraint on waveform bandwidth; wide frequency control dynamic range; arbitrarily fine frequency control resolution consistent with phase accumulation frequency synthesis. It is apparent that the techniques presented here are readily adaptable to generate more complex piecewise-linear (PWL) waveforms without loss of the above advantages. Finally, we should also mention some distinct disadvantages with this approach: reduced waveform complexity and waveshape control flexibility; wide dynamic range analogue design is required to ensure waveform amplitude and shape stability with frequency; closed-loop stability considerations in the case of the triangle waveshaper.

5.3.1

The phase accumulator as a digital frequency synthesiser The phase accumulator can be viewed as a digital frequency synthesiser with arbitrarily fine frequency control resolution and an inherently linear control characteristic. The phase accumulator carry output pulse has an average frequency given by φfs/2M and is always one sample clock period wide. The carry output exhibits period jitter or uncertainty in the position of the pulse relative to the previous pulse. The amplitude of this jitter (measured in of the output period) is exactly one sample clock period. Of course, this period jitter may be interpreted as an equivalent frequency jitter where the phase accumulation process causes the jitter distribution over time to be such that the long-term average frequency is exactly φfs/2M. The most significant bit (MSB) of the M-bit phase word is a quasi-square wave signal with identical period jitter to the carry output and a maximum frequency of fs/2. The phase accumulator may therefore be viewed as a programmable digital divider that divides the reference sample frequency by the rational fraction φ/2M 9

The carry output of a phase accumulator we define as the carry output of the most significant adder stage. Assertion of the carry signal indicates phase accumulator overflow.

206


according to the phase increment φ. Although the phase accumulator uses a fixed reference sample clock, use of the carry output as our synthesised frequency within an analogue waveshaping system is properly referred to as a variable sample rate system. When φ/2M takes on radix-2 fractions (e.g. 12, 14, 18, etc.) the output frequency is always jitter-free and consecutive cycles have identical period. When φ/2M takes on irrational values (e.g. 13, 17, etc.) the phase accumulator can be viewed as a ‘dynamically variable’ divider that alternately divides the sample frequency by the integers φ/2M and φ/2M such that the long-term average value approaches the exact irrational value of φ/2M. For example, if we let M ¼ 12 and φ ¼ 257, we have φ/2M ¼ 257/4096 which clearly evaluates to an irrational value. The division factor is simply the reciprocal value 4096/257 15.938. . . and so the phase accumulator alternately divides by 15 and 16 to ensure that the long-term average division ratio converges to 4096/257. In other words, over 1000 sample clocks the phase accumulator divides by 15 for 62 clocks and 16 for 938 clocks yielding an average division value of 15.938. The peak-to-peak period jitter is fixed at 1/fs and can be made arbitrarily small by selection of a suitable phase accumulator sample frequency, bounded only by the speed of the phase adder and accumulator technology. The relative jitter error, which we define as the ratio of jitter amplitude to synthesised period, therefore increases with frequency and reaches a maximum when φ ¼ 2M1 1. The relative jitter error is reduced by dividing the phase accumulator output by an integer value which reduces the maximum output frequency in direct proportion. This also reduces the maximum synthesisable frequency relative to the sample frequency. For example, a J-bit binary counter whose most significant bit is taken as the synthesised frequency output and which is enabled to count by the phase accumulator carry output, reduces the maximum output frequency to fs/2Jþ1. The peak-to-peak jitter as a fraction of output period is therefore reduced by 2J at the expense of reduced maximum frequency. We observe that the output frequency is now φfs/2MþJ and hence the maximum frequency is fs/2Jþ1 and the frequency control resolution (or equivalently the minimum synthesisable frequency) is fs/2MþJ. A simple example is useful to help clarify application of this technique. Suppose we require a digitally programmable frequency whose maximum value is at least 1 MHz, with a control resolution of exactly 0.1 Hz and a peak-to-peak jitter of better than 10 ns. From our previous discussion we then have fs/2MþJ ¼ 0.1, fs/2Jþ1 1 MHz and fs 100 MHz. Taking the first expression and setting M þ J ¼ 30 gives fs; 107.374 MHz, which satisfies both the frequency control resolution and jitter requirements. From the maximum frequency expression we determine that J ¼ 5 and hence M ¼ 25. The maximum output frequency is therefore approximately 1.678 MHz, which exceeds requirement and occurs when φ ¼ 224 1. The design therefore comprises a 25-bit phase accumulator and 5-bit fixed jitter divider with φ 2 [1, 224 1]. The most significant bit (MSB) of the 5-bit divider is a square wave signal with a peak-to-peak jitter amplitude of around 9 ns (i.e. 1/fs). We observe that increasing fs to 1.07374 GHz increases the maximum output frequency to 16.78 MHz, and reduces timing jitter tenfold to less than 1 ns.


5.3.2

207

Analogue waveshaping principles and some fundamental problems There are several fundamental concepts that underpin the analogue waveshaping techniques presented in this section: using a phase accumulating frequency synthesiser to control the systematic integration of a control current to generate piecewise-linear waveforms; compensating waveform amplitude variation with frequency by proportioning the integration rate to the phase increment parameter; converting the phase increment to an analogue voltage (or current) over a wide dynamic range consistent with large values of M; incorporating switched integrator gain as part of the phase increment conversion. In the simplest scenario, we arrange for an integrator to be periodically reset at the synthesised frequency and thereby generate a linear sawtooth waveform at the output of the integrator. If we integrate a fixed reference current and reset the integrator on each rising edge of the jitter counter MSB, the amplitude of the resultant sawtooth waveform will reduce linearly with increasing frequency. We may, of course, compensate this behaviour by arranging for the integration current to increase linearly with phase increment and therefore frequency. On each rising edge of the jitter counter MSB, the integrator is reset by a fixed width pulse generated by an analogue monostable or digital equivalent. The width of this reset pulse is a design parameter that is a function of the required reset time, integration capacitance and reset method (e.g. resistive discharge or fast constant current integration to the reset state). The integration current is generated by a D-bit DAC which converts the phase increment into a linearly proportional voltage and whose control word we denote by φD. Figure 5.24 illustrates a hypothetical sawtooth analogue waveshaper using this principle incorporating an inverting operational amplifier integrator. ϕ fs 2M

J-bit counter

MSB

ϕ fs 2M + J

Monostable

0

ϕ

M −1 M

tr

fs

co

z-1

∑

Ci M

Ri DAC

D

ii

Vref

− +

0 − Va

Figure 5.24 Periodically resetting an integrator to generate sawtooth waveforms.

208


Since the Nyquist frequency is the highest frequency usefully generated by an M-bit phase accumulator, we observe that only M 1 phase increment bits are required. Therefore, the maximum value of the compensating DAC word size is D ¼ M 1. The phase accumulator and jitter counter combination can therefore be viewed as a ‘black box’ frequency synthesiser, with M bits of control resolution, but only an M 1 bit frequency control word (i.e. phase increment) consistent with generating frequencies up to fs/2. It is a generally accepted tenet of wide range analogue circuit design that currents are often preferable to voltages as control signals. In an ideal implementation, we would therefore use a current-output DAC feeding the inverting operational integrator summing node directly. This reduces susceptibility to integrator input offset voltages and their temperature coefficients, assuming the amplifier input bias current can be made sufficiently small so as not to cause a significant offset error. However, this level of design detail is beyond the scope of this book and we do not consider it further. All we present here is a conceptual implementation that forms the basis of a detailed circuit-level design. For our present illustrative discussion, we assume that φD ¼ φ (i.e. D ¼ M 1) and so the DAC and phase accumulator have equal dynamic range. Assuming a perfectly linear DAC, the integration current ii is then given by ii ¼ kφD, with φD 2 [0, 2D 1] and k is a scale factor governed by the DAC reference voltage and integrator input resistance. Typically, we have k ¼ Vref/(Ri2D), where Vref is the DAC reference voltage and Ri is the integrator input resistance. (We also assume that the DAC and integrator have zero DC offset voltage, which is not necessarily true in practice and must be corrected for.) The peak integrator output voltage Va at the end of each cycle just before reset is then given by Va ¼ iiτ/Ci, where Ci is the integration capacitance and τ ¼ 2MþJ/ φfs (i.e. the period of the phase accumulator output frequency). Hence, Va is the amplitude of a periodic sawtooth waveform whose frequency is determined by the phase increment φ alone. If we substitute for ii in the expression for Va we obtain Va ¼ k2MþJ/Cifs and observe that it is constant and most importantly, independent of φ. Substituting for k we obtain Va ¼ Vref 2MþJ/(RiCi fs). In typical implementations, M soon exceeds the practicable DAC resolution and the corresponding analogue design challenge in the DAC and integrator increases significantly. For the purposes of this discussion, we therefore assume that D 16. In the simple frequency synthesiser design example outlined at the end of Section 5.3.1, we obtained M ¼ 25 and J ¼ 5. We therefore have to truncate the 24-bit phase increment to 16-bits or less to generate the amplitude compensation voltage. In the simplest case, the DAC

MD1 input is taken from the D most significant bits of the M 1 bit φ (i.e. φD ¼ φ/2 ). This immediately imposes two serious limitations on performance: the sawtooth amplitude is no longer invariant with φ; there is now a minimum threshold value of φ (and hence frequency) below which the waveshaper will stop functioning due to the DAC output being driven to zero. When D < M 1, the sawtooth amplitude is given by: Va ¼

V ref j φ k 2M þJ , 2D 2M D1 φRi C i f s

ð5:38Þ

209

Normalised amplitude Va


1 0.8

2 M −D −1

0.6 0.4 0.2 0 10

100

10

3

10

4

10

5

10

6

10

7

Phase increment ϕ Figure 5.25 Variation in sawtooth amplitude Va with φ for M ¼ 25 and D ¼ 12. Observe the

operating threshold is located at 2MD1 ¼ 4096.

which we plot in Figure 5.25 illustrating the normalised variation in Va with φ for M ¼ 25 and D ¼ 12. Increasing oscillatory amplitude variation is observed with reducing φ until a low frequency threshold point where the amplitude drops to zero. This threshold occurs when φ ¼ 2MD1. As D increases and approaches M, the amplitude variation reduces and the curve of Figure 5.25 is simply translated to the left (i.e. the amplitude variation occurs at lower frequencies). In principle, the low frequency amplitude variation could be removed by an ‘amplitude levelling loop’ that servo-stabilises the sawtooth amplitude in a similar manner to that used in the Wien bridge or state variable analogue oscillators discussed in Section 1.3. However, loop settling time with this approach generally increases at lower operating frequencies and may not be practicable in most applications. We can significantly reduce amplitude variation with frequency and eliminate the low frequency cut-off by using a ‘floating point’ representation for the amplitude compensation mechanism. The D-bit DAC control word is now aligned with the phase increment according to the absolute phase increment value. For example, when φ 2 [1, 2D 1], the D-bit DAC control word is aligned with the D LSBs of the phase increment and no information is lost. If φ 2 [2D, 2Dþ1 1] the D-bit DAC input word φD is obtained from the next D LSBs of the phase increment by left-shifting φD with respect to φ. As φ increases, the D-bit DAC input word is progressively leftshifted relative to φ. In general, for φ 2D the required number of left shifts r is given by r ¼ ⌊ log2 (φ)⌋ D þ 1, and for φ < 2D r ¼ 0. For each left shift, the DAC output spans the same voltage range over φ and so we must halve the integrator gain to maintain sawtooth amplitude. For a typical operational integrator, this is accomplished by simply halving the integrator capacitance Ci for each left shift of the DAC control word relative to φ. In a floating point interpretation, the DAC output therefore represents the mantissa and the shift position (i.e. integrator gain) represents the exponent.


ϕ fs 2M

ϕ fs 2M + J

5-bit counter

Monostable

1

z-1

∑

Ci 4096

25

24

4-16 decode

4

.....

ϕ

tr

fs

co

24

24

.....

210

Ci 8

Ci 4

13

Ci 2 r Barrel shifter

Ri

ϕD

DAC

12

ii

Ci − +

0

Vref

− Va

ϕ ∈ [ 2 D+11, 2 D+12 − 1] Increasing ϕ M = 25 ϕ D = 12 ϕ D

ϕ ∈ [0, 2 D − 1]

r bit shift

ϕ ∈ [ 2 D , 2 D+1 − 1]

Figure 5.26 An improved sawtooth waveshaper using a floating point DAC and integrator.

If we assume M ¼ 25 and D ¼ 12, there are 13 possible DAC shift positions and hence 13 possible integrator gain settings spanning the range Ci, Ci/2, Ci/4 . . . Ci/4096 in order of increasing frequency for r 2 [0, 12]. This can be accomplished with 13 binary weighted integrator capacitors individually switched as illustrated in Figure 5.26, which also depicts an outline of the floating point DAC data representation relative to φ. The barrel shifter block computes two output signals from φ – the 12-bit DAC control word φD and a binary number representing the number of left shifts r that are required to satisfy φ 2 [2Dþ(r1), 2Dþr 1] for r 1. A 4–16 decoder (or demultiplexer) converts r into M D discrete control signals which set the integration capacitance. In our example design, r is a 4-bit binary value and M D ¼ 13. In general, we observe that r 2 [0, M D 1].

211


1

2D 0.9995

2 M −1 0.999 10

100

10

3

10

4

10

5

10

6

10

7

10

8

Figure 5.27 Normalised amplitude error with floating point DAC and switched gain integrator

compensation.

Assuming an inverting operational amplifier integrator, the sawtooth waveform amplitude is then given by: Va ¼

V ref j φ k 2M þJ 2r : 2D 2r φRi C i f s

ð5:39Þ

Figure 5.27 illustrates the normalised amplitude variation with φ for our design example. Maximum amplitude error is now reduced to 0.05% and there is no low frequency cut-off threshold. In essence, the digital to analogue conversion process is now split between the DAC and a switched gain integrator allowing design optimisation for specific requirements.

5.3.3

Triangle waveform shaping We may generate a triangle waveform by integrating the square wave output from the MSB of the phase accumulator jitter divider. In the simplest embodiment, the state of the square wave signal controls the slope of the integration process whose rate is compensated with φ to maintain constant amplitude in a similar manner to the sawtooth case. If the integration rate is designed so that it always reaches full amplitude in exactly one half period, a triangle waveform is generated at the output of the integrator. An ‘open-loop’ integrator is unsuitable here as it will also integrate any residual non-zero mean value in the square wave signal and thereby cause a drift in the mean of the triangle waveform. In principle, this drift can be prevented by placing the integrator inside a servo loop which forces the integrator output to equal a set-point input in the steady state. In effect, we now have a controlled slew rate limiter, where the integrator RC time constant sets the slew rate. This arrangement is conceptualised in Figure 5.28 where we include a multiplying current-output DAC (MDAC) to control the integration rate.

212


ϕ fs 2M

J-bit counter MSB

ϕ

M −1

M −1

fs

co

Level shifter z-1

∑

2M +J ϕ fs + Va

M ± ii MDAC

D

− Va

Ci − +

− A1

+

A2

Vref

+ Va − Va Figure 5.28 A conceptual amplitude compensated triangle waveshaper. The arrangement is similar to the sawtooth case except we now incorporate the integrator within a stabilising servo-loop. For simplicity, we show the case where D ¼ M1. Alternatively, the amplitude compensation scheme of Figure 5.26 may be used.

The MDAC can effectively be modelled as a digitally controlled resistor RDAC from the Vref input to the current-output port. A1 is an integrating amplifier which integrates the MDAC output current. The integrator output is compared with the set-point input voltage using an error amplifier A2 to generate an error signal which servos the MDAC reference input. The MSB of the phase accumulator jitter counter is level shifted to produce a precise square waveform with amplitude Va and frequency φfs/2MþJ. As in the simple sawtooth waveshaper case, we assume φD ¼ φ and so D ¼ M. If the integrator RDACCi time constant is chosen correctly, we generate a symmetrical triangle wave of amplitude Va at the output of the integrator whose waveshape is maintained with frequency. We may readily apply the floating point DAC and switched integrator technique to reduce amplitude variation under the practicable condition D < M. Finally, we observe that this is only a conceptual description and hardware implementation will require careful consideration of the servo loop stability taking of the embedded MDAC, particularly if required to operate at higher frequencies.

5.4 DDS clock generation

5.4

213

DDS clock generation In many digital signal processing applications there is a requirement for a clock source having programmable frequency, pulse-like waveshape with a consistent duty-cycle (e.g. 50%) and most importantly low jitter (i.e. low phase noise). There are several approaches to DDS clock generation reported in the literature:

pulse output phase accumulator fractional divider; ‘pulse swallowing’ DDS; phase interpolating DDS; phase dithered DDS; ‘hard-limited’ sinusoidal DDS.

So-called hard-limited sinusoidal DDS is capable of satisfying all of these requirements, in addition to providing instantaneous frequency transitions, 2M1 1 discrete frequencies across the Nyquist interval and an arbitrarily small, fixed frequency control resolution of fs/2M. The absolute lower bound on DDS clock jitter is set by the intrinsic jitter of the reference sample clock source. Before investigating this approach further, we briefly outline some alternative DDS based clock generation techniques reported in the literature. The phase accumulator fractional divider, as discussed in the introduction to Section 5.3, is the simplest technique to implement, but fundamentally constrained by having an absolute output jitter amplitude which is inherently fixed at one sample clock period peak-to-peak [7]. Low jitter clock generators using this approach therefore require a high sample clock frequency to control the absolute jitter performance or a reduced maximum frequency specification to ensure an acceptable relative jitter performance (i.e. jitter amplitude as a fraction of the synthesised period). Dividing the phase accumulator output by a fixed integer value reduces the maximum output frequency relative to the sample clock frequency and produces an improvement in relative jitter performance equal to the division factor. The so-called ‘pulse swallowing’ or fractional divider DDS technique [7] uses the phase accumulator carry output pulse to control a divide by n or n þ 1 counter so that division by n þ 1 occurs on a carry. The accumulator is, in turn, clocked by the output of the divider counter setting the n þ 1 divide state for the next output of the divider after the carry occurs. The divider is clocked by the sample clock and the output frequency is taken from the output of the divider and defined by fo ¼ fs/(n þ φ). In this context, the phase increment φ is interpreted as the fractional part of the divisor with n the integer part. However, jitter performance is similar to that of the phase accumulator fractional divider. So-called phase interpolating10 DDS [8] provides reduced jitter, but without the overhead of sinusoidal phase–amplitude mapping. This technique exploits a

10

This nomenclature is widely used in the literature and is not to be confused with phase interpolated fractional addressing of a wavetable.

214


fundamental property of phase accumulation where the value of the phase sequence ϕ(n) is always proportional to the phase difference between a carry output transition and an ideal reference frequency source. Accordingly, ϕ(n) can be used to phase shift (or delay) a pulse output phase accumulator or pulse swallowing DDS and thereby reduce jitter. The digitally controlled phase shift can be implemented by either digital or analogue means – the latter incorporating a PLL wherein a DAC controlled by ϕ(n) sets a voltage offset into the PLL VCO. Jitter levels are ultimately bound by the error characteristics of the DAC function. Phase dithered DDS takes many forms, but all endeavour to eliminate periodicities in the phase sequence ϕ(n) and hence reduce jitter in the carry output pulse transitions or, equivalently, spurious components in the DDS output spectrum. This requires an addition of a small pseudo-random value to the instantaneous truncated phase accumulator value prior to phase–amplitude mapping [9]. In Section 5.2.2 we have illustrated the beneficial effects of phase dithering in eliminating spurious spurs in the DDS output spectrum at the expense of an elevated noise floor across the Nyquist bandwidth. Hard-limited sinusoidal DDS is advantageous compared to the all-digital pulse output form since it uses some of the ϕ(n) information to generate a sinusoid. This sinusoid is subsequently band-limited to further reduce residual phase truncation errors and then hard-limited in amplitude to generate a square waveform. Error spurs in the sinusoid amplitude spectrum are manifest as jitter in the time domain and so reducing their magnitude through phase–amplitude mapping and band-limiting reduces jitter in the hard-limited sine waveform. In the limit, with optimal or near-optimal phase–amplitude mapping (e.g. L ¼ 2M or suitable phase interpolation) the spurious energy in the error spectrum becomes dominated by sample clock jitter, DAC non-linearities, reconstruction filter noise and ultimately intrinsic comparator switching point jitter due to thermal noise. These mechanisms set a lower bound on overall jitter performance and can only be minimised. Several commercially available sinusoidal DDS devices [10] now include an on-chip comparator to facilitate square wave clock generation from the sinusoidal DDS output. These devices require off-chip analogue low- (or band) reconstruction filtering prior to hard-limiting.

5.4.1

Hard-limited sinusoidal DDS Hard-limiting describes the conversion of a sine wave (or indeed any continuous waveform function) to a square or rectangular wave using a comparator and suitable reference voltage – in essence, a 1-bit analogue to digital convertor or quantiser. Figure 5.29 illustrates the architecture of a hard-limited sinusoidal DDS clock generator. In this example we assume a simple non-interpolated phase–amplitude mapping stage. We have already seen that sinusoidal DDS generates a complex distribution of erroneous frequency components across the Nyquist interval whose magnitude depends on the phase–amplitude mapping algorithm and φ. These frequency components are manifest as jitter in the square waveform that is generated by hard-limiting the sine

215

5.4 DDS clock generation

fs

ϕ

M z-1

∑

I

Sine wavetable

Reconstruction filter

DAC

+ −

fo =

ϕ fs 2M

M

Jitter t j T

0.1

1000

0.01

100

0.001

10

1

0.0001

0.00001 − 20

− 30

− 40

− 50

− 60

− 70

− 80

Jitter (ps) fs = 100 MHz

Figure 5.29 A hard-limited sinusoidal DDS clock generator.

0.1

Amplitude error spur magnitude (dBc) Figure 5.30 The ratio of timing jitter to sample clock period tj/T as a function of cumulative error

spectrum spur amplitude. The right hand axis shows the absolute jitter relative to a 100 MHz sample clock.

wave fundamental. An expression relating the peak-to-peak jitter amplitude tj and the amplitude of the DDS non-harmonic amplitude spectrum error spurs εi is reported in [11] and given by ! N sp X T εi , ð5:40Þ t j ¼ tan1 π i¼1 where T denotes the sample clock period, Nsp is the number of error spurs in the bandwidth of interest and εi is the amplitude of the ith spur normalised to a unitamplitude carrier. Clearly, the cumulative spur amplitude represented by the summation term in Eq. (5.40) generally increases with the number of lines in the error spectrum and leads to increased jitter. Figure 5.30 illustrates the relationship between the ratio of peak-to-peak jitter tj to sample clock period T and the cumulative error spur amplitude expressed in dBc (i.e. εi in Eq. (5.40) expressed as εi ¼ 10 Ai =20 , where Ai represents the ith spur amplitude expressed in dBc).

216


Figure 5.30 also includes the absolute jitter amplitude for the specific case where fs ¼ 100 MHz and hence T ¼ 10 ns. This figure can be interpreted in two ways: either as a relationship between a single dominant error spur amplitude and the jitter ratio, or the cumulative amplitude of all the error spurs within a specific bandwidth expressed in dBc.

5.4.2

Reconstruction filter bandwidth The bandwidth of the DDS sinusoidal spectrum sets the overall error spectrum energy and hence jitter after hard-limiting. Clearly, a wider frequency control dynamic range requirement corresponds to increased signal bandwidth and hence jitter amplitude. Frequency control dynamic range and jitter amplitude are therefore a fundamental design trade-off with hard-limited DDS architectures. However, low noise sinusoidal phase–amplitude mapping algorithms tend to mitigate this trade-off to some degree. For a given sample clock phase noise specification, jitter performance is now determined predominantly by the DAC, reconstruction filter stop-band attenuation and comparator switching threshold jitter. If we hard limit the DDS sine wave without reconstruction band-limiting, the edge jitter amplitude will always be bounded at 1 sample clock period peak-to-peak. This is due to the sampled DDS sine wave containing many extraneous frequency components above the Nyquist frequency. By applying low- reconstruction filtering to suppress these extraneous spectrum components, we observe a significant reduction in edge jitter amplitude after hard-limiting. However, even with an ideal low- reconstruction filter that removes all extraneous energy above the Nyquist frequency, we still observe residual jitter due to the effects of in-band erroneous amplitude spectrum spurs due to phase truncation. The objective in DDS clock generator design is to ensure that the phase–amplitude mapping algorithm (including DAC and reconstruction filter effects) is sufficiently exact to cause residual jitter to be bound by comparator performance and intrinsic phase noise in the sample clock source. Reference [12] provides a useful discussion of DDS clock generator design based upon the Analog Devices range of DDS components, but the material presented is sufficiently generic to be applied to bespoke designs. If we need to synthesise a low jitter clock signal whose frequency only spans a subband of the Nyquist interval, we can optimise the reconstruction filter bandwidth accordingly and realise an improvement in jitter performance. The reconstruction filter now takes on a band- response with a centre frequency and bandwidth that match the required frequency control range. The transition slopes and stop-band attenuation optimise DDS error spur suppression in the operating bandwidth and are a function of the filter type and order. This approach retains all of the key advantages of DDS (i.e. instantaneous frequency transition and arbitrarily fine frequency control resolution), but now over a reduced frequency control dynamic range that is optimised to the application and minimises jitter. A development of this approach uses a band- reconstruction filter whose centre frequency tracks the DDS phase increment. This provides the reduced jitter benefits of lower bandwidth, but wider frequency control dynamic range. However, the implementation of such a tracking filter is a non-trivial design undertaking.

5.5 Variable sample frequency AWG

217

We may adapt a computer simulation of the sinusoidal DDS amplitude error spectrum to estimate the jitter performance as a function of reconstruction filter bandwidth. This is accomplished by arranging the summation in Eq. (5.40) to span an appropriate sub-band of the error spectrum. Each of the εi is then taken from the appropriate sub-band of the amplitude spectrum. A closer approximation may be obtained if we for non-ideal filter behaviour and include the effects of finite stop-band attenuation. However, such an approach does not include the intrinsic jitter performance of the sample clock source and the comparator and must be ed for separately.

5.5

Variable sample frequency AWG All of the waveform generation algorithms presented so far have operated at a fixed sample frequency and therefore execute their arithmetic and DAC processing at a constant rate. However, there is an alternative waveform generation technique where the waveform frequency is controlled by varying the sample frequency directly. The sample frequency is typically a fixed integer multiple of the required waveform frequency, and so frequency control dynamic range is determined by the variable sample frequency source alone. In this section we outline a hypothetical architecture that serves to illustrate the key concepts of this approach. Our example architecture comprises a phase accumulating frequency synthesiser clocking a unit-increment phase counter that indexes a wavetable tabulating an arbitrary waveform function. The wavetable output samples are fed to a DAC and reconstruction filter which must now operate at a variable sample frequency (i.e. the cut-off frequency must ideally track the variable sample rate). Alternative approaches employ a variable analogue oscillator or low jitter DDS clock generator combined with a PLL frequency multiplier to generate the sampling frequency.

5.5.1

Basic architecture and implementation limitations Figure 1.10 presented in Section 1.2.5, illustrates a conceptual variable sample rate AWG. In essence, a variable frequency oscillator clocks a unit-increment phase counter that addresses a wavetable containing the periodic waveform to be generated. The wavetable feeds a DAC and reconstruction filter, which generates the continuous-time waveform. In Section 5.3 we saw how the phase accumulator could be viewed as a standalone frequency synthesiser that generates variable frequency pulse waveforms with an inherent worst case jitter amplitude of one sample clock period peak-to-peak. Dividing the phase accumulator output by a fixed radix-2 value reduces the relative jitter error at the expense of a proportionally lower maximum frequency. The J-bit jitter reduction counter is therefore clocked at a variable sample frequency given by φfs/2M and produces a periodic unit-increment sawtooth phase sequence of frequency φfs/2MþJ with φ 2 [1, 2M 1 1]. Alternatively, we could have used a DDS clock generator as discussed in Section 5.4 to generate the variable sample frequency with much lower

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jitter. However, the frequency control dynamic range requirement is now much wider. The J-bit ‘jitter counter’ is now viewed as a phase counter which indexes a wavetable and where the above frequency expressions still apply. The periodic sawtooth phase sequence is converted to an arbitrary waveform amplitude sequence by using a wavetable tabulating the required waveform function, exactly as in the constant sample frequency case. However, waveform samples are now generated and fed to the DAC at a variable sample frequency, which leads to several important distinctions: the generated waveform always comprises 2J samples per cycle, irrespective of frequency; the rate at which samples are fed to the DAC varies directly with output frequency; alias images of the wavetable function spectrum are exact harmonic multiples of the output waveform frequency; the DAC must now be specified according to the highest sample frequency; the reconstruction filter cut-off frequency must now track the variable sample frequency to reject alias images and preserve waveshape integrity over the operating frequency range. Specifying the wavetable function is performed in an identical manner to the fixed sample frequency case, only now we need not be concerned about aliasing of the upper harmonics at high waveform frequencies. Indeed, aliasing in the fixed sample frequency sense (i.e. the presence of in-band alias spurs generally non-harmonically related to the waveform frequency) can no longer occur. The generated waveform frequency is linearly proportional to φ with frequency control resolution fs/2MþJ and maximum frequency fs/2Jþ1. Furthermore, discounting the effects of any residual jitter in the clock signal, error spurs in the amplitude spectrum due to phase truncation cannot occur with this approach. If we recall the phase accumulating frequency synthesiser design example presented in Section 5.3.1, the 5-bit counter was viewed as a jitter reduction mechanism ahead of analogue waveshaping. Here we view the jitter counter as a phase counter that indexes a wavetable tabulating an arbitrary waveform function. In general, a J-bit phase counter corresponds with a 2J length wavetable. If we use a DDS phase accumulator to synthesise the variable sample clock directly, the inherent frequency jitter causes the phase counter increment rate to vary slightly over time. This, in turn, introduces error spurs in the amplitude spectrum.

5.5.2

Harmonic aliasing and reconstruction filter considerations If we assume that the phase counter increment rate is constant, all alias images of the wavetable spectrum lie on harmonic boundaries of the fundamental frequency and no other non-harmonic spurs are present in the output spectrum. The waveform error spectrum is therefore characterised by harmonic distortion alone. However, the phase counter does not necessarily increment at a constant rate due to jitter in the sample clock source. If we use a phase accumulator frequency synthesiser as our sample clock source,

5.6 Computer music and audio test applications of DDS AWG

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output frequency jitter causes erroneous non-harmonic spurs to appear in the waveform amplitude spectrum. The principal advantage of variable sample frequency AWG is preservation of waveform shape with increasing frequency. This, of course, is in contrast to fixed sample frequency DDS AWG, where the fixed reconstruction filter bandwidth causes a general smoothing of waveshape with increasing frequency due to the progressive suppression of higher frequency harmonics. The change in waveshape is particularly noticeable in waveforms that contain features with a fast time rate of change. In the limit, as the waveform frequency approaches the Nyquist frequency, the waveshape approaches a sinusoid. This effect can only be mitigated by adopting an oversampling strategy, where the Nyquist frequency is much higher than that required for the maximum synthesised waveform frequency, and thereby introducing ‘excess bandwidth’ to maintain waveshape features. To accommodate the Nyquist frequency variation that occurs with variable sample frequency waveform generation we must control the reconstruction filter cut-off frequency to track the variable sample frequency fs. If we assume a J-bit phase counter, the effective sample frequency is always 2J fo and the corresponding Nyquist frequency 2J1 fo. The wavetable is therefore constrained to a maximum of 2J1 harmonics, although the maximum harmonic number is usually restricted to less than 2J1 to provide sufficient transition bandwidth11 for the reconstruction filter whose cut-off frequency must track fs. Accordingly, there is a design trade-off between maximum harmonic number and reconstruction filter complexity. Tracking the reconstruction filter cut-off frequency with synthesised waveform frequency is handled in a similar manner to the analogue waveshaping amplitude correction discussed in Section 5.3. Now we require a low- filter with suitable stop-band attenuation whose cut-off frequency is digitally controlled from φ, possibly using a combination of resistive MDAC and binary switched capacitors. The filter roll-off slope and hence stop band attenuation are governed by the number of poles and the filter response characteristic (e.g. Butterworth or Bessel). We consider reconstruction filter design further in Chapter 9.

5.6

Computer music and audio test applications of DDS AWG In this section we review some specific DDS AWG application considerations in the computer music and audio fields. Thus far our discussion has focused on the underlying concepts and performance measurement while avoiding application-specific considerations. It is apparent from computer music literature [13] that the underlying principles of DDS AWG have enjoyed wide application in various forms. The following discussion is confined to some specific control problems that are unique to computer music applications. We conclude with an outline discussion of some precision audio test applications, where exact frequency control across multiple synchronised sources and very high spectral purity are essential. 11

We discuss filter transition bandwidth in Chapter 9.

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5.6.1

Harmonics and partials An important and fundamental computer music synthesis technique is known as sinusoidal additive synthesis, which we define as the time-varying linear combination of sinusoidal basis components to synthesise a particular tonal characteristic or timbre. Two distinct forms are reported in the literature: harmonic additive synthesis and the more general partial additive synthesis. Harmonic additive synthesis produces exactly periodic signals according to a spectrum model whose basis frequencies follow an exact harmonic distribution. Partial additive synthesis produces signals according to a spectrum model whose basis components or partials are distinguished by having time-varying frequency, often around an exact harmonic baseline value. We therefore define a partial as a generalised frequency component with time-varying frequency and a harmonic as the limiting case where the set of possible frequencies comprises an exact harmonic series. Both synthesis algorithms process parameter envelopes, which we define as the time-variation profile described by a parameter relative to some initiation event (e.g. a key depression). Partial additive synthesis is an important computer music synthesis technique and provides accessibility to the lowest level of timbral composition and expression through independent control parameters that are consistent with the human auditory perception model. The manipulation of partial envelopes to construct new sounds is usually referenced to a known point in ‘timbre space’ by editing a partial envelope set obtained from analysis of a real instrument sound. This approach is intuitive since human auditory perception favours a frequency domain transformation. However, the weak association between individual partial parameter changes and the corresponding change in perceived timbre is problematic. Baseline envelopes are obtained from a spectrum analysis of real sounds using a short-time Fourier transform (STFT), which provides time-localisation of spectral information. Partial magnitude and phase envelopes emerging from the STFT analysis are converted into corresponding amplitude and frequency envelopes using a piecewise-linear approximation which forms the baseline parameters from which we synthesise ‘new’ sounds. DDS AWG allows generation of musical signals with harmonic composition. Furthermore, as we will see in Chapter 6 this technique is readily extended to generate timevarying harmonic spectra or dynamic timbre in a musical application context. In principle, multiple instantiations of sinusoidal DDS allow generation of a partial sinusoid series that may be linearly combined to effect partial additive synthesis using appropriate amplitude and frequency envelope functions. The principal advantages of partial additive synthesis include: generality and accessibility of control parameters that provide access to the lowest levels of a sound’s composition; intuitive correspondence with the human auditory perception model; temporal evolution of timbre; parametric articulation of timbre; synthesis is baselined against natural sounds via established spectrum analysis tools; the sequential algorithm architecture is conducive to hardware pipelining and therefore FPGA and VLSI ‘friendly’.


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Conversely, the principal disadvantages include: high computational cost associated with synthesising numerous partials; high control parameter bandwidth and implicit computation cost to generate multiple time-varying parameters; ‘weak’ control parameter association with perceived timbre; dependency on ‘baseline parameter sets’ obtained from real instruments to initiate synthesis of new sounds (i.e. not a ‘synthesis from scratch’ technique).

5.6.2

Frequency control, musical pitch and tuning The frequency control of a musical signal source is expressed in of a parameter known as pitch rather than absolute frequency. Human pitch perception is based on the ratio of frequencies rather than absolute frequency [14]. Thepffiffiequal tempered scale ffi 12 defines the so-called half-step or semitone frequency ratio as 2 1:059463. This is equivalent to the frequency ratio between adjacent keys on a conventionally tuned piano keyboard, for example. Since this tuning system is relative, a basis frequency is needed to define an absolute pitch scale. For the equal tempered scale, this basis frequency is defined by the international pitch standard [14] as exactly 440 Hz and defines the A above middle-C (A4) on a conventionally tuned piano. The cent is defined as onepffiffiffi hundredth of a half-step or a ratio ofpffiffi1200 2 1:000578. In general, a k cent pitch shift ffik equates to frequency scaling of 1200 2 . There is a limit to human audio perception in distinguishing the relative pitch between two sinusoidal tones of equal intensity presented one after the other. When the difference in frequency between the two tones is below this limit, both tones are perceived as having the same pitch. When the frequency difference exceeds the just noticeable difference (JND) threshold a change in pitch is perceived. The pitch change JND is widely reported in the literature and depends on the frequency, intensity and duration of the test tone. It also varies greatly from person to person, is affected by the level of musical training and depends considerably on the measurement technique employed [15]. The literature consensus is that a 5 cent pitch change represents the order of JND for most listeners and listening conditions, although Rakowski [16] reports that under ideal listening conditions a very well trained ear can discriminate a frequency change of between 0.03 and 0.08 Hz around 160 Hz. This corresponds to a pitch change JND of approximately 0.3 cents. The pitch change JND is crucial in determining the absolute tuning accuracy or frequency resolution of a musical oscillator. However, frequency resolution below that required to satisfy the pitch change JND is needed when the beat frequency between two (or more) closely tuned oscillators must be precisely controlled – a common requirement in computer music synthesis. A 5 cent pitch tuning resolution at 7040 Hz (A8) requires a frequency resolution of 20.4 Hz which is inadequate for precise beat frequency control (i.e. beat frequencies could only be specified in integer multiples of 20.4 Hz). We now consider phase accumulator frequency resolution taking into both pitch change JND and beat frequency tuning across the audio range. We assume that a

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frequency resolution of the order of 0.01 Hz will provide sufficient beat frequency control resolution for all conceivable musical applications. Furthermore, we consider the impact of achieving a pitch tuning accuracy between 0.3 and 5 cents. The number of phase accumulator bits M is related to the frequency control resolution fr according to: 1 f ð5:41Þ M¼ log s : logð2Þ fr For a sample rate of 48 kHz, which is typical in professional audio applications, a frequency control resolution of 0.01 Hz requires M ¼ 23. Since a pitch change is a fixed ratio of frequencies, a constant frequency control resolution represents an increasing pitch tuning error with reducing frequency. We define the pitch tuning error εp in cents, as the frequency ratio corresponding to a unit change in φ for a specific minimum frequency fmin, sampling frequency fs and phase accumulator word size M. We then have: 1200 fs log 1 þ M : ð5:42Þ εp ¼ logð2Þ 2 fmin Equation (5.42) reveals that the pitch tuning error is below 1 cent at all synthesised frequencies above 27.5 Hz when M 22 with fs ¼ 48kHz, and M 24 with fs ¼ 192kHz, which is another professional audio sample rate. Choosing M ¼ 24 provides surety of pitch and beat frequency tuning accuracy for all fs values likely to be used in computer music applications. Increasing the sampling frequency over that required for normal audio bandwidth (i.e. oversampling) causes a corresponding increase in the Nyquist frequency, reducing susceptibility to upper harmonics aliasing when complex wavetables are resynthesised.

5.6.3

Audio measurement – harmonic and intermodulation distortion So-called coherent test conditions require application of composite test stimulus signals that comprise multiple orthogonal sinusoidal tones. Coherency describes the condition where the sample rate of the measurement ADC (or ADC under test) is synchronous with the test stimulus signals ensuring that all of the test signals lie exactly on an FFT bin centre. Accordingly, all test stimulus signal and sample frequencies can be programmed to be integer ratios. Orthogonal signals are statistically independent and can therefore be detected and measured without ambiguity. These test signals are arranged to be integral multiples (i.e. harmonics) of a primitive frequency f equal to the reciprocal of the FFT analysis record length in sample periods T. Exactly one cycle of the primitive frequency (or fundamental) therefore occupies the FFT analysis record. In general, the composite signal is fed to the unit under test and the output response signal analysed by computing the FFT over a vector of samples whose length is determined by the test signal primitive frequency and sample frequency. The FFT produces both amplitude and phase information for each input tone, in addition to any harmonic and intermodulation response spurs. This, in turn, allows accurate measurement of many performance metrics, such as harmonic distortion and frequency/phase response.


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The field of precision audio system test and characterisation often requires variable frequency sinusoidal sources with ultra-low distortion and noise. Example systems include diverse functions such as small-signal amplifiers, power amplifiers and wide dynamic range ADCs. Similarly, testing and characterisation of high performance DACs require similar test signals, but now in discrete-time form. A variety of established techniques reported in the literature enable the measurement of total harmonic distortion (THD), intermodulation distortion (IMD), frequency response, phase response and inter-channel crosstalk [17]. All of these techniques require test signals with specific and often unique attributes compared to more general system testing. From a signal generation perspective, which concerns us here, these signals can be classified into essentially three groups: single-tone sinusoidal signals with independently adjustable amplitude and frequency; two-tone sinusoidal signals with independently adjustable amplitude, frequency and possibly phase (if the tones are ‘harmonically locked’); so-called ‘multi-tone’ signals comprising multiple discrete sinusoids each with adjustable amplitude, frequency and phase (e.g. a non-contiguous harmonic spectrum). In general, it is essential that the THD, SFDR and residual noise of these test signals be significantly better than the distortion levels we expect from the system under test – at least by an order of magnitude. Accordingly, signal purity approaching or exceeding a 24-bit quantisation noise floor is not uncommon, particularly in a high-end audio test [18]. Figure 5.31 illustrates some examples of THD and IMD signal spectra. These include the associated input test signals which are indicated by an arrow, and the corresponding typical distortion spurs that we wish to measure are indicated by circular markers. Single-tone sinusoid test signals are used to measure THD which is simply defined as the ratio of the RMS voltage of all the harmonic error spurs to that of the fundamental f0. Similarly, two-tone test signals each having independently programmable frequency are used to measure IMD. We have shown examples of the SMPTE and CCIF standard IMD measurement techniques, which differ primarily according to the spacing between the two input tones. Our last example spectrum shows a typical multi-tone test signal comprising a contiguous set of harmonic sinusoids relative to a fundamental f0. The response signals represent the frequency-sampled profile of the amplitude and phase frequency response of the unit under test (UUT). Interpolation of these responses provides an estimate of the actual continuous frequency response of the UUT. All of these signals can be generated by the DDS techniques presented in this book. The single-tone requirement is satisfied by a single sinusoidal DDS using appropriate phase–amplitude mapping (including the DAC and reconstruction filter stages) to satisfy THD and SFDR requirements. A brute force sinusoid waveform generator with zero phase truncation error is provided by the trigonometric identity phase–amplitude mapping algorithm. The two tone requirement may be satisfied by using two synchronised DDS generators or a single arbitrary waveform DDS if harmonically related sinusoids are acceptable. The arbitrary waveform approach offers the additional


THD spectrum

f0

2 f0

3 f0

4 f0

5 f0

IMD spectrum (SMPTE) fH − fL fH − 2 fL

Amplitude

224

fH + fL fH + 2 fL

fL

fH

IMD spectrum (CCIF) 2( f H − f L )

fH − fL

2 fL − fH

2 fH − fL

fL fH

Multi-tone test spectrum

f0

2 f0

3 f0

4 f0

UUT tone response

UUT frequency response

kf 0

Frequency Figure 5.31 Spectra of several audio test signals for THD and two types of IMD measurement including hypothetical responses. A typical multi-tone test spectrum is also shown, including an overlaid frequency response from the unit under test (UUT).

advantage of being able to synthesise multi-tone harmonic test signals according to the definition of the tabulated waveform function. If we require truly arbitrary multi-tone test signals (i.e. a non-harmonic frequency distribution), our only option is multiple synchronised DDS generators. In Chapter 6 we discuss several arbitrary waveform DDS architectures which satisfy these requirements. Finally, we outline three important ‘signal planning’ considerations in design and generation of multi-tone signals: so-called ‘tone pruning’ to optimise the spectrum of a multi-tone test signal; the ‘peak to RMS’ ratio (or crest factor); ‘dynamic overload’ or slew rate considerations.

5.7 Summary

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When deg and optimising a multi-tone test signal for a particular measurement, it is often necessary to remove or ‘prune’ some tones to avoid conflict with expected distortion products. For example, when measuring THD at 3f and 7f, we would not necessarily include test signal components at 6f and 9f that would obscure measurement of the second and third harmonics of the 3f test tone [17]. One reported mitigation strategy is to use tone sets that comprise prime number frequency distributions. However, this may also prohibit some required tones from the set. When many sinusoids are linearly combined (as with a Fourier series, for example), the composite waveform may exhibit a high amplitude peak compared to the RMS amplitude at some points. This, in turn, can lead to reduced measurement SNR when the test signal level is adjusted to ensure that the peak level does not cause the UUT to saturate. It is possible to adjust the phase of the individual tones to produce a waveform with minimum crest factor. However, as reported in [17], such waveforms are sensitive to non-linear phase response in the UUT causing an effective growth in crest factor within a UUT processing chain and hence the possibility of internal saturation. Cabot [18] reports that optimal multi-tone test waveforms have a near-Gaussian amplitude distribution and pseudo-random phase distribution. Both of these conditions are straightforward to arrange with arbitrary waveform DDS based upon wavetable lookup or the more flexible IDFT approach described in Chapter 7. Finally, we must consider the maximum slew rate (i.e. time rate of change of voltage) of a multi-tone test signal, which can often exceed that of simpler test signals of equal peak value. Slew rate limitations (or other non-linear dynamic effects) in the UUT introduce signal distortion if the slew rate of the test signal exceeds that of the UUT and can only be mitigated by using a lower amplitude test signal. In general, wideband test signals tend to have higher slew rate than narrowband, and this is another factor in the design of a multi-tone test signal.

5.7

Summary This chapter has introduced the focal topic for this book – arbitrary waveform generation based upon DDS principles, hitherto applied to sinusoidal waveform generation. Phase truncated indexing of a wavetable tabulating a non-sinusoidal waveform function (i.e. an arbitrary waveform) has been introduced and the principal error mechanisms identified. Mitigation of phase truncation errors is only possible by using larger wavetables with correspondingly longer fill times, or fractional addressing of smaller wavetables through phase interpolation introduced in Chapter 4. After a short tutorial on Lagrange polynomial interpolation, we have reviewed the harmonic aliasing problem, which is fundamental to arbitrary waveform generation. Techniques for specifying the waveform function in the time and frequency domains have been discussed, including band-limiting methods to mitigate Gibbs artefacts and aliaon regeneration. To conclude the introductory material, we have outlined the key criteria for choosing DDS AWG simulation parameters to demonstrate particular behaviours or produce worst case performance of a specific metric (e.g. SNR or SFDR). A simple analysis confirms the

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optimal phase–amplitude mapping condition where all phase accumulator states are uniquely mapped into the amplitude domain. Harmonics of the tabulated waveform function are shown to be aliased about integer multiples of the sampling frequency with a sinc function amplitude envelope. Simulated amplitude spectra, SNR and SFDR figures have been presented for several classes of phase–amplitude mapping algorithm and parameter values and the following conclusions may be drawn for the DDS AWG case: optimal (i.e. phase truncation error-free) performance is achieved when L ¼ 2M, irrespective of the tabulated wavetable spectrum; phase truncated wavetable indexing introduces significant error spurs, whose number and amplitude are a strong function of the harmonic complexity of the tabulated waveform; higher harmonics introduce more phase truncation error noise for a given wavetable length and non-radix-2 phase increment; assuming simple phase truncated indexing, these errors can only be mitigated by using very large wavetable lengths that might be impracticable in many applications; phase dithered wavetable indexing improves SFDR considerably, but introduces a lower bound on the noise floor across the Nyquist band; phase interpolation reduces the magnitude of error spurs in the amplitude spectrum and improves SNR and SFDR; for a given interpolation order and wavetable function, SNR and SFDR increase with wavetable length; for a given wavetable length and tabulated function, SNR and SFDR increase with interpolation order; for a given wavetable function and increasing interpolation order, each doubling of wavetable length produces a greater increase in SNR; SNR and SFDR generally reduce with increasing wavetable function harmonic content. The chapter has concluded with an outline discussion of analogue phase–amplitude techniques, square wave digital clock generation using DDS principles and some specific application examples of DDS AWG in the fields of computer music and audio system test. We have presented conceptual analogue waveform shaping techniques that may readily be combined with DDS frequency synthesis. In some very specific applications, analogue waveshaping may prove advantageous over the more flexible wavetable-based techniques, for example, in very high linearity sawtooth waveform generation. Techniques for generating low jitter digital clocks with all of the desirable DDS frequency tuning attributes have been presented. The simple relationship between the magnitude of non-harmonic amplitude error spurs and phase jitter in the synthesised clock waveform has been investigated. It is theoretically possible to construct very low jitter frequency-agile clock sources using the high performance phase–amplitude techniques presented (e.g. linear interpolation or trigonometric identity based methods).

5.8 References

5.8

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References 1. H. T. Nicholas and H. Samueli, An analysis of the output spectrum of DDFS in the presence of phase-accumulator truncation, 41st Annual Frequency Control Symposium, pp. 495–502, 1987. 2. S. V. Vaseghi, Advanced Signal Processing and Digital Noise Reduction, John Wiley and Sons Ltd. and B. G. Teubner, 1996. 3. S. Nakamura, Numerical Analysis and Graphic Visualisation with MATLAB, Prentice Hall PTR, 1996. 4. J. O. Smith, Digital Audio Resampling Home Page Center for Computer Research in Music and Acoustics (CCRMA). Stanford University, [2011–03–29]. Web published at http://www. ccrma.stanford.edu/~jos/resample/. 5. J. G. Proakis and D. G. Manolakis, Digital Signal Processing – Principles, Algorithms and Applications, 3rd edition, Prentice-Hall Inc, 1996. 6. F. S. Acton, Numerical Methods That Work, 2nd printing, Mathematical Association of America, p. 228, 1990. 7. Bar-Giora Goldberg, Digital Frequency Synthesis Demystified – DDS and Fractional-N PLLs, LLH Technology Publishing, 1999. 8. R. Hassun, ‘The common denominators in fractional N’, Microwaves and RF, p.107, June 1984. 9. J. A. Crawford, Frequency Synthesizer Design Handbook, Artech House, Inc, 1994. 10. Analog Devices, RF/IF IC Selection Guide. http://www.analog.com/, 2012. 11. D. Brandon, and K. Gentile, DDS-based clock jitter performance vs DAC reconstruction filter performance, Analog Devices Application Note AN837, http://www.analog.com/, 2006. 12. Analog Devices, A technical tutorial on direct digital synthesis, http://www.analog.com/, 1999. 13. C. Roads, The Computer Music Tutorial, The MIT Press, Cambridge, Massachusetts, 1996. 14. F. R. Moore, Elements of Computer Music, Prentice-Hall, Inc, 1990. 15. T. D. Rossing, The Science of Sound, 2nd edition, Addison-Wesley, 1990. 16. A. Rakowski, Pitch discrimination at the threshold of hearing, Proceedings of the 7th International Congress on Acoustics, Vol. 3, Budapest, 1971. 17. M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits, IEEE Computer Society Press, 1987. 18. R. C. Cabot, ‘Fundamentals of modern audio measurement’, Journal of the Audio Engineering Society, 47, (9), pp. 738–762, September 1999.

6

Dynamic waveshape and spectrum control

In this chapter we investigate several techniques for generating waveforms with timevarying waveshape and corresponding spectrum. We consider three distinct techniques which are inherently compatible with the DDS model: paged wavetable access – where a contiguous sequence of waveform functions is tabulated in memory and accessed sequentially according to a time-varying waveshape (or spectrum) parameter; linear wavetable combination – where multiple wavetables that each tabulate different waveform functions are linearly combined according to a time-varying parameter; modulation – where the frequency, phase or amplitude of a typically sinusoidal carrier waveform is modulated by a modulator waveform. Paged wavetable access requires a paged memory structure and provides time-varying waveshape (or corresponding spectrum) by selecting waveform ‘waypoints’ from a set of predefined wavetables. This is analogous to replaying a sequence of video frames where each frame represents a distinct waveform. In its most rudimentary form, the resolution of this technique is bound by the amount of physical memory available for wavetable storage and hence the number of distinct waveshape waypoints that may be included in a set. We also present an enhanced form called paged wavetable interpolation, which effectively interpolates waveforms that lie between the predefined waypoints, thus increasing the waveshape or spectrum control resolution. Waveshape may now be controlled in a piecewise-linear manner with arbitrarily fine control resolution according to a fractional page address. Linear wavetable combination has two distinct architectural subclasses to consider, which we discriminate according to the number of phase accumulators used. In the simplest ‘single phase accumulator–multiple wavetable’ architecture, we have a single phase accumulator simultaneously indexing multiple wavetables whose outputs are linearly combined. We are therefore restricted to generation of periodic waveforms with time-varying waveshape according to the linear combination and exactly harmonic spectra. The ‘multiple phase accumulator–multiple wavetable’ architecture assigns a dedicated phase accumulator to each wavetable and thereby enables the generation of non-harmonic band- spectra with an arbitrary frequency distribution. However, additional frequency control processing is now required to maintain tracking of the sideband components relative to the centre frequency.

6.1 Paged wavetable memory – piecewise stepped waveshaping

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An inherent feature of DDS is that it allows independent linear modulation of frequency, phase and amplitude, irrespective of the phase–amplitude mapping function. We conclude this chapter by investigating some specific modulation examples for the sinusoidal DDS case, although the techniques presented are equally applicable when arbitrary waveforms are tabulated in the wavetable.

6.1

Paged wavetable memory – piecewise stepped waveshaping A desirable attribute of any waveform generator is the ability to vary waveshape according to a single control parameter. Variation of the control parameter causes a change in waveshape according to some predefined function: for example, a rectangular waveform with continuously variable rise and fall times, or a sine wave that varies from having no harmonic distortion to one with a particular harmonic distortion characteristic. Both of these examples imply a smooth, ‘well-behaved’ change in waveshape as the control parameter varies. However, instantaneous switching between different waveforms from a predefined set is also of utility in many application domains (e.g. digital carrier modulation emulation). Although we refer to waveshape in these examples (i.e. a time domain perspective), variation in the corresponding spectrum (i.e. a frequency domain perspective) is equally important depending on the application. In this section we investigate ‘wavetable paging’, where the output waveform at a given time is selected from a set of predefined waveforms stored in many distinct wavetables. In principle, if we define a sufficient number of waveforms with small incremental changes in waveshape across the set, we achieve a smooth control of waveshape as the wavetable indexing parameter or page address varies. Wavetable paging therefore requires specification of a contiguous set of wavetable functions that collectively define the variation in waveshape as we sequence through them. In effect, we consider each wavetable as defining an arbitrary point in an abstract ‘waveshape space’. We now review paged memory addressing and paged indexing of a group of wavetables.

6.1.1

Page indexing a group of wavetables Paged memory addressing is a simple way of organising a given memory space into distinct blocks or ‘pages’. Let us imagine a hypothetical memory comprising 216 or 64k locations. This memory may be considered as one contiguous block of data addressed by a 16-bit address where each address indexes a unique data point. We may organise this memory into many smaller blocks called pages. For example, we may organise it into 64 pages each comprising 210 or 1k locations. Accordingly, the physical memory address is now split into two logical fields – a 6-bit page address comprising the 6 most significant address bits and a 10-bit data address comprising the 10 least significant address bits. In a wavetable context, this example corresponds to 64 distinct 1k sample wavetables where each wavetable is assigned to a unique page within the physical memory array.


p(n) = 2P−1

LL

230

2I+P

p (n) = 1 p (n) = 0

2I Page 0 fs ϕ

M ∑

z–1

fI (n)

I

LSBs Paged wavetable memory

P M

y(n)

DAC

y (t)

MSBs

Page address p (n) Figure 6.1 A conceptual paged wavetable memory. The particular wavetable indexed by the

phase accumulator is selected by the integer page address p(n) and fed to a DAC and reconstruction filter to resynthesise the waveform. (A phase offset adder and amplitude scaling multiplier are omitted for clarity, but may be included if required.)

A conceptual paged wavetable memory is illustrated in Figure 6.1 and represents a simple development of the phase truncated phase–amplitude mapping algorithm discussed in Chapter 5. This figure also illustrates the idea of a paged wavetable memory tabulating a progressive change in waveshape. The paged wavetable memory is divided into 2P pages each storing a unique wavetable of 2I samples. The total memory length requirement is therefore 2IþP samples and is always a radix-2 value. The time-varying page address is denoted by p(n) 2 [0, 2P 1] and provides the P most significant memory address bits. The sample address is denoted by ϕI (n) and provides the I least significant memory address bits. The sequence p(n) selects one of the 2P distinct wavetables and effectively represents a ‘proxy’ waveshape parameter when the wavetables tabulate a progressive change in


231

waveshape. If we require a smooth transition of waveshape as p(n) varies, P must be sufficiently large so as to minimise the waveshape change for each increment of p(n). The overall wavetable memory requirement is now governed by two parameters – I, which determines SNR and error spectrum performance as discussed in Chapter 5, and P, which determines the ‘granularity’ of waveshape control according to the number of tabulated waveform functions. As with the single wavetable case, phase interpolation may be applied by performing the requisite number of paged wavetable read operations and associated interpolation computations each sample period. Phase interpolation is independent of the paged wavetable indexing which only selects a particular wavetable from a set.

6.1.2

Specifying a group of wavetables An important question is now apparent – how do we specify a sequence of waveform functions to tabulate in a paged wavetable memory? The answer depends on what we are trying to achieve as the page address p(n) varies to control waveshape. There are essentially two cases to consider. The first case arises when we wish to effect a smooth variation from ‘waveshape A’ to ‘waveshape B’ as p(n) varies over its range. This requires that we carefully consider each tabulated waveform across the 2P wavetables as part of a contiguous set. A refinement of this approach only specifies intermediate ‘waypoint’ waveshapes that must be included in the set. From this set of waypoints we compute the intermediate ‘unspecified’ wavetables by linear interpolation during wavetable tabulation. As the number of wavetables increases, the change in waveshape between adjacent wavetables becomes progressively smaller and so the control of waveshape with p(n) generally becomes smoother. However, this also increases the total wavetable memory requirement, computation and fill time. The second case involves ‘random access’ selection of a waveform from a set of 2P independent arbitrary waveforms according to the value of p(n), which is now considered as a ‘1 from N’ waveform selection parameter. In this case, each wavetable tabulates a waveform that is distinct from its neighbouring wavetables and not part of a smoothly evolving set. These two operating cases are illustrated in the hypothetical examples in Figure 6.2. Figure 6.2a shows a smoothly changing sawtooth waveform sequence comprising four wavetables whose harmonic content is increasing with wavetable number. We show both the ‘classic’ truncated Fourier series waveform with Gibbs phenomenon clearly evident and the same waveform whose harmonic profile has been weighted by the Lanczos sigma function as discussed in Section 5.1.4. The latter waveform clearly exhibits less ringing and shows increasing ramp linearity and ‘rise time’ as the number of harmonics increases. We also show simulated waveform sequences for each of the tabulated functions where p(n) is arranged to transition part way through a waveform cycle. We observe a steadily improving sawtooth waveshape as p(n) increases, although occasional waveform amplitude discontinuities are evident as we switch between wavetables. The nature of the discontinuity is dependent on the differences between adjacent

232


(a)

Truncated Fourier series

Page 0

Page 1

Lanczos corrected

Page 2

Page 3

Lanczos corrected

Truncated Fourier series

p(n) = 1

p(n) = 0

p(n) = 2

p(n) = 3

(b)

Page 0

Page 1

p(n) = 0 3 cycles

p(n) = 1 1 cycle

Page 2

Page 3

p(n) = 0

p(n) = 0

2 cycles

2 cycles p(n) = 2 1 cycle

p(n) = 3 1 cycle

Figure 6.2 Two examples of paged wavetable specification: (a) A piecewise contiguous set of four

waveforms that specify a stepped variation in waveshape according to p(n). Circular regions highlight discontinuities when switching between wavetables. (b) Four wavetables that tabulate ‘normal’ and anomalous sine waveforms with various hypothetical waveshape errors. Anomalous waveforms are selected by changing p(n) on a waveform cycle boundary.


233

wavetable functions and the phase point at which the transition occurs. Application of the Lanczos sigma function to effectively low- filter the wavetable function is seen to reduce the magnitude of the discontinuity. In general, there are several ways to reduce the magnitude of paged wavetable discontinuities: use more wavetables in the paged set thereby ensuring sufficiently small changes in waveshape between adjacent wavetables; only allow p(n) to change at a phase point that will not cause a significant discontinuity; only allow p(n) to change at the end of a waveform cycle; linearly interpolate the transition between wavetables. The last approach eliminates discontinuities entirely and allows p(n) to change independently of the waveform phase. There is a small increase in real-time computation associated with the interpolation calculations, but this has to be offset against reduced wavetable memory overhead and fill time. We investigate paged wavetable interpolation in the next section. Figure 6.2b shows four sinusoidal wavetables containing hypothetical waveform anomalies typical of an ‘error-mode’ signal emulation application. The first wavetable tabulates an ideal sine wave which is our baseline signal. In this case p(n) controls the synchronised imposition of a waveform anomaly by selecting an erroneous wavetable for a specific number of cycles on the occurrence of an external trigger event. In the example of Figure 6.2b, the erroneous waveforms are only selected for a single cycle. Accordingly, p(n) is only allowed to change at a waveform cycle boundary to mitigate transitional discontinuities. The waveform end phase may be determined by examining the phase accumulator output sequence and detecting the overflow condition defined by (ϕ(n) þ φ) > (2M 1).

6.1.3

Paged wavetable interpolation – piecewise continuous waveshaping In principle, with a sufficiently large array of paged wavetables, we can achieve an arbitrarily fine change in waveshape as p(n) varies to index the array. The penalty for this improvement in waveshape control is an increase in the amount of physical memory required in addition to the wavetable computation and memory fill time. It is possible to achieve a smooth variation in waveshape with p(n) using a reduced set of wavetables by employing paged wavetable interpolation at the expense of increased real-time computation. In effect, this technique computes the current-output sample from a ‘virtual’ wavetable lying between the tabulated ones according to a fractional representation of the page address p(n). In a similar manner to the waveform phase ϕ(n) generated by the phase accumulator, we now represent p(n) in a fractional form comprising P integer bits and F 0 fraction bits. The integer part pP(n) provides the physical wavetable memory page address (i.e. selecting one of 2P wavetables). The fractional part pF 0 (n) is used to linearly interpolate samples from the current wavetable and next wavetable pages to compute the output sample. Hence, for a given

234


value of p(n), we interpolate the two adjacent wavetables indexed by pP(n) and pp(n) þ 1 in a similar manner to the phase interpolation case. Before proceeding further, we make further denotations to clarify our discussion and henceforth drop the discrete-time sequence notation for brevity. We denote a paged wavetable address by ( pp, ϕI) where pp denotes the P-bit wavetable page index and ϕI denotes the I-bit truncated phase accumulator output. Accordingly, we denote a paged wavetable read operation by W[ pP, ϕI]. If we assume phase truncated wavetable indexing (i.e. no phase interpolation), our two wavetable samples to be interpolated according to pF 0 are W[ pP, ϕI] and W[ pP þ 1, ϕI]. As a fractional quantity, the wavetable 0 page index may be denoted as ( pP þ γ), where pP 2 [0, 2P 1]1 and γ ¼ pF 0 /2F with the fractional part of the page address pF comprising F 0 bits. The fractional wavetable page index γ is used to linearly interpolate the adjacent wavetables W[ pP, ϕI] and W[ pP þ 1, ϕI] to generate an output sample y(n). The paged wavetable interpolation is now defined by the expression: yðnÞ ¼ ð1 γÞW½ pP , ϕI þ γW½ pP þ 1, ϕI :

ð6:1Þ

0

Paged wavetable interpolation effectively computes 2F 1 ‘virtual wavetables’ inbetween each of the 2P 1 explicitly defined adjacent wavetable pairs. The total number of distinct waveshapes that may be synthesised by this method is therefore 0 (2P 1)(2F 1) and determined by P and F0. We may apply phase interpolation to each wavetable indexing operation to reduce phase truncation errors as discussed in Chapter 5. In Chapter 8 we present a novel memory architecture that s linear (and higher order) phase interpolation combined with linear paged wavetable interpolation. It is evident that wavetable interpolation requires careful definition of the waypoint waveforms to ensure the desired waveshape transition occurs as the interpolation proceeds. Even if the waypoint waveforms are all normalised to unit-amplitude, the amplitude of the interpolated waveform can deviate from unity. This causes a variation of waveform amplitude with interpolation (i.e. waveshape) and is not an error phenomenon, but a mathematical property of linear interpolation between different waveforms normalised to unit amplitude. The amount of amplitude variation is a strong function of the two waveforms being interpolated and is easily corrected if necessary. Figure 6.3 illustrates a simple example of linear wavetable interpolation across a group of four wavetables according to a fractional wavetable page index. The four wavetables tabulate a sine wave, two sawtooth waveforms and a square waveform approximated by a Fourier series with Lanczos sigma correction to reduce Gibbs ringing artefacts. Figure 6.3 also shows a simulated waveform sequence where we interpolate across all four wavetables over several cycles, varying (pP þ γ) accordingly. Unlike the noninterpolated paged indexing case, the results show a smooth transition in waveshape with no discontinuity at any point. However, a small fluctuation in waveform amplitude is observed as the interpolation proceeds. 1

For compatibility with hardware memory implementations where address 0 is a valid address, we let all vector indices (i.e. memory addresses) start from zero.


Page 0

Page 1

Page 2 pP = 0

pP = 0

235

Page 3 pP = 2

pP = 1

pP = 2

pP = 1

W[ pP+1, φI]

W[ pP ,φI]

γ

(1 − γ ) γ ∈ [ 0 , 1)

∑ Interpolator

y(n)

p = pP + γ

3

0 Figure 6.3 A hypothetical implementation of linear wavetable interpolation across four wavetables. Observe the discontinuity-free change in waveshape with p(n) which now takes on fractional values.

6.1.4

Frequency domain behaviour Paged wavetable interpolation is fundamentally a time domain process and so it is instructive to consider the spectrum of the interpolated waveform. If we linearly interpolate two wavetables containing waveform functions whose corresponding harmonics are exactly in-phase, the harmonic amplitudes in the interpolated waveform will vary linearly between their respective values in the two wavetables as the

236


interpolation proceeds. To see this, let us consider two wavetables with identical harmonic phase that may be defined thus: 0 1 Nh X 2πka A, W1 ½a ¼ Ak sin@ L k¼1 0 1 Nh X 2πka A, W2 ½a ¼ A0 k sin@ ð6:2Þ L k¼1 where Ak and A0 k are the wavetable harmonic amplitude vectors, Nh is the number of harmonics and a 2 [0, L 1]. Assuming only phase truncated indexing for simplicity, the waveform sequence produced by linearly interpolating these two wavetables is then given by: yðnÞ ¼ ð1 γÞW1 ½ϕI þ γW2 ½ϕI ,

ð6:3Þ

where γ 2 [0, 1) is the fractional page address and ϕI is the integer phase component. We also drop some of the time indices for clarity as in Chapter 5. If we substitute from Eqs. (6.2) and let Sk ¼ sin(2πkϕI/L), then Eq. (6.3) may be expressed as: yðnÞ ¼

Nh X 0 ð1 γÞAk þ γA k S k

ð6:4Þ

1

and we observe that the amplitude scaling factor for the harmonic sine Sk is just the linear interpolation of the two amplitude vectors Ak and A0 k according to γ. This result means that paged wavetable interpolation may be used to generate time-varying harmonic spectra with piecewise-linear harmonic amplitude profiles. From a frequency domain perspective, paged wavetable interpolation may be viewed as spectral interpolation according to the fractional wavetable page address. However, if the wavetables contain waveforms whose corresponding harmonics are not in-phase, we observe harmonic amplitude variation in the interpolated waveform that does not vary linearly as the interpolation proceeds. Indeed, a 180 phase offset between corresponding wavetable harmonics will cause that harmonic’s amplitude to through zero at a specific interpolation point. Several computer music applications of so-called spectral interpolation synthesis based upon paged wavetable interpolation as presented here, are presented in [1].

6.2

Linear combination of multiple wavetables In this section we investigate dynamic waveform and spectrum generation by the amplitude-weighted summation or linear combination of multiple DDS waveform generators. Linearly combining amplitude weighted, phase offset harmonic sinusoids is an important limiting case equivalent to the inverse discrete Fourier transform (IDFT). There are several cases to consider, which can be classified into two groups according to frequency control:

6.2 Linear combination of multiple wavetables

237

the linear combination of waveforms that share a common phase accumulator and are therefore phase locked and constrained to exact integer multiples of a single fundamental frequency; the linear combination of waveforms where each is associated with a distinct phase accumulator and can therefore be at any frequency and need not be phase locked or harmonically related. Since DDS is based upon phase accumulation frequency synthesis, we denote these two classifications as single phase accumulator and multiple phase accumulator, respectively. In the multiple phase accumulator case, we may generate waveforms at essentially any frequency and are only constrained by the frequency control resolution of the individual phase accumulators and the Nyquist frequency. There is no fundamental frequency that our generated frequencies are relative to. If the phase accumulators share a common sample clock, our combined waveforms will be phase-coherent (i.e. always synchronous with a single reference frequency) and may, if suitably programmed, be phase locked (i.e. integer multiples of a single frequency). In this context, we define two (or more) signals to be phase locked if they have a constant phase offset between them. The single phase accumulator architecture is a special case of the more general multiple phase accumulator case. However, if we have a multiple phase accumulator system and wish to generate an exact harmonic series, we must ensure that the phase accumulators are all coherently initialised (i.e. ϕ(0) ¼ 0) to ensure correct phase offset control according to the offset value added to each phase accumulator output. Although the schematic architectures of both single and multiple phase accumulator waveform generators appear complex, they are easily adapted to a time division multiplexed implementation which significantly reduces hardware complexity and cost. We consider this further in Chapter 8 and for our present discussions use the ‘brute force’ parallel processing descriptions to illustrate the underlying principles.

6.2.1

Single phase accumulator case – harmonic signal synthesis A single phase accumulator indexing multiple wavetables is illustrated in Figure 6.4. Each of the k wavetable outputs is weighted according to a unique time-varying amplitude parameter Ai(n) with i 2 [1, k]. For clarity, we omit the optional phase offset adders at each wavetable address input. Several important properties are evident with this architecture: each wavetable can only tabulate a periodic waveform with a harmonic spectrum; the frequency ratio between any two wavetables can only take on harmonic values according to the number of waveform cycles tabulated in each wavetable; the phase accumulator fractional phase information ϕF(n) may be used to impose phase interpolation across all wavetables if required; for a given set of amplitude weighting values, the composite output waveform could have been generated with a single wavetable. Given this last observation, the principal advantage of this approach is that it allows real-time control of waveshape according to a harmonic spectrum set by the wavetable


fs ϕ

M ∑

z–1

I

I

Wavetable 1 ∏ A1(n)

M I

Wavetable 2 ∏ LL

A2(n)

∑

y (n)

LL

238

I

Wavetable k ∏ Ak(n)

Figure 6.4 A single phase accumulator indexing multiple wavetables. Wavetable outputs are

weighted and summed to form the composite output waveform. Phase offsets θk(n) may be applied by placing k adders (not shown) at the wavetable indexing inputs.

amplitude (and phase) weightings. Although omitted from Figure 6.4 for clarity, it is possible to include a phase offset weighting to each of the wavetables if required. A simple example will help demonstrate the utility of this technique. Let us imagine a waveform generator comprising four linearly combined wavetables all indexed from a single phase accumulator. The accumulator phase increment controls the fundamental frequency of the composite waveform. The first wavetable tabulates an ideal sine waveform, which is the principal generated signal in this example. However, this wavetable could tabulate any periodic waveform according to a harmonic specification. The remaining three wavetables tabulate particular harmonic sinusoids (e.g. the 2nd, 3rd and 4th). By varying the amplitude weighting of the ‘harmonic wavetables’ relative to the fundamental wavetable, we may dynamically control the total harmonic distortion of the composite sinusoid. If we increase the number of wavetables we may generate more complex harmonic distortion profiles. Furthermore, if appropriate phase interpolation is used, very low distortion sinusoids may be synthesised with precisely controlled harmonic distortion levels. It is important to that we are not constrained to tabulate distinct harmonic sinusoids in the wavetables. Alternatively, we might tabulate waveforms with fixed harmonic composition and then vary the respective amplitude weightings to synthesise a particular spectrum change over time. This technique has been applied in the computer


239

music domain and is known as group additive synthesis [2]. (In its most general form, group additive synthesis employs the multiple phase accumulator model that we discuss later.) The tabulated waveform function is completely arbitrary and may have any integer number of cycles per wavetable, bound only by the Nyquist limit. For Nc cycles per wavetable and Nh harmonics in each waveform function, we must always satisfy the non-aliasing condition NcNh/2I 1/2. In the limit, where we tabulate a distinct harmonic sinusoid in each wavetable with separate phase offset control, we effectively implement the IDFT in real time. However, as we will see later, there are more computationally efficient methods for real-time computation of the IDFT.

6.2.2

The IDFT as a limiting case If we tabulate a series of contiguous (or indeed non-contiguous) harmonic sinusoids across the group of wavetables and incorporate a phase offset adder before each wavetable, we effectively implement the IDFT in real time. The number of harmonics in the synthesised waveform is determined by the number of wavetables, and the fundamental frequency is set by the phase accumulator phase increment. The partitioning afforded by this approach means that we are not constrained to a contiguous harmonic series. Only the total number of harmonics is bound according to the number of wavetables. We may therefore synthesise a waveform (or spectrum) in real time according to a harmonic amplitude and phase specification that itself may be timevarying. This raises an important problem – how do we control so many parameters, given that each harmonic requires both amplitude and phase information? One solution is a so-called ‘one–many’ mapping function that translates from a single ‘meaningful’2 input parameter into many individual harmonic amplitude and phase parameters. We denote the input parameter as a metaparameter, a term which has been applied in the field of computer music synthesis [3]. An illustrative example of a metaparameter is one that controls the total harmonic distortion (THD) of a quasi-sinusoidal waveform. THD is defined as the ratio of the sum of the powers of all distortion harmonics to the power of the fundamental (i.e. the first harmonic) and usually expressed as a percentage. It is used to describe the spectral purity or quality of a sine wave signal, which in the ideal case will have no distortion harmonics and hence zero THD. A given value of THD therefore describes a spectrum of harmonic amplitudes. The corresponding metaparameter mapping function defines the relationship between a THD input variable (the metaparameter) and multiple harmonic amplitude output parameters that are used by the IDFT waveform generator. We observe that the fractional page index in a paged wavetable interpolation system can be viewed as a metaparameter that controls the amplitude and phase of multiple harmonics according to the waveform functions tabulated in the set of paged wavetables. The architecture depicted in Figure 6.5a represents a ‘brute force’ parallel processor that computes a k-harmonic IDFT in real time, where k separate wavetables each 2

We take ‘meaningful’ in this context to be relative to the particular application.


fs ϕ (n)

(a)

M ∑

I

z–1

∑ q1(n)

Sine wavetable 1

M

∏

A1(n) ∑ q2(n)

Sine wavetable 2

∏

LL

LL

A2(n)

∑ qk(n)

Sine wavetable k

∑

y(n)

∏

Ak(n) (b) θc (n)

M

ϕ c(n)

∑ ∑

z–1

I

Sine wavetable 1

M

∏

Ac(n) fs M

θs1(n)

∑ ±ϕ s1(n)

∑

z–1

I

∑

Sine wavetable 2

∏

fs M θsk(n)

∑ ± ϕ sk(n)

∑

∑

y(n)

LL

M

LL

As1(n) LL

240

z–1

I

∑

Sine wavetable k

∏

Ask(n) fs M Figure 6.5 (a) A brute force real-time implementation of the IDFT according to harmonic amplitude and phase offset parameters. (b) Multiple phase accumulators indexing multiple sine wavetables. This arrangement s a carrier-sideband programming model where sideband frequencies are offset with respect to a single carrier frequency. In both cases, simple phase truncated wavetable indexing is shown for clarity. Phase interpolation may be applied if required.


241

tabulate a distinct harmonic sinusoid. Although very fast due to the high degree of parallelism, this approach requires a large amount of hardware due to a separate phase offset adder, wavetable and amplitude scaling multiplier for each harmonic term. The weighted harmonic summation across k channels adds further processing overhead and complexity. We consider a more computationally efficient method in Chapters 7 and 8.

6.2.3

Multiple phase accumulator case – band- signal synthesis A multiple phase accumulator configuration is illustrated in Figure 6.5b. The architecture shown s a ‘carrier-sideband’ programming model where the carrier is the principal signal and all of the sideband frequencies are offset with respect to it. The carrier frequency is set by φc(n) and the k distinct and independent sideband frequencies are set by the φsi(n) parameters, with i 2 [1, k]. The amplitudes of the carrier and each sideband are set by the corresponding Asi(n) parameters. For completeness, we also show individual phase offset adders which set the carrier and sideband phase offset according to the θsi(n) parameters. A fixed phase offset between signals is only applicable if the respective phase accumulators are programmed with exact harmonic frequencies (i.e. the phase increment values are integer multiples of a fundamental value). In this case, we must also initialise the phase accumulators to ensure ϕ(0) ¼ 0 before adding an offset to the wavetable index. We now have a dedicated phase accumulator for each wavetable, enabling independent setting of the linearly combined sine waveform frequencies. Although coherent with a single sample clock, the individual phase accumulators may be set to any frequency consistent with their frequency control resolution. The multiple phase accumulator configuration allows generation of band- signals that are not constrained to have a harmonic spectrum and typically comprise multiple discrete spectral lines (i.e. individual sinusoids). Band- signals are characterised by having a discrete spectrum that can take many forms, which include: multi-tone signals with arbitrary (e.g. non-harmonic) frequency spacing; modulation-like signals (e.g. amplitude modulation (AM) carrier-sideband signals); intermodulation signals. Multi-tone signals that are equally spaced in frequency are effectively a harmonic series with a fundamental frequency equal to the separation frequency between the tones. Alternatively, we may synthesise a multi-tone signal with a logarithmic or other non-linear frequency spacing. Equally or logarithmically spaced multi-tone signals comprising a ‘comb’ of equal amplitude, ultra-low distortion sinusoids are widely used as test and system characterisation signals, particularly in audio system testing [4]. As input signals to a system-under-test (e.g. an audio amplifier), they allow the simultaneous, and hence high speed, measurement of frequency response, phase response, total harmonic distortion and noise behaviour in the presence of a signal. Detuning the high frequency tones between two independent multi-tone signals is used to measure interchannel separation (or ‘crosstalk’) in a two (or more) channel system. Multi-tone test signals are often used in conjunction with so-called ‘synchronous FFT’ analysis.

242


Stated simply, the source and analysis sampling frequencies (assuming a digital implementation) are exactly synchronised so that any input test signal frequency will always lie exactly on an FFT bin centre. If we assume a multiple phase accumulator configuration, matching the analysis FFT length with the number of possible phase accumulator states (i.e. 2M) will always satisfy this condition, irrespective of the programmed frequency. In other words, we must make the FFT record length 2M samples. Since fast, large FFTs are possible on modern hardware, we observe that values of M of the order of 24 are practicable. For example, a multiple phase accumulator audio generator with fs ¼ 104.8576 kHz and M ¼ 20 provides a multi-tone signal generator with 0.1 Hz frequency control resolution and up to 50 kHz bandwidth on each channel. A subsequent FFT record length of 220 (i.e. 106) samples, which is practicable to implement, ensures any input frequency generated by the multi-tone signal generator always lies on a bin centre. In turn, this ensures that the amplitude spectrum is exact. Multi-tone signals may be used to emulate a system response under specific conditions in order to calibrate, or debug a measurement instrument or process. Modulation-like signal spectra are characterised by having a centre or ‘carrier’ frequency surrounded by a spectrum of sidebands at specific offsets from the carrier. They are specified by a centre frequency and multiple sideband frequencies at specific offsets above and below the centre frequency. It is also possible to easily synthesise asymmetric arrangements of sidebands (e.g. upper or lower single sideband (SSB) modulation signals). Intermodulation signals are similar to modulation signals and characterised by a spectrum comprising the sum and difference frequencies (and possibly their harmonics) of two primary tones. So-called intermodulation distortion is an important metric in measurement of high linearity amplifiers and other analogue components. Typically, two ultra-low distortion sinusoidal tones are used as input stimuli to the systemunder-test and the resulting response spectrum computed to measure intermodulation distortion. The tones may be closely or widely spaced depending on the type of intermodulation distortion measurement. As before, a multiple phase accumulator generator may be used to generate the two tone input signal or to emulate a particular intermodulation distortion spectrum for diagnostic purposes. Once again, the signal emulation applications of these types of waveform synthesiser are almost unbounded. In this discussion we have assumed that each wavetable tabulates a single sine wave cycle allowing generation of band- signals composed of distinct sinusoids. However, as with the single phase accumulator case, waveforms having an arbitrary harmonic spectrum may also be tabulated.

6.3

Modulation We now consider frequency, phase and amplitude modulation of a DDS waveform generator. All reported advanced modulation forms (e.g. QAM and QPSK) are based upon only these three types of modulation, either collectively or individually. This discussion applies to both sinusoidal and arbitrary waveform implementations as DDS

6.3 Modulation

243

modulation of any form is independent of the phase–amplitude mapping process. As we have already seen, DDS provides precise, linear and independent control of frequency and phase. As the bandwidth of these modulation paths is bound only by the Nyquist frequency, they may be used to impose modulation according to a suitably band-limited modulation signal. Frequency control resolution is determined by the phase accumulator word size and is essentially unbounded. Phase control resolution is determined by wavetable length and to a limited degree the phase interpolation method employed. Amplitude modulation is implemented by multiplying the output samples with an appropriate modulation signal.

6.3.1

Frequency, phase and amplitude modulation If we assume an M-bit phase accumulator, the generalised DDS frequency and phase modulated phase sequence are given by: n X 2π ϕðnÞ ¼ M nφc þ ðφm ð jÞÞ þ θm ðnÞ þ θ0 , ð6:5Þ 2 2M j¼1 where φc is the fixed phase increment that sets the carrier frequency fc, φm(m) is the frequency modulating sequence, θm(n) is the phase modulating sequence and θ0 is the initial phase. If θm(n) ¼ 0 and φm(n) is a sinusoidal signal with frequency fm and amplitude m, this expression defines the instantaneous discrete-time phase of a classical sinusoidal frequency modulated (FM) signal. The modulation index is determined by m ¼ Δf /fm, where Δf denotes the change in carrier frequency. Conversely, if φm(n) ¼ 0 and θm(n) is a sinusoidal signal with frequency fm and amplitude m, this expression defines the instantaneous discrete-time phase of a phase modulated (PM) signal. If we assume ideal phase–amplitude mapping using a 2M sample wavetable, the modulated sinusoid is then given by: yðnÞ ¼ AðnÞ sinðϕðnÞÞ,

ð6:6Þ

where A(n) denotes an amplitude modulating (AM) sequence. However, we are not confined to sinusoidal carrier waveforms and the modulated phase sequence may be used to index a wavetable tabulating any periodic function. In a physical implementation, we typically truncate the phase accumulator sequence in order to reduce the size of the wavetable, and must therefore modify Eq. (6.5) accordingly. Furthermore, the phase accumulation computations must be performed with signed arithmetic (e.g. 2’s complement). Figure 6.6 illustrates the generalised DDS modulation model where we assume truncated phase–amplitude mapping for simplicity. The output of the phase accumulator is truncated to I bits with the F bit fraction component ϕF (n) used to phase interpolation if required. Phase interpolation takes place entirely within the wavetable block, which now accepts ϕF (n) as an additional input. If phase interpolation is not required, the phase offset adder need only be I bits wide and the phase truncation imposed at the phase accumulator output. A multiplier at the output of the wavetable imposes amplitude modulation according to A(n).

244


ϕc ϕm(n)

M

M

fs ∑

M ∑

z–1

I ∑

I

Wavetable ∏

θ0 θ m(n)

M

I

I

y (n)

∑

I

A(n) Figure 6.6 Hypothetical DDS continuous modulation model using truncated phase–amplitude

mapping for simplicity. Independent frequency, phase and amplitude modulation are ed by this architecture.

The DDS modulation model illustrated in Figure 6.6 is strictly independent of the tabulated wavetable function which may be a sinusoidal or arbitrary waveform. For a non-sinusoidal wavetable, the modulation spectrum is the superposition of the modulation of each of the waveform harmonics.

6.3.2

FSK and PSK modulation Multi-level frequency shift keying (FSK) and phase shift keying (PSK) modulation are easily implemented with sinusoidal or arbitrary waveform DDS. FSK modulation can take two forms – phase-continuous and phase-coherent. In Chapter 2 we saw how DDS is inherently phase-continuous with respect to step transitions in phase increment and therefore frequency. We may impose phase-continuous m-level FSK or PSK modulation by generating the corresponding modulation signals from an m input multiplexer that selects from one of m fixed frequency or phase values as illustrated in Figures 6.7a and 6.7b, respectively. These values correspond to the discrete FSK or PSK modulation levels. The multiplexer is controlled by a log2(m)-bit modulation control sequence that we denote by dm(n). In the FSK case, this scheme represents phase-continuous FSK. In the PSK case, we observe that the modulated DDS phase offset is always phasecoherent (by definition) since all phase shift states are coherent with the same phase accumulator sequence and sample clock. In the digital domain, DDS FSK or PSK produces smooth, instantaneous changes (discounting pipeline latency delays) in carrier frequency and phase. However, in the analogue domain we typically observe a transient following a step change in frequency or phase due to the finite bandwidth of the postDAC reconstruction filter. The magnitude of this transient is a function of the frequency step change relative to the reconstruction filter bandwidth. Phase-coherent FSK is implemented by having m independent DDS channels all synchronous with the same sample clock (i.e. coherent) and each set to run continuously

6.3 Modulation

245

(a) fs

M M

m:1 mux

LL

ϕ1 ϕm

dm (n)

log2 m

I

z–1

∑

Wavetable

y (n)

Wavetable

y (n)

M fs

(b) ϕc

M ∑

I

z–1

∑

I

M LL

θ1

I m :1 mux

I

θm

dm(n)

fs

(c) ϕ1

log2m

M ∑

z–1

I

Wavetable

LL

LL

M

m :1 mux

y (n)

fs ϕm

M ∑

z–1

I

log2 m Wavetable

dm(n)

M Reset φ (0) = 0 Figure 6.7 Hypothetical DDS modulation models according to the modulation sequence dm(n): (a) An m-level FSK modulation model; (b) An m-level PSK modulation model; (c) A phasecoherent DDS FSK modulation model.

246


at one of the m FSK modulation frequencies. The phase accumulators should all be initialised by a common reset event to ensure that ϕ(0) ¼ 0 for all channels. Phasecoherent FSK modulation is implemented by selecting the appropriate DDS output according to the modulation signal value. Figure 6.7c illustrates a hypothetical phasecoherent FSK DDS implementation. An alternative and novel technique for implementing phase-coherent FSK and PSK modulation in DDS is presented in [5]. This technique causes the frequency or phase transition to occur at the zero-crossing points in the sine wave cycle.

6.3.3

Frequency sweep and chirp generation We now consider the generation of a particular class of linear FM signals which are also known as linear frequency sweep or chirp signals, depending on the application domain. Such signals are characterised by a linear rate of change frequency sweep from a start frequency to a stop frequency, often in response to an external trigger event. In general, a chirp is distinguished only by having a relatively fast time rate of frequency change. A linear frequency sweep (or chirp) has an instantaneous frequency f (t) that varies linearly with time and can be described by the linear equation f (t) ¼ f (0) þ kt, where f(0) is the start frequency at t ¼ 0 and k is the time rate of change of frequency or chirp rate. The corresponding phase function is the integral of frequency and given by: ðt

ðt k ϕðtÞ ¼ f ðtÞdt ¼ ðf ð0Þ þ kt Þdt ¼ t 2 þ f ð0Þt þ ϕð0Þ, 2 0

ð6:7Þ

0

where ϕ(0) is the initial phase at t ¼ 0. In DDS, we generate a linear frequency sweep or chirp by using a second accumulator to generate a linear ramp sequence φ(n) which provides the phase increment to a phase accumulator. The initial value of the frequency sweep accumulator sets the sweep start frequency according to the phase increment φi. The frequency increment sets the frequency sweep rate in integer multiples of the frequency control resolution fs/2M per sample period. If we set the frequency increment to 2R with initial condition φ(0) ¼ R þ φi, we obtain the linear frequency sweep phase sequence: ϕðnÞ ¼ Rn2 þ φi n þ ϕð0Þ,

ð6:8Þ

where R controls the frequency sweep or chirp rate, φi is the initial DDS phase increment that specifies the start frequency and ϕ(0) is the initial phase at n ¼ 0. Equation (6.8) is the discrete-time form of Eq. (6.7), where t ¼ nT. Figure 6.8 illustrates a linear frequency sweep DDS model which may be used for frequency sweep or fast chirp synthesis. In a typical implementation, control logic initiates the sweep accumulator in response to an external trigger event. Subsequently, the sweep ramp φ(n) is compared with the stop frequency phase increment φs, halting the sweep accumulator when the condition φ(n) ¼ φs is detected.

6.4 Summary

ϕ (n) = ϕ s

247

ϕs

=

fs 2R

ϕ (n )

Halt

M ∑

z–1

fs

M

φ (n )

∑

z–1

I

Wavetable

y (n )

M M

ϕ ( 0) φ ( 0)

ϕ (n )

φ (n )

n

Rate

0

2R

R + ϕi

1

2R

3 R + ϕi

R + ϕi + φ ( 0 )

2

2R

5 R + ϕi

4 R + 2ϕi + φ ( 0 )

3

2R

7 R + ϕi

9 R + 3ϕi + φ ( 0 )

4

2R

9 R + ϕi

16 R + 4ϕi + φ ( 0)

n

2R

( 2 n + 1) R + ϕ i

n 2R + nϕi + φ (0 )

φ (0)

Figure 6.8 The linear FM DDS model. A second accumulator generates a linear phase increment ramp sequence between predetermined start and stop values that control the frequency generating phase accumulator. The table shows the φ(n) and ϕ(n) sequence progression from n ¼ 0.

6.4

Summary In this chapter we have introduced several techniques for effecting real-time control of waveform shape and corresponding spectrum within the DDS AWG model. Beginning with paged wavetable indexing, we have introduced the idea of dynamic phase– amplitude mapping, where we select the generated waveform from a set of predefined waveforms with smoothly varying waveshape across the set. The waveform set can be contiguous, tabulating a gradual change in some waveshape feature, or a set of distinct (possibly unrelated) waveforms that are ‘randomly accessed’ as required in a specific application. Paged wavetable indexing is effectively a piecewise stepped waveshape control mechanism. We have extended the concept of phase interpolation to the interpolation between two distinct wavetables to generate a new waveform that is a linear combination of the two that are tabulated. We may now smoothly change waveshape across a set of predefined

248


wavetable ‘waypoints’, limited only by available memory constraints. We call this technique paged wavetable interpolation, which provides a piecewise linear waveshape control mechanism. We observe that both of these techniques are fundamentally time domain processes, where we are dynamically modifying waveshape according to a control parameter. We have proceeded to investigate the linear combination of multiple wavetable signals using single and multiple independent phase accumulators. In the limit, we see that the single phase accumulator case becomes equivalent to the IDFT algorithm, allowing synthesis of waveforms from a harmonic spectrum in the frequency domain and whose spectral characteristics can be changed in real time. This technique is developed further in Chapters 7 and 8, where we introduce more computationally efficient techniques than the ‘brute force’ approach discussed here, which primarily serves to illustrate the concept. The multiple phase accumulator case is a development of DDS that allows generation of band- spectra according to a carrier-sideband model. We have introduced the idea here ahead of presenting an efficient implementation method in Chapter 8 that makes this technique practicable. Finally, we have outlined the three ‘classic’ modulation methods that are easily incorporated into the DDS model, irrespective of the waveform being generated. Given its importance in many application domains, we have also discussed linear chirp generation using a second frequency accumulator to control a primary phase accumulator. This technique is readily extensible to the generation of chirps with non-linear frequency-time profiles.

6.5

References 1. M. Serra, D. Rubine and R. Dannenberg, ‘Analysis and synthesis of tones by spectral interpolation’, Journal of the Audio Engineering Society, 38(3), pp. 111–128, 1990. 2. P. Kleczowski, ‘Group additive synthesis’ Computer Music Journal, 13(1), pp. 12–20, 1989. 3. D. A. Jaffe, ‘Ten criteria for evaluating synthesis techniques’, Computer Music Journal, 19(1), pp. 76–87, 1995. 4. M. Mahoney, DSP Based Testing of Analog and Mixed-Signal Circuits, Wiley-IEEE Computer Society Press, 1987. 5. D. Brandon, ‘Efficient FSK/PSK modulator uses multichannel DDS to switch at zero crossings’, Analog Dialogue, 46, January 2012.

7


In Chapter 4 we introduced the idea of phase domain processing and outlined the permissible arithmetic operations that may be applied in a DDS context. In this chapter we apply simple multiplicative scaling of a phase sequence to combine DDS frequency synthesis (i.e. phase accumulation) with waveform synthesis based upon the inverse discrete Fourier transform (IDFT). This, in turn, enables computationally feasible real-time execution of the IDFT at any fundamental frequency and represents a powerful waveform generation technique. Waveform synthesis using the IDFT is fundamentally a frequency domain or spectrum specification method requiring multiple harmonic amplitude and phase parameters to specify the waveform. In a similar manner to the wavetable methods discussed earlier, we may also apply ‘spectral shaping’ (e.g. the Lanczos sigma function) to mitigate waveform ringing artefacts due to the Gibbs phenomenon. The fundamental frequency of the synthesised waveform may be programmed with all the advantageous attributes of DDS (e.g. phase continuity, linearity and arbitrarily fine frequency control). We now have a DDS arbitrary waveform generator with a fully parameterised IDFT phase–amplitude mapping algorithm. Another application of phase domain processing, that we investigate further in Chapter 8, exploits the properties of a phase sequence formed by the addition of two separate sequences from coherent phase accumulators clocked at different sample frequencies with a radix-2 ratio. By appropriate partitioning of the input phase increment between the two phase accumulators, the frequency control resolution of the summed sequence is determined solely by the accumulator with the lower clock frequency. This technique may be used to significantly reduce the amount of fast logic needed in very high frequency phase accumulator designs, thereby optimising power consumption, heat dissipation and cost [1]. Other forms of phase domain processing reported in the literature include phase dithering and noise shaping and have already been outlined in Chapter 4. These techniques are concerned solely with reducing the magnitude of DDS phase truncation error spurs and localised noise floor suppression (i.e. shaping) in the amplitude spectrum.

7.1

Fundamental concepts Before presenting methods for combining DDS with the IDFT, we first discuss several important concepts which underpin the techniques presented. We first review the definition of the IDFT and summarise its constituent arithmetic processes. We next

250


review the relationship between instantaneous phase and frequency as introduced in Chapter 2. We exploit the properties of this relationship to generate multiple harmonic phase sequences (and thereby harmonic sinusoids) from a single fundamental frequency phase sequence generated by a DDS phase accumulator. This operation is critical to real-time implementation of the IDFT. We next discuss the principal control problem which is unique to the IDFT and outline the basis of a novel method for its simplification. We proceed to discuss aliasing prevention by controlling the number of harmonics used in the IDFT summation. Finally, we introduce the concept of time division multiplexed (TDM) processing as this underpins the presented methods for generating multiple harmonic phase sequences and efficiently computing the IDFT.

7.1.1

The inverse discrete Fourier transform (IDFT) The inverse discrete Fourier transform (IDFT) computes a periodic waveform sequence according to a specification comprising Nh þ 1 harmonic amplitude and phase coefficients Ak and θk, where k 2 [0, Nh]. The A0 coefficient corresponds to the waveform’s DC offset term when θ0 ¼ 0. A discrete-time waveform sample is defined according to the IDFT by the expression: y ð nÞ ¼

Nh X

Ak cos ð2πkfo nT þ θk Þ,

ð7:1Þ

k¼0

where fo is the waveform fundamental frequency in Hz. For each sample index n, Eq. (7.1) accumulates an amplitude and phase weighted series of Nh þ 1 sinusoids (including the DC or zero frequency term), which are harmonic multiples of a fundamental frequency. An alternative, but equivalent, form expresses the IDFT in of the complex harmonic amplitudes Ik and Qk, thus: y ð nÞ ¼

Nh X

ðI k cos ð2πkfo nT Þ þ Qk sin ð2πkfo nT ÞÞ,

ð7:2Þ

k¼0

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi where Ak ¼ I 2k þ Q2k and θk ¼ tan1(Ik/Qk). This form is useful if we wish to generate waveforms from a quadrature harmonic specification. To compute the IDFT in real time according to Eq. (7.1) therefore requires an efficient method for performing several distinct arithmetic operations: synthesising a set of Nh harmonic phase sequences relative to a waveform fundamental frequency fo; phase offset weighting each phase sequence according to θk (which is unnecessary in the complex IDFT formulation expressed by Eq. (7.2)); mapping each phase sequence to a corresponding sinusoidal amplitude sequence; amplitude weighting each sinusoid according to Ak (or Ik and Qk); accumulating each of the weighted sine into a single output sample y(n). A brute force implementation of Eq. (7.1) is illustrated in Figure 7.1. This implementation uses Nh separate phase accumulators whose phase increments are computed to be

251

7.1 Fundamental concepts

A1

ϕ

fs

M

∏

θ1

∑

1

∑

Sine wavetable

z–1

A0 A2

M θ2

∏ ∑

2

∑

∑

∑

y (n )

Sine wavetable

z–1

LL

ϕ

fs

M

LL

M

AN

h

ϕN

fs

M

θN

∏

h

∑

h

∑

Sine wavetable

z–1

M Figure 7.1 A brute force processing architecture capable of synthesising harmonic and

non-harmonic signals based on the IDFT. This is a generalised form of the IDFT processing architecture presented in Chapter 6.

harmonic multiples of the fundamental phase increment parameter, Nh separate phase– amplitude mapping stages and an Nh input adder to compute the output sample summation. The DC offset term A0 is added to the final output sequence. The architecture shown in Figure 7.1 requires additional processing (not shown) that computes Nh harmonic phase increments φk from the fundamental phase increment input parameter φ1 (i.e. φk ¼ kφ1 for k 2 [1, Nh]). This adds additional processing overhead in a generalised harmonic implementation. The processing architecture presented in Figure 7.1 provides a generic band signal generation system, as introduced in Chapter 6, when the individual phase increments take on arbitrary (e.g. non-harmonic) values. A simpler approach uses a single set of hardware that

252


is multiplexed in time across each of the Nh harmonic computations. An output accumulator computes a ‘running sum’ of the weighted harmonic amplitude values over each sample. After Nh operations, on each sample clock event, the accumulator contains the output waveform sample. However, the penalty is that the multiplexed processor has to run at Nh fs computations per second and is conducive to pipelined implementation. In Chapter 8 we present a computationally efficient method for implementing this processing architecture in hardware. Despite its computational complexity, several important attributes are evident with the real-time IDFT waveform synthesiser when compared to the wavetable method. These may be summarised thus: elimination of a large wavetable memory and corresponding ‘fill time’ overhead; instantaneous waveshape or spectrum control at the harmonic level; elimination of aliasing and reduction of Gibbs ringing artefacts through real-time harmonic amplitude profiling; phase modulation of individual harmonics to impose a precisely controlled frequency offset from the harmonic value; a phase truncation noise level that is independent of harmonic number (unlike the wavetable tabulation case discussed in Chapter 5). The last attribute is in contrast to the wavetable tabulation case where we tabulated a waveform according to the IDFT from a harmonic specification. In that scenario, higher waveform harmonics are effectively stored in shorter wavetables leading to increased phase truncation error. In real-time IDFT waveform synthesis every harmonic is computed from the same length wavetable and (if appropriate) interpolation function. Hence, all harmonics have the same amount of phase truncation error. These attributes are important when weighing up the large computational overhead compared to wavetable based methods that we have considered so far. If real-time spectrum control, aliasing mitigation and harmonic phase modulation are not required we should consider the paged wavetable interpolation method introduced in Chapter 6 as it is computationally less demanding. This, of course, assumes that the waveshape or spectrum variation with wavetable page address can be predefined before tabulation. Moreover, changing the spectrum variation with page address requires time-consuming recalculation of the paged wavetable functions and subsequent . Finally, we observe that when the IDFT is executed in real time, the harmonic phase offset and amplitude parameters may be time-varying sequences and therefore properly denoted by θk(n) and Ak(n), respectively. However, for brevity in our present discussion we drop the discrete-time index and accept that these parameters may be fixed or time varying.

7.1.2

Weighted phase sequence summation Before investigating some novel methods for generating harmonic phase sequences, it is necessary that we review the relationship between discrete-time instantaneous phase and frequency. This relationship underpins material presented in


253

Sections 7.2 and 7.3, where we investigate generation of harmonic sinusoids from a fundamental frequency phase sequence. The instantaneous value of an M-bit phase accumulator output sequence at time index n is given by: * + n X ϕ ð nÞ ¼ ðφðmÞÞ þ θ , ð7:3Þ m¼1

2M

where φ(n) denotes a time-varying phase increment (i.e. frequency parameter) and θ is the initial phase or phase offset when n ¼ 0 and hence θ ¼ ϕ(0). ϕ(n) therefore represents the instantaneous phase of a discrete-time periodic signal. Let us now imagine another phase sequence ϕ0 (n) defined according to Eq. (7.3), but with corresponding input parameters φ0 (n) and θ 0 . If we sum these two phase sequences ^ ¼ ϕðnÞ þ ϕ0 ðnÞ and given by: we obtain a new phase sequence ϕðnÞ * + * + n n X X 0 0 ϕ^ðnÞ ¼ ðφðmÞÞ þ θ þ ðφ ðmÞÞ þ θ m¼1 + 2M * m¼1 n X ≜ ðφðmÞ þ φ0 ðmÞÞ þ θ þ θ 0 : m¼1

2M

ð7:4Þ

2M

We observe that the instantaneous frequency of ϕ^ ðnÞ is simply φ(n) þ φ0 (n) and similarly, the phase offset is θ þ θ 0 . If we assume that the phase increment parameter is constant, we obtain: 0 ϕ^ðnÞ ¼ hnðφ þ φ0 Þ þ θ þ θ i2M

ð7:5Þ

^ and observe that the frequency and phase offset of the composite phase sequence ϕðnÞ are equal to the sum of the constituent phase sequence frequencies and phase offsets, respectively. We now consider the special case where we sum two identical phase sequences. If we neglect the phase offset and again assume constant frequency, the new phase sequence is expressed by hϕðnÞ þ ϕðnÞi2M ¼ h2ϕðnÞi2M ¼ h2nφi2M and we observe that the slope and hence frequency of the resultant sequence are exactly doubled. From this we deduce the general case where we multiply ϕ(n) by a positive integer k modulo 2M, to give a new phase sequence ϕk(n) that we define thus: ϕk ðnÞ ¼ hkϕðnÞi2M ¼ hnkφi2M ,

ð7:6Þ

and observe that the frequency of the new phase sequence is also multiplied by k and given by kφfs/2M for k 2 Z, k > 0. To satisfy the Nyquist criterion we that k is bounded according to k 2M/2φ. We therefore conclude that for a given phase sequence ϕ(n), we may compute the corresponding kth harmonic phase sequence by multiplying ϕ(n) by k modulo 2M. This result underpins a novel technique first proposed by Chamberlin [2] and expanded in [3] in the context of computer music synthesis, for generating harmonically related phase sequences that enable real-time computation of the IDFT. We discuss this technique in Section 7.2 and generalise it in Section 7.3.

254


7.1.3

Dynamic spectrum control and the metaparameter An IDFT waveform synthesiser provides independent control of the amplitude and phase of each harmonic that comprises the waveform specification. In addition, we are able to set the fundamental waveform frequency independently of the harmonic spectrum parameters. Although it is a very flexible waveform synthesis technique, real-time spectrum control has one fundamental disadvantage, namely the number of control parameters required, particularly when the number of harmonics is large. A waveform specification comprising Nh harmonics requires 2Nh amplitude and phase control parameters to fully specify and control. If the IDFT method is to be of practical utility, we need to find a way of reducing the number of control parameters. In the domain of computer music synthesis, where application of the IDFT is generalised as additive synthesis or AS, this problem is generally known as the ‘control parameter problem’ [4]. As noted in Chapter 6, a novel solution based on the idea of a so-called metaparameter has been suggested by Jaffe [5] in connection with practicable additive synthesis implementation, and it is outlined here to illustrate the salient features. A metaparameter, which we denote by Pm, is a single parameter that simultaneously varies multiple control parameters in a predefined way through a ‘one–many’ mapping function as conceptualised in Figure 7.2. Here we see a simple example depicting the metaparameterisation of four harmonic amplitude and phase parameters, with the DC term assumed zero. Accordingly, there are four mapping functions to define, each taking the metaparameter as an argument. In general, we may express the mapping functions thus: ðAk , θk Þ ¼ fk ðPm Þ,

ð7:7Þ

where (Ak, θk) represent the kth harmonic amplitude and phase data pair, and fk(Pm) are the Nh þ 1 distinct metaparameter mapping functions with k 2 [0, Nh]. Assuming we can define and compute these mapping functions in a given application, metaparameterisation provides a structured way of controlling an IDFT waveform synthesiser. However, the computation burden increases with both the number of harmonics and the complexity of the mapping functions. Metaparameterisation of the IDFT may be implemented in one of two ways according to how we interpret the (Ak, θk) data pair. The first implementation specifies the IDFT input parameters directly, where (Ak, θk) are interpreted as harmonic amplitude and phase spectrum values (as shown in Figure 7.2). The second implementation ‘scales’ a set of predefined harmonic amplitude and phase values where (Ak, θk) can now be interpreted as a complex filtering operation (e.g. multiplicative scaling of harmonic amplitudes and additive offset of the phase offsets). The latter implementation allows a predefined spectrum and its corresponding waveform to be modified according a particular function. For example, we could define a waveshape via its spectrum and through an appropriate metaparameterisation impose the effect of an arbitrary filtering operation as Pm varies. Taking a simple example from a computer music application, let us imagine a waveform that has some arbitrary harmonic specification that emulates a steady-state musical instrument tone. Metaparameterisation might be used to impose control of highly subjective, but -friendly; musical timbral attributes such as tone


255

Metaparameter mapping functions (Ak, qk) = fk (Pm), k ∈[0, Nh]

A1 A2 f1

A3

Amplitude vector

A4 f2 Pm f3 θ1 θ2

f4

θ3

Phase vector

θ4

fs

M

ϕ

ϕ

Ak memory

k Ak

Ak

IDFT waveform synthesiser

Pm k

k

qk

qk

qk memory Figure 7.2 A hypothetical metaparameter mapping to harmonic amplitude and phase that

enables simple, but specialised, control of an IDFT waveform synthesiser.

y(n)

256


‘brightness’ or ‘warmth’. Of course, defining and computing the mapping function here is the challenge. Alternatively, this example may be applied as a simple control mechanism for the total harmonic distortion of a sinusoid signal. In general, metaparameterisation is an application-specific problem.

7.1.4

Aliasing control and the mitigation of Gibbs phenomenon A distinct advantage of real-time IDFT waveform synthesis is its inherent ability to dynamically control the number of harmonics used in the synthesis summation and their respective amplitude and phase. Furthermore, if we make the number of harmonics a function of frequency (i.e. the fundamental phase increment), we may ensure that the inequality φNh/2M < 1/2 is always satisfied and thereby prevent aliasing as the waveform frequency is increased. This requires that we introduce a new variable Nh max, which denotes the maximum number of harmonics ed in a particular implementation, with Nh Nh max. However, abruptly truncating the number of harmonics according to the phase increment is analogous to a ‘brick wall’ filtering operation since Ak ¼ 0 for all k Nh when Nh Nh max and k 2 [0, Nh max]. This tends to introduce Gibbs phenomenon artefacts following discontinuities in the synthesised waveform, and these are generally undesirable. An improved approach uses a filter response that gradually scales all of the harmonic amplitudes so that Ak ¼ 0 for all k Nh and so φNh/2M < 1/2, significantly reducing Gibbs artefacts. This is equivalent to the Lanczos sigma factor filtering operation introduced in Section 5.1.4 in connection with mitigating Gibbs phenomenon in wavetable tabulation. The filter response is not fixed, but chosen according to the φ value to ensure that no harmonics are included in the summation above the Nyquist frequency. A typical filter function based upon the Lanczos sigma factor is defined in Eq. (5.17). In this application we denote the filter response vector by Hφ,k, which describes a set of distinct filter responses that are selected by φ. The individual filter coefficients (i.e. the harmonic amplitude scaling factors) are indexed by k. In principle, this requires that a unique filter response be computed for every value of φ to maintain the inequality φNh/2M < 1/2, which is somewhat impractical when Hφ,k becomes very large. In practice, a smaller set of precomputed filter response vectors is tabulated over steadily reducing Nh. A particular filter vector is chosen to scale the harmonic amplitude vector Ak over a range of φ values by using the MSBs of φ to select the particular filter vector, as illustrated in Figure 7.3. An improvement of this approach linearly interpolates intermediate filter responses between the tabulated ones to give finer control with φ if required. It is evident that for high waveform frequencies there are fewer harmonics included in the IDFT summation than at lower frequencies to prevent aliasing. Therefore, a waveform synthesiser with a given maximum number of harmonics will have ‘wasted’ computation at high waveform frequencies due to all those harmonics with Ak ¼ 0. If we denote the time to compute a single harmonic by th (which is governed entirely by the hardware or software implementation), we may ‘trade’ sample frequency and hence synthesis bandwidth with Nh max according to fs 1/(Nh maxth). For example, if th ¼ 10 ns and fs ¼ 1 MHz we have Nh max ¼ 100. Alternatively, if fs ¼ 100 kHz we have Nh max ¼ 1000.


257

fs

ϕ

M

M

ϕ

ϕ MSBs

IDFT waveform synthesiser

Hϕ ,k Hϕ ,k lookup table k ∏

Hϕ ,k vector page select A

Ak k lookup table Ak

θ

k θk lookup table θ k

Hϕ ,k Ak

y(n)

k θk

Figure 7.3 A hypothetical aliasing control scheme. Harmonic amplitudes are adjusted according

to a tabulated filter vector that is selected by the MSBs of the phase increment φ.

7.1.5

Time division multiplexing (TDM) For a processing system with a fixed sample frequency, a time division multiplexed (TDM) processing strategy divides each sample period into an equal number of ‘time slots’ in which specific elemental processes are executed consecutively. At the end of each sample period all of the elemental processes will have been executed and the final result is sent to an output buffer. TDM processing is particularly suited to highly regular, ‘feed forward’ algorithms such as consecutive multiply-accumulate operations represented by Eq. (7.1). Furthermore, TDM processing is well-suited to pipelined implementation that increases throughput at the expense of signal flow and control latency. We investigate pipelined processing and pipelined TDM further in Chapter 8 when we investigate hardware implementation. To see how we might implement Eq. (7.1) in TDM form, it is first instructive to expand the summation as a series of Nh based upon wavetable indexing, where each wavetable tabulates a specific harmonic sinusoid, thus: yðnÞ ¼ A1 W 1 ½ϕI ðnÞ þ θ1 ðnÞ þ A2 W 2 ½ϕI ðnÞ þ θ2 ðnÞ þ A3 W 3 ½ϕI ðnÞ þ θ3 ðnÞ þ þ AN h W N h ½ϕI ðnÞ þ θN h ðnÞ,

ð7:8Þ

where Wk[a] ¼ cos(2πka/2 ) and ϕI (n) ¼ bϕ(n)/2 c. In a TDM implementation that computes Eq. (7.8), the sample period is divided into Nh equal duration ‘time slots’ that are allocated to the computation of each term and whose results are accumulated to compute the output sample value. Each term in Eq. (7.8) is computed sequentially in a dedicated time slot using an appropriate I

F

258


harmonic multiplier, amplitude and phase offset parameter. The result from each time slot operation is placed in an accumulator and on each sample clock the accumulator value is transferred to an output buffer. The result from the first time slot computation initialises the accumulator overwriting the final result from the previous sample. Subsequent intermediate results are then accumulated until the end of the sample period. As we see in Section 7.2, a TDM implementation suggests a novel way of generating contiguous harmonic phase multiples of a fundamental phase sequence using a simple arithmetic observation. We investigate the hardware-specific implementation of TDM processing further in Chapter 8 and present processing architectures that efficiently execute the IDFT in real-time from both contiguous and non-contiguous harmonic spectrum specifications.

7.2

Contiguous harmonic phase generation and the IDFT In this section we consider arithmetic processing of the phase accumulator output sequence ϕ(n) to generate new phase sequences with consecutive harmonic frequency distributions. This builds on material presented in Section 7.1.2 and computational structures first proposed by Chamberlin [2]. Recalling Eq. (7.6), we see that a phase sequence ϕ(n) multiplied modulo-2M by an integer k produces a new sequence ϕk(n) whose frequency is exactly the kth harmonic multiple of the ϕ(n) frequency, and so ϕk ðnÞ ¼ hkϕðnÞi2M . We now introduce a novel method for efficiently computing harmonic phase sequences which exploits the observation that accumulation is equivalent to multiplication of the initial accumulator value by a consecutive integer sequence.

7.2.1

Harmonic phase accumulation Figure 7.4 illustrates the concept of harmonic phase accumulation based upon [2]. A second ‘phase multiplying’ accumulator accumulates each M-bit ϕ(n) value providing a TDM sequence of contiguous integer (i.e. harmonic) multiples modulo-2M. This technique exploits the fundamental property of a digital accumulator initialised with x to produce the sequence x, 2x, 3x, . . . kx as the accumulation proceeds to k cycles. Accordingly, the harmonic phase multiplying accumulator is clocked at Nh fs, where fs denotes the ϕ(n) sample frequency and Nh denotes the total number of harmonics required in the IDFT computation. The accumulator generates the set of TDM phase sequences {ϕ(n), 2ϕ(n), 3ϕ(n), . . ., Nhϕ(n)}. In general, the harmonic phase accumulator generates the consecutive TDM sequence: ϕk ðnÞ ¼ hkϕðnÞi2M ,

ð7:9Þ

where k 2 [1, Nh] and is now considered as the TDM time-slot indexing variable that increments at Nh fs.1 Figure 7.4 illustrates a frequency synthesising phase accumulator 1

In Chapter 8, where we present several example processing architectures, we sub-divide the sample period into Nh time slots indexed by a time slot address variable (TSA) that increments at this rate.

259

7.2 Contiguous harmonic phase generation and the IDFT

M

ϕ

Preload

fs

M ∑

=1

φ (n)

z-1

Nh fs

M

z-1

Mux

φk ( n) = kφ (n)

2M

φk (n) = kφ (n)

2M

φk (n) = kφ (n)

2M

∑

M M

φ (n) written into harmonic accumulator

Preload cycle M

ϕ

φ (n)

fs

M ∑

z-1

Nh fs

M

z-1

Mux

∑

φ (n) M M Harmonic accumulation cycles M

ϕ

Nh fs

fs

M ∑

z-1

φ (n)

M

z-1

Mux

∑

(k + 1)φ (n) 2

kφ (n)

2M

M

M M

φ (n) accumulated in harmonic accumulator Figure 7.4 Generating a TDM phase sequence ϕk ðnÞ ¼ hkϕðnÞi2M with a contiguous harmonic

frequency distribution. The preload path initialises the harmonic phase accumulator with ϕ(n) at the start of each sample. Harmonic accumulation cycles generate the TDM sequence ϕ(n), 2ϕ(n), 3ϕ(n), . . .

260


fs

T Nh Nh fs L

Preload Σ phase accumulator

φ (n)

z −1phase accumulator

φ (n − 1)

φk (n) = kφ (n)

2M

N hφ (n − 1)

L

φ (n)

L

φ (n)

2φ (n)

3φ (n)

k =1

k=2

k =3

L

N hφ (n) k = Nh

Figure 7.5 Simplified timing diagram illustrating initialisation of the harmonic phase multiplying accumulator at the beginning of a sample. Subsequent accumulation of ϕ(n) at the Nh fs rate is also shown.

clocked at fs followed by a ‘harmonic phase multiplying’ accumulator which is clocked at an integral rate of Nh fs. The harmonic multiplying accumulator is ‘preloaded’ or initialised with the ϕ(n) value from the adder of the fundamental frequency synthesising phase accumulator at the beginning of each sample cycle. The runtime signal flow illustrations of Figure 7.4 depict the two modes of the harmonic accumulation process – initialisation and harmonic accumulation at the Nh fs rate. Figure 7.5 illustrates a simplified timing diagram of the preloading and harmonic accumulation process. The preload signal is active for one harmonic accumulation cycle (i.e. T/Nh) at the beginning of each sample. The fs clock loads the phase accumulator adder value into the output simultaneously with the Nh fs clock loading the same phase accumulator adder value into the harmonic phase accumulator . The phase multiplying accumulator efficiently computes all harmonic multiples of the fundamental frequency in a contiguous sequence over the interval [1, Nh]. This sequence must be computed to the highest required harmonic, irrespective of some intermediate harmonics being superfluous in a particular waveform synthesis application. An unwanted kth harmonic must be excluded by setting the corresponding amplitude parameter to zero, effectively wasting every computation cycle when Ak ¼ 0. In Section 7.3 we present a modified architecture which allows completely arbitrary, non-contiguous harmonic distributions to be computed according to a new harmonic multiplier parameter.

7.2.2

Harmonic phase offset The process model of Figure 7.4 requires that we sub-divide the sample period into Nh time-slots (strictly Nh max time slots following our discussion in Section 7.1.4). Imposing a specific phase offset on each harmonic is accomplished by introducing an adder

7.2 Contiguous harmonic phase generation and the IDFT

I

θk

φk (n) = kφ (n)

M 2M

261

∑

I

φk (n)

Sinusoidal phase–amplitude mapping

⎛ 2π ⎞ ≈ cos⎜ I φk ( n) + θ k ⎟ 2 ⎝ ⎠

φk (n)

I

F

F Figure 7.6 Applying a fixed or time-varying phase offset to each harmonic according to θk.

between the phase multiplying accumulator and phase–amplitude mapping stage as illustrated in Figure 7.6. Each time-slot computes a specific harmonic instantaneous phase value which is now phase offset according to the θk parameter and subsequently mapped to a sine amplitude sample. Accordingly, the harmonic phase offset data are time division multiplexed to align with the output sequence of the phase multiplying accumulator. Here we are not concerned with the phase–amplitude mapping implementation,2 which is independent of the harmonic phase computations. However, Figure 7.4 assumes a phase truncated form, possibly using linear phase interpolation according to the fractional harmonic phase index ϕk F ðnÞ. The phase offset is not constrained to fixed values and may be obtained from another phase accumulator sequence, thereby applying a frequency offset from the nominal harmonic frequency. The offset frequency is proportional to the rate of change (i.e. phase increment) of the modulating phase sequence and we assume that the modulating sequence is coherent with the fundamental phase accumulator. In this case, the phase offset arithmetic must be performed with M-bits of precision before phase truncation and phase–amplitude mapping. Figure 7.6 illustrates a fixed phase offset parameter θk added to an I-bit phase truncated sequence before sinusoidal phase–amplitude mapping. For completeness, we show the residual F-bit fractional harmonic phase index ϕk F ðnÞ which would be used in linearly interpolated phase–amplitude mapping.

7.2.3

Amplitude accumulation Following sinusoidal phase–amplitude mapping, each harmonic’s instantaneous amplitude sample is scaled by the TDM amplitude parameter Ak. The weighted harmonic samples are then summed in an accumulator over one sample period to generate the output sample. This process is repeated continuously at the sample frequency, producing a stream of waveform samples computed according to the IDFT. There are three considerations in the design of the amplitude accumulator:

2

The exact phase–amplitude implementation is governed primarily by the SNR and SFDR specification.

262


2π ⎛ ⎞ A1 cos⎜ φI (n) I + θ1 ⎟ 2 ⎝ ⎠

Preload

=1

Nh fs

fs

z-1

z-1

Ak 2π ⎛ ⎞ cos⎜ φk I (n) I + θ k ⎟ 2 ⎝ ⎠

∏

Mux

y (n)

∑

> 2b Figure 7.7 The final stage of real-time IDFT execution – accumulating the harmonic amplitude

samples.

initialising the accumulator at the start of an accumulation cycle and thereby clearing the previous accumulation result; dynamic range of the accumulator to accommodate the summation of Nh sinusoids without arithmetic overflow; transfer of the accumulated samples to an output at the end of a sample. Initialisation of the accumulator is accomplished in an identical manner to that used in the harmonic phase multiplying accumulator. A preload pulse is active for one Nh fs clock period and loads the amplitude weighted fundamental sinusoid sample into the accumulator . Thereafter, subsequent weighted harmonic samples are added to the accumulator as the processing proceeds. Assuming b-bit fixed-point sine amplitude samples, the worst case amplitude growth is log2(Nh) bits and assumes that the amplitudes of all Nh harmonics are unity – a somewhat unlikely occurrence in practice. The output of the amplitude multiplier will be 2b bits wide, and for optimal quantisation noise performance the accumulator should therefore be 2b þ log2(Nh) bits wide. Finally, at the end of the accumulation process we must transfer the accumulated value to a storage before preload initialisation of the accumulator with the first value of the next accumulation cycle. Figure 7.7 illustrates the amplitude accumulation signal flow. Accumulator initialisation is identical to that used in the harmonic phase multiplying accumulator. In Chapter 8 we discuss hardware implementation of the amplitude multiplieraccumulator in more detail.

7.3

Non-contiguous harmonic phase generation When we use the real-time IDFT to synthesise waveforms from a frequency domain specification, we do not always require a numerically contiguous set of harmonics. Often, only groups or clusters of harmonics are required with arbitrary (i.e. non-contiguous)

7.3 Non-contiguous harmonic phase generation

263

frequency distributions, particularly in the audio and music synthesis fields. We may use the contiguous harmonic implementation discussed in Section 7.2 and simply set the amplitudes of unwanted harmonics to zero. However, this wastes a computation cycle for each zero amplitude term which may be important in some applications. In this section we present an alternative approach which is still based upon TDM, but generates non-contiguous harmonic phase sequences according to a new explicitly defined harmonic multiplier parameter k. This requires a slight change to our TDM implementation when compared to the contiguous case. The sample period is still divided into a number of time slots, which is fundamental to a TDM implementation, but now each slot processes an arbitrary harmonic according to a multiplier parameter which we denote kj, where j is now the indexing variable. In our earlier contiguous harmonic phase generator, each time slot number k was also an implicit harmonic multiplier and this harmonic multiple of ϕ(n) was generated irrespective of being required in the IDFT summation or not (i.e. we generated the contiguous harmonic multiples 1, 2, 3, 4, 5, . . . Nh in sequence). Now, we may generate an arbitrary sequence of harmonic multiples. For example, 1, 3, 6, 8, 12, . . . Nh, with the number of bound only by the number of time slots which we denote by Nt.

7.3.1

Phase multiplication Building on the harmonic phase multiplying accumulator concept, we now introduce an integer multiplier block in place of the harmonic phase accumulator. This enables generation of non-contiguous harmonic phase sequences. This multiplier computes the integer multiple ϕj(n) of the phase accumulator sequence ϕ(n) according to an arbitrary harmonic multiplier parameter kj modulo 2M, thus: ϕj ðnÞ ¼ hk j ϕðnÞi2M ,

ð7:10Þ

where kj 2 [1, Nh] and j 2 [1, Nt]. This approach requires us to discriminate between the maximum harmonic multiplier max (kj) ¼ Nh and the number of harmonics computed per sample period Nt, with Nh Nt. For example, if Nt ¼ 4 we may compute the harmonic sequence {1, 3, 7, 16}, whereas with the contiguous processing model of Section 7.2 we were constrained to the contiguous sequence {1, 2, 3, 4}.

7.3.2

Modulo integer multiplication Figure 7.8 illustrates a harmonic phase sequence generator where the phase multiplying accumulator is replaced by an integer multiplier which computes the modulo-2M product of ϕ(n) and kj. This product represents a TDM harmonic phase sequence that we denote by ϕj(n) representing the harmonic multiple according to kj. We denote the phase truncated integer and fraction components by ϕjI ðnÞ and ϕjF ðnÞ, respectively. The sample period is partitioned into Nt computation time-slots whose index we denote by j, with j 2 [0, Nt 1]. There is now no explicit correspondence between the value of j and the harmonic multiplier. Instead, j indirectly specifies a new harmonic

264


φ j (n) I

ϕ

fs

M ∑

-1

z

kj

θj

K

M

I

∏

I

∑

Sinusoidal phase–amplitude mapping

⎛ 2π ⎞ ≈ cos⎜ I φ jI (n) + θ j ⎟ ⎝2 ⎠

φ j (n) F

F

φ (n) φ j ( n ) = k jφ ( n )

2M

M

Figure 7.8 Non-contiguous IDFT harmonic generation. Amplitude weighting and accumulation processing is identical to the contiguous harmonic case depicted in Figure 7.4.

multiplier parameter kj, that must now be supplied along with the phase offset and amplitude parameters. In most implementations, the integer multiplier processes asymmetrical operand word sizes where one operand is log2(Nh) bits and the other M bits, which can be large for fine frequency control resolution. For example, a 10 by 32-bit integer multiplier, which corresponds to 1024 harmonics and a 32-bit phase accumulator, is a reasonable expectation for this arithmetic function. Since we are concerned with integer operands and a product which must always be modulo-2M, it is evident that a simple ‘shift and add’ multiplier architecture is feasible motivated by modular arithmetic rules from number theory. Specifically, we appeal to the modular arithmetic reducibility and distributivity rules ha bin ¼ hhain hbinin and habin ¼ hhain hbinin, respectively. These rules allow us to express Eq. (7.10) in a form which is amenable to simple hardware implementation using a series of shift and add operations. We therefore obtain: hk j ϕðnÞi2M hk ð0Þ hϕðnÞi2M þ k ð1Þ h2ϕðnÞi2M þ þ k ðK1Þ 2K1 ϕðnÞi2M * + K 1 X i ¼ k ðiÞ h2 ϕðnÞi2M , i¼0

2M

ð7:11Þ

2M

where k(i) 2 {0, 1} and denotes the ith bit of the K ¼ dlog2 ðN h Þe bit harmonic multiplier word kj and we observe that kj 2 [0, 2K 1] using this denotation. Equation (7.11) is readily implemented in hardware using only left-shift, multiplexer and addition operations that we consider further in Chapter 8. For now, we accept that the harmonic multiplier block is straightforward to implement in hardware and is a viable option for a flexible real-time IDFT waveform synthesiser implementation.

7.4

Summary In this chapter we have developed the concept of phase domain processing to generate harmonic phase sequences from a DDS frequency synthesiser. Combined with sinusoidal phase–amplitude mapping, these sequences enable efficient computation of the

7.5 References

265

IDFT in real time. The amalgamation of DDS and the IDFT realises a periodic waveform synthesiser that uses a frequency domain specification comprising harmonic amplitude and phase parameters that may be adjusted in real time. After reviewing the IDFT as a waveform synthesis technique, we have investigated the arithmetic manipulation of a phase accumulator output sequence to generate integer multiples of a fundamental frequency determined by the phase increment. These phase sequences are mapped to sinusoids that form the harmonic basis signals in the IDFT sum-of-products computation. Accordingly, all IDFT harmonics are generated relative to this fundamental frequency as harmonic multiples. We have shown how the IDFT provides real-time spectrum control of a synthesised waveform which leads to the problem of generating the multiple harmonic amplitude and phase parameters in a given application. The concept of a so-called metaparameter and its mapping function have been introduced as one method of alleviating this problem, albeit in an application-specific context. One method, particularly suited to diagnostic signal emulation applications, captures reference waveforms, perhaps using a DSO. These waveforms are subsequently decomposed into their respective harmonic spectra, which are then modified to introduce some desirable additional or erroneous feature. A metaparameterised interpolation between ‘good’ and ‘erroneous’ spectra may then be used to control the IDFT to effect real-time generation of the emulated signal. Finally, we have investigated several arithmetic operations which are fundamental to an efficient hardware implementation of the DDS-IDFT in real time. We present the full processing architectures in Chapter 8. These operations comprise harmonic phase accumulation, ‘brute force’ harmonic multiplication of a fundamental phase sequence and arithmetic accumulation of the IDFT weighted harmonic amplitude samples.

7.5

References 1. Bar-Giora Goldberg, Digital Frequency Synthesis Demystified, LLH Technology Publishing, 1999. 2. H. A. Chamberlin, ‘Experimental Fourier series tone generator’, Journal of the Audio Engineering Society, 24, No. 4, May 1976. 3. H. A. Chamberlin, Musical Applications of Microprocessors (2nd edition), Hayden Books, 1987. 4. C. Roads, The Computer Music Tutorial, The MIT Press, 1996. 5. D. A. Jaffe, ‘Ten criteria for evaluating synthesis techniques’, Computer Music Journal, 19(1), pp. 76–87, 1995.

8


In this chapter we investigate hardware implementation of the DDS, sinusoidal and arbitrary waveform generation techniques presented in earlier chapters. We do not concern ourselves with specific target technologies such as FPGAs, but restrict our signal flow descriptions to the ‘ transfer level’ (RTL). The exact implementation technology (e.g. FPGA, ASIC or even hardwired logic) and the partitioning between hardware and embedded software are left to the suitably skilled reader and his or her application-specific requirements. For the most part, implementation of these algorithms, particularly in wide bandwidth applications, is best handled in high speed FPGA or ASIC logic. It is intended that this chapter will impart sufficient architectural detail to enable adaptation to any particular implementation technology. There are several processing strategies that underpin high speed DSP hardware implementation. These comprise arithmetic pipelining, time division multiplexing and parallel processing. We begin Section 8.1 by reviewing these techniques. We then discuss high speed pipelined implementation of the digital accumulator and its constituent adder which are fundamental building blocks in both DDS and the IDFT. Given its fundamental importance, we investigate wavetable memory architectures and introduce the idea of a ‘vector memory’ that produces a vector of consecutive data samples relative to a single base address in only one memory access cycle. This architecture employs a combination of parallel processing and pipelining. As we recall from Chapter 5, phase interpolated wavetable indexing requires multiple wavetable samples that surround the sample indexed by the integer part of the fractional phase index. The number of samples, and hence the length of the vector, are determined by the order of the interpolation polynomial. In Section 8.2 we investigate the novel idea of ‘partitioned phase accumulation’, which is of particular utility in the ‘speed-power’ optimisation of very high speed phase accumulators. In Section 8.3 we investigate pipelined linear phase interpolation hardware that is applicable to both DDS sinusoidal and arbitrary waveform generation. In Section 8.4 we combine pipelined vector memory and phase interpolation processing to produce a flexible interpolated wavetable memory architecture. This memory forms the basis of a high performance arbitrary waveform generator that uses polynomial phase interpolation. We conclude this section by presenting a waveform generator architecture that uses paged wavetable interpolation to provide dynamic control of waveshape, as introduced in Chapter 6.

8.1 Processing techniques and design considerations

267

Finally, in Section 8.5 we present a DDS phase–amplitude mapping processor that computes the IDFT in real time incorporating material introduced in Chapter 7. This allows us to specify and control the synthesised waveform in the frequency domain.

8.1

Processing techniques and design considerations In this section we outline several important techniques for implementing high speed digital arithmetic processing in hardware (e.g. FPGA). These are ‘system level’ architectural techniques primarily concerned with ‘top level’ signal flow between arithmetic blocks whose detailed implementation and optimisation are generally assumed (i.e. we treat these blocks as ‘black boxes’ that efficiently perform a particular arithmetic operation). However, given their ubiquity in sinusoidal and arbitrary waveform DDS, we investigate high speed adder and wavetable memory implementations. Broadly, these techniques can be grouped according to the following general classifications which we now discuss: parallel processing; sample and block level pipelined processing; time division multiplexing.

8.1.1

Pipelined and parallel processing Pipelined processing describes the division of a complex processing operation into multiple simpler elemental operations that are computed sequentially across multiple ‘subprocessors’ or processing elements (PEs) separated in time by digital s. Each elemental operation is computed by a dedicated PE that is ideally optimised for execution of that function. This is in contrast to the non-pipelined approach where a single processor performs all of the elemental operation in one time interval. PEs are therefore connected together in a serial arrangement, separated by s, with the output of one connecting to the input of the next, and so all of the PEs operate concurrently on different subtasks. Pipelined processing can be likened to a form of parallel processing where PEs in a linear array are all operating simultaneously, but separated in time. Pipelined processing is therefore analogous to a factory production line where each product is assembled in stages as it es down the line, with each stage performing a specific assembly task. In simple pipelined arithmetic processing, input data are fed to the first PE and, once processed, the result is presented to the next PE and so on until the processed data emerge from the last PE stage. All of the partitioning or pipelining s are clocked simultaneously at the sample frequency. A simple example will clarify this idea. Suppose we wish to compute the function y(n) ¼ acos(kx(n) þ m) every sample clock, where a, k and m are control parameters and x(n) is the discrete-time input operand. We could compute this function by brute force every sample clock, which would require two multiplications, one addition

268


and one cosine operation. Alternatively, in a pipelined computation we have (at least) four stages. The first stage computes the product kx(n), the second stage computes the addition kx(n) þ m, the third stage computes the cosine operation cos(kx(n) þ m) and finally the fourth stage computes the multiplication acos(kx(n) þ m) to yield the result y(n). There is clearly a four sample latency between input and output, but each stage now only has to compute a single operation per sample clock. This reduction in processing effort within each stage can be exploited in essentially one of two ways. The process can use slower logic and consume less power or can be optimised so that the slowest computation executes in just under a sample period, maximising throughput. For the waveform generation processors that we present in this chapter, several simplifying assumptions may be made to assist a pipelined implementation: the pipeline processes discrete-time data at a fixed clock frequency that may be the system sample frequency or an integer multiple thereof; the pipeline is constantly fed with input data and is completely synchronous; each pipeline stage has exactly one sample clock period to complete its particular operation; the most complex PE function must therefore always execute within one sample clock period; all of the waveform generation algorithms are feed-forward with no global paths; we may implement pipelined PEs that process single samples or blocks of samples in each clock interval. Synchronous pipelining requires that there be a pipeline between each PE in the chain and that all s be clocked simultaneously at the sample clock frequency. For any synchronous arithmetic pipeline, we define latency as the delay between a disturbance in the input data and the effects of that disturbance being observed in the processed output data. A p stage pipeline requires p pipeline s surrounding p 1 PEs and therefore incurs a fixed latency delay of pT seconds, where T denotes the sample clock period. Pipelined implementation of a particular algorithm therefore requires careful partitioning of the overall arithmetic process, taking of the pipeline clock frequency (e.g. the sample frequency or its integer multiple), hardware processing speed and permissible latency delay. The last consideration is particularly pertinent to control paths.

8.1.2

Sample and block pipelining In this chapter we are concerned with two distinct types of synchronous pipeline – sample and block pipelines. The principal difference between these two types of pipeline is the amount of data propagating through the pipeline on each sample clock event. In sample pipelining only a single sample propagates through the pipeline on each clock event. However, in block pipelining a block (or vector) of samples propagates on each clock. Figure 8.1 illustrates a hypothetical four-stage sample pipeline comprising three PEs and four unit-delay elements.

269


fs

x(n)

fs

z-1

PE 1

x( n − 1)

z-1

PE 2

z-1

z-1

PE 3

x3 ( n − 4)

x2 (n − 3)

x1 (n − 2)

T x(n) x( n − 1)

x1 (n − 2) x2 (n − 3) x3 ( n − 4)

4T Figure 8.1 A four-stage sample pipeline clocked by fs. The accompanying timing diagram

shows the progressive data propagation through the pipeline.

Assuming an input sample denoted by x(n), the first PE’s input is the unit-delayed input sample x(n 1), where each unit-delay is one sample clock period. The second PE’s input we denote by x1(n 2), and this is the unit-delayed output sample from the first PE. Similarly, the third PE’s input we denote by x2(n 3), and this is the unitdelayed output sample from the second PE. Finally, the pipeline output sample is the unit-delayed output from the third PE that we denote by x3(n 4). We observe a four-sample latency delay through the pipeline, which corresponds to the number of unit-delay pipeline s. For a given PE processing time tPE, any implementation requires that we must take of three parameters specific to the pipeline s – the minimum clock to data output valid time td, the input setup time ts and the input hold time th. In any hardware implementation we require that two inequalities are satisfied: th < td and td þ tPE þ ts < T. Many logic families are designed to have th ¼ 0, which ensures compliance with the first inequality. However, the second inequality forces a lower bound on T (and hence an upper bound on fs) set by td and ts, as tPE becomes smaller through the use of a faster processing logic. In block pipelining, a vector of samples propagates through the pipeline on each clock event. We assume that each PE is fast enough to be able to process multiple data values in each sample period. Block pipelining is a logical extension of sample pipelining and significantly enhances the throughput of algorithms which have vectors as their operands or process time multiplexed single samples. In a block pipelined processor chain, the s are replaced by dual-port memory (DPM) elements – both providing a unit sample delay. A DPM is characterised by a single physical memory space that may be accessed via two physically independent access ports, each with its

270


Sample index n + 1

Sample index n

Port 1

Block B

Port 2

Port 1

B⇒

⇒B x(n − 1)

x(n) ⇒A

Port 2

Block B

x(n + 1)

x(n)

Block A

Block A

A⇒

T

fs 2

MSB1 MSB 2

Port 1

⇒A

⇒B

Port 2

B⇒

A⇒

Figure 8.2 DPM ping-pong buffer arrangement. Physical memory spaces are written to and read from on alternate samples.

own control signals, address and data buses. In a block pipeline, entire blocks or vectors of data are processed en bloc within the same clock period by each PE. A particular PE reads data from an input DPM, processes it according to its function and then writes it into the output DPM. In this way, a vector of data now propagates along a concatenation of PEs. There is no reason, in principle, why data cannot propagate in both directions along such a pipeline and data flow is determined by the nature of the PE, since the DPM ports are usually read/write. A memory contention1 is prevented across the DPM by arranging the MSBs of the two DPM address ports to be mutually complementary and toggle at the block processing rate. This technique is also known as ‘ping pong’ or double buffering. If we assume the block processing rate is equal to the sample frequency fs, the port address MSB signals are anti-phase square waveforms at fs/2, effectively a ‘ping-pong clock’. In our block pipelining context, when one half of the DPM space is being written with data, the other half is being simultaneously read. This avoids memory access contention at the expense of introducing a latency delay of one block processing cycle. Figure 8.2 illustrates the ping-pong DPM concept and shows the same DPM over two consecutive samples. The physical DPM space is split into two blocks that we denote ‘Block A’ and ‘Block B’. In sample index n, Block A is written with data 1

A memory contention occurs when a DPM memory location is being written by one port simultaneously with being read or written by the other port, leading to the possibility of erroneous data transfer.


271

T fs 2

MSB1 MSB 2

‘Ping-pong’ clock

fs 2

x(n)

fs 2

DPM

DPM

PE 1

x(n − 1)

DPM

PE 2

x 2 ( n − 3)

x1 (n − 2)

T x(n) x( n − 1) x1 (n − 2) x 2 (n − 3) 3T Figure 8.3 A block processing pipeline using DPM storage elements. We denote the vector of

samples propagating along the pipeline by x.

simultaneously with Block B being read, producing the previous sample’s data. In the next sample (index n þ 1) Block B is now written with data simultaneously with Block A being read and producing the previous sample’s data. The timing diagram shows the DPM data port activity and the relative states of the respective address MSB lines MSB1 and MSB2 which effectively control data flow. Within each pipeline clock period, which we assume is the sample period T, each PE is able to read in, process and write out as many data operands as its execution speed and the DPM access cycle time will allow. This arrangement may be used to process a vector of samples en bloc or multiple independent samples from multiplexed channels according to the PE architecture. The latter mode is particularly suited to real-time pipelined TDM execution of the IDFT, as discussed in Chapter 7, where each harmonic is computed in a dedicated TDM pipeline. We apply this technique in Section 8.5. Figure 8.3 illustrates a simple block pipeline analogous to the sample pipeline of Figure 8.1. The first PE in Figure 8.3 processes the vector x(n 1) from the first DPM and writes the results x1(n 1) into the second DPM. The output of the second DPM x1(n 2) feeds the second PE which writes the results x2(n 2) into the third DPM. The vector x can represent a single data vector or a set of distinct multiplexed data samples – what matters is that a block of data is now being processed.

272


TSA f s 2

θ j (n)

Phase offset DPM

TSA f s 2

TSA f s 2 TSA f s 2

ϕ j (n)

Phase increment DPM

∑

State variable DPM

∑

Output DPM

φ j (n)

PE 2 PE 1

Figure 8.4 An example of a DPM block pipeline implementing a multichannel phase accumulator with phase offset. The multiple phase sequences are present in consecutive locations of the output DPM and updated at the sample rate fs. All data paths are M-bits wide.

8.1.3

Time division multiplexing Here we assume a TDM processing strategy with Np equally spaced processing timeslots across the sample period that might be used to compute the IDFT, as discussed in Chapter 7, with Np ¼ Nh. In order to control and synchronise data transfer through the pipeline, we generate a time-slot address (TSA) that partitions the sample period into Np equal duration intervals with TSA 2 [0, Np 1] and addresses all but the MSB of both DPM address ports. If we assume a radix-2 value of Np, the TSA is generated by a log2(Np)-bit counter clocked at Np fs and so the DPMs require 2N p þ1 locations. Each PE in the pipeline is now multiplexed across Np state variables according to the TSA. This approach is strictly a TDM implementation of the single sample pipeline. Within each time-slot, a PE may read both state variable (i.e. data samples) and control parameters from separate DPMs as required. In principle, each PE may read any number of data values from ‘upstream’ DPMs and similarly write any number of results into the ‘downstream’ DPMs. The number of read or write operations is bound by the sample time T, the DPM access time and PE processing speed. Figure 8.4 illustrates a DPM block pipeline where we multiplex a phase accumulator and phase offset adder using these principles. In effect, this processor computes Np distinct phase accumulating frequency synthesisers every sample period, where the instantaneous phase of each synthesiser is stored in the output DPM. The pipeline accepts Np phase increment and phase offset input parameters that we denote by φj(n) and θj(n), respectively, and computes Np output phase sequences ϕj(n). In this simple example, each PE is only a single M-bit adder. Each DPM block shows the TSA address input and fs/2 ping-pong clock which drives the pipeline. This pipeline example uses two state variables stored in the DPMs and requires two control signals – the ping-pong clock and the TSA. We also observe that in each time-slot, an additional control signal


273

(not shown) is required to control each DPM write operation on every Np fs clock. As this occurs at the fs rate on each channel, it is this write operation that represents the multiplexed phase accumulator sample clock.

8.1.4

Arithmetic and modulo accumulation The digital accumulator is a fundamental arithmetic operation in DSP systems. Many DSP algorithms, including the IDFT, can be represented as a ‘sum-of-products’, and when the number of product becomes large, an accumulator offers an efficient solution. In phase accumulating frequency synthesis (i.e. DDS) and the IDFT phase– amplitude mapping algorithm, the digital accumulator undertakes two subtly different functions: M as a modulo 2 phase accumulator with signed or unsigned arithmetic where overflow and wraparound are necessary to emulate modulo 2π phase wrapping; as an arithmetic accumulator using signed arithmetic, where overflow or underflow must be prevented as they represent amplitude saturation or ‘clipping’.

Both applications may use signed 2’s complement arithmetic. The arithmetic accumulation operation is typically preceded by a multiplier to implement the so-called multiply-accumulate operation. The accumulator dynamic range (i.e. word length) must now accommodate both the double width multiplier output word and ‘word growth’ due to multiple accumulations, without saturating. If the amplitude samples are represented with b bits in a fixed-point representation, the multiplier output requires 2b bits to avoid rounding or truncation errors. The accumulator will therefore require more than 2b bits to avoid saturating. The number of additional ‘headroom’ bits is a function of the number of potential full-scale accumulations. If we accumulate two full-scale samples, the accumulator requires one extra bit to accommodate the worst case result. Similarly, accumulating four full-scale samples requires two extra bits to accommodate the worst case result. In general, accumulating Nh full-scale samples requires 2b þ dlog2 (Nh)e bits. This scenario is unlikely in practice and so we may choose to append fewer headroom bits. In practice, the accumulator word size is likely to exceed the resolution of the DAC, which typically follows the IDFT waveform synthesiser. For example, let us assume a 16-bit fixed-point fractional 2’s complement sample representation and a 16-bit DAC. The multiplier output will then be 32-bits wide and, assuming a 256 harmonic summation, the total accumulator word size would be 40-bits if we do not truncate the multiplier output. It is important to that, at least in principle, all of these 40-bits may contain valid information. However, a 40-bit DAC is somewhat impractical and so we are forced to truncate the accumulator output in some way. The simplest option is to truncate (or round) the 24 LSBs from the accumulator and use the 16 MSBs to drive the DAC. However, this ‘wastes’ DAC resolution when we sum significantly fewer than 256 harmonics and the waveform amplitude at the accumulator output is well below full-scale. An optimum solution is to place a barrel shifter between the accumulator and the DAC and set the block shift so that the 16 active accumulator

274


output bits are fed to the DAC. The DAC output will now always be normalised to fullscale. The block shift value is set according to the number of harmonics (i.e. Nh) summed to produce the output waveform. The block shift may also be used to scale the DAC output in the analogue domain, using a switched gain amplifier (or attenuator) to increase the dynamic range in a floating-point fashion. In the phase accumulator case, signed phase increments and modulo 2M underflow and wraparound exactly emulate the generation of a negative frequency which is necessary in specific frequency modulation (FM) applications. In many instrumentation applications, however, the phase accumulator need only use unsigned arithmetic (i.e. to generate positive frequencies).

8.1.5

High speed binary addition The binary addition function is fundamental to accumulator implementation. Apart from the holding , initialisation multiplexer and associated control logic, the adder is the most complex logic element within the accumulator. A binary adder which adds two b-bit binary words can be implemented with a concatenation of b 1-bit full-adder stages, with each handling one bit. This type of adder structure is known as a ripple carry adder and is well documented in the literature [1]. The least significant full-adder carry input c0 is usually set to 0, and the carry output of each full-adder is connected to the carry input of the next. Unless we are performing modulo addition (e.g. as in the phase offset adder), two b-bit operands require a b þ 1-bit result. The final carry out represents the extra bit. A binary adder based on ripple carry propagation is inherently slow, since the worst case carry must propagate from the least significant full-adder to the most significant one. Clearly, the speed of a ripple carry adder is limited by the cumulative propagation delay in the ripple carry path, which can be significant for large adders. If we assume that the operands are fed to the adder simultaneously, the worst case addition time is given by tΣ ¼ t1 þ (b 2)t2 þ t3, where t1 is the propagation delay from the operand inputs to the carry-out of each adder stage, t2 is the propagation delay from the carry-in to the carry-out of each stage and t3 is the propagation delay from the carry-in to the adder output of each adder stage. Clearly when b is large, the ripple carry propagation delay t2 dominates the worst case addition time. A significantly faster adder can be realised by using the concept of carry lookahead. The carry lookahead block calculates the ith stage carry in ci using two rules – carry generate and carry propagate. For a particular combination of adder operands xi and yi, the adder stage i generates a carry if it produces a carry-out of 1 (i.e. ciþ1 ¼ 1) independent of the x and y inputs and c0. For a particular combination of adder operands xi and yi, the adder stage i propagates carries if it produces a carry-out of 1 (i.e. ciþ1 ¼ 1) when the x and y inputs and c0 cause a carry-in of 1 (i.e. ci ¼ 1). Using these definitions we define two new variables, carry-generate gi ¼ xi · yi and carry-propagate pi ¼ xi þ yi, where the · and þ operators denote logical AND and OR operations, respectively. The carry output of any stage can now be expressed in of the generate and propagate signals and the carry input, thus ciþ1 ¼ gi þ pi · ci. Carry ripple


275

is eliminated by recursively expanding the ci term for each stage and simplifying to a 2-level AND–OR expression. Each ci term now requires only three levels of logic delay – one for the generate and propagate signals and two for the logic sum-of-product [1]. A carry lookahead adder uses these three-level Boolean expressions within the ‘carry lookahead logic’ block of each adder stage. The sum output for any stage is calculated by combining the carry bit (from the lookahead logic) with the two addend bits xi and yi. However, it is also possible to design multi-bit adders and use carry lookahead internally to generate carries. We then apply ripple carry across the multi-bit groups to form a so-called group-ripple adder. Various implementation methods are described in [1]. Inspection of the addition and carry logic reveals that both the ripple and carry lookahead adders are easily pipelined. For the ripple carry adder, the pipeline s are placed in the ripple carry path as this is the path with the longest propagation delay. However, the input operands must now be delayed in a staggered fashion to ensure that the operands and their corresponding pipelined carry bits arrive at each adder block simultaneously. This delay or data pre skewing is strictly not part of the pipelined data flow, but rather a data alignment mechanism to ensure correct operation. Similarly, the early computed sum bits must be appropriately delayed or de-skewed to ensure that the result word is correctly bit-aligned before the next processing stage. Figure 8.5 illustrates the placement of pipeline, pre-skewing and de-skewing delays in an example 4-bit ripple carry adder. This methodology can be applied to any length of adder as discussed in [1].

8.1.6

Wavetable memory architectures In earlier chapters we have shown that the wavetable is a fundamentally important element in both sinusoidal and arbitrary waveform phase–amplitude mapping. In hardware , the wavetable is simply a memory block addressed by the integer component ϕI (n) of the fractionally partitioned phase accumulator output sequence ϕ(n). Depending on the order of the phase interpolation polynomial used, there are multiple read operations required around the ϕI (n) value on each sample clock event. For example, with linear interpolation we require wavetable read operations from two locations addressed by ϕI (n) and ϕI (n) þ 1. Similarly, with cubic interpolation we require wavetable read operations from the four locations addressed by ϕI (n) 1, ϕI (n), ϕI (n) þ 1 and ϕI (n) þ 2. Clearly, for phase interpolated wavetable indexing using an order-N interpolation polynomial and implemented with sequential memory addressing, the wavetable memory must be accessed N þ 1 times on each sample clock. This causes a significant memory access bottleneck when the interpolation polynomial is high order (e.g. cubic). Even linear phase interpolation halves the effective memory speed with sequential addressing. If we consider advanced waveform generation systems that use paged wavetable interpolation to control waveshape, as discussed in Chapter 6, the memory read bottleneck compounds further since two wavetable phase interpolated samples are required to compute each linearly interpolated output sample from the two pages. Assuming each of

276


Pipeline clocked at f s s4 co b3

∑

s3

∑

s2

∑

s1

∑

s0

a3

b2

a2

b1

a1

b0

a0 ci 0 Lines of constant pipeline delay Figure 8.5 A hypothetical 4-bit pipelined ripple carry adder.

these samples is linear phase interpolated, we have a fourfold reduction in effective memory speed with sequential addressing of a single wavetable memory. With cubic phase interpolation, this increases to an eightfold reduction in effective memory speed. An alternative approach that is a reasonable proposition, given the ever-reducing cost of semiconductor memory, is to simply duplicate the wavetable memories in a redundant architecture. Our linear phase interpolated example outlined above now has two


277

identical wavetable memory arrays running in parallel. One is indexed by ϕI (n) and the other by ϕI (n)þ1 to produce the two operands for the subsequent linear interpolation calculation in parallel. This may seem wasteful, but it does allow the memories to be accessed at full speed and the sample period matched to the memory cycle time. The downside is increased cost, power consumption and, on first inspection, wavetable fill time. However, each wavetable contains exactly the same tabulated waveform function and so both can be written in parallel thereby incurring no increase in fill time compared to a single wavetable. This is true for any number of parallel wavetables. It is evident that for higher phase interpolation orders combined with paged wavetable interpolation, the amount of duplicated memory may start to become prohibitive and a more efficient memory architecture is required.

8.1.7

Vector memory In this section we introduce a data-parallel memory architecture that enables random access of a consecutive data block or vector from a single logical base address. This architecture is readily extensible to any radix-2 vector length. A vector memory architecture is motivated by the data requirements of phase interpolated wavetable indexing discussed in Chapter 5, which requires N þ 1 wavetable samples (i.e. the sample set) for an order-N interpolation. This vector, together with coefficients computed from the phase fraction component, is used to calculate an interpolated wavetable sample that approximates the ideal sample at an arbitrary fractional address. High speed execution of an order-N phase interpolation using data-parallel arithmetic processing requires that all N þ 1 wavetable samples in the vector be available simultaneously from a single read operation, every sample period. A sequentially indexed single memory produces a set of samples, but requires multiple consecutive read operations and is therefore inherently slow. Fundamentally, an order-N polynomial phase interpolation requires N þ 1 memory read operations and is therefore N þ 1 times slower than a single phase truncated memory indexing operation. One method for speeding up this operation is to use N þ 1 duplicate wavetable memories in parallel, with each tabulating the same waveform function. Each wavetable in the set is progressively phase retarded by one sample modulo the wavetable length. For a given phase index ϕI, the N þ 1 memories output the N þ 1 distinct data points in contiguous order with respect to the memory ports. The downside of this approach is that N additional redundant memories are required compared to the single memory case. A parallel redundant memory array is a simple, but inefficient, example of a vector memory that produces a vector of samples on each read operation. Before describing the vector memory architecture in detail, we review its function as a ‘black box’ with respect to the logical address input and sample set vector output. In the discussions which follow, we omit the discrete-time sequence indices for brevity and use ϕI, ϕF and α to represent the phase sequences normally denoted by ϕI (n), ϕF (n) and α(n), respectively. Finally, for clarity, we do not show the additional multiplexer logic which is required for a host system to access and fill the memory arrays. For a logical address ϕI, indexing a wavetable which we denote by the vector W, this vector memory

278


architecture produces the set of k wavetable samples {W[ϕI], W[ϕI þ 1], W[ϕI þ 2], . . ., W[ϕI þ (k 1)]} simultaneously from k separate output ports. Optimal order-N polynomial interpolation (i.e. with minimum error bound) requires that the fractional address lie within the middle sub-interval of the sample set for all odd-order interpolation calculations or within either sub-interval about the middle sample of the sample set for all even-order interpolation calculations. By adding a fixed offset j to the logical address, the sample set can be positioned arbitrarily with respect to W[ϕI] and we obtain the sample set {W[ϕI þ j], W[ϕI þ j þ 1], W[ϕI þ j þ 2], . . ., W[ϕI þ j þ (k 1)]}. By setting j ¼ b(N 1)/2c with k ¼ N þ 1, we obtain the sample set required for an optimal order-N interpolation having minimum interpolation error bound. In the following discussion, we describe memory operation using a non-offset logical base address to simplify explanation of the concept. We also observe that this vector memory architecture is only suitable for odd-order interpolation sample sets requiring a radix-2 number of samples in the vector (i.e. 2, 4, 8, etc.). Unlike the parallel memory configuration, this memory architecture does not require duplication of data across multiple memories, and so no memory is wasted. The key idea is that groups of k consecutive samples are now uniquely stored across k separate memory blocks, where k is a radix-2 number (i.e. 2, 4, 8, etc.). This requires an unusual addressing strategy that causes the order of the k samples in the output vector to take on k cyclic permutations of the ‘ideal’ consecutively ordered sample set {W[ϕI], W[ϕI þ 1], W[ϕI þ 2], . . ., W[ϕI þ (k 1)]} with respect to the k output ports depending on the phase index ϕI. Data re-ordering multiplexers controlled from the logical address realign the data samples into the correct sequential order. This vector memory architecture comprises three sequential processing elements – logical to physical address translation, a parallel memory array and output data re-ordering – and is inherently amenable to pipelined hardware implementation. To illustrate its operation, we first consider the memory structure for the simplest case comprising two memories that produce the two sample set {W[ϕI], W[ϕI þ 1]}, as required for linear phase interpolation where N ¼ 1 and k ¼ 2. We assume a memory vector W, of radix-2 length 2P L, which contains 2P wavetables each of length L that we index with the page address p as described in Chapter 6 to effect dynamic waveshape control. The physical vector memory comprises two distinct memory blocks denoted by the vectors B0 and B1, each of length 2P L/2 samples where block B0 holds k-spaced even address samples and block B1 holds k-spaced odd address samples of the vector W. This data structure is exemplified in Figure 8.6 for the illustrative case where L ¼ 8. It is clear that memory blocks B0 and B1 are written with data from W according to: B0 ½n ¼ W½2n, B1 ½n ¼ W½2n þ 1,

ð8:1Þ

where n 2 [0, 2P1 L 1]. Assuming a radix-2 L, we partition the log2 (2P L)-bit logical address into two fields – a phase index ϕI 2 [0, L 1] comprising the log2 (L) ¼ I least significant bits that address a particular wavetable sample modulo-L, and a wavetable index component p 2 [0, 2P 1] that selects a particular wavetable from the set of 2P wavetables and comprises the P most significant bits.

279


Logical wavetable memory space

W[φI ] 2P L L

L 0

1

2

3

4

5

6

7

0

1

2

p=0

3

4

5

6

7

5

6

7

p =1

First sample in sample set 0

2

4

6

0

2

4

B0 [φ0 ] ⇒ 0

6

L 2 1

3

2

2

4

0

1

0

1

B1 [φ1 ] ⇒ 1

1

3

3

0

1

0

s0 5

7

1

3

5

7

s1 p=0

1

p =1

Physical wavetable memories Figure 8.6 Logical and physical memory structures for a simple vector memory that produces

two consecutive samples in parallel on each read operation.

The phase index ϕI is transformed into two physical block addresses ϕ0 2 [0, L/2 1] and ϕ1 2 [0, L/2 1],2 which address memory blocks B0 and B1 modulo-L/2, respectively. The ϕ0 and ϕ1 block addresses are defined so as to index the {W[ϕI], W[ϕI þ 1]} sample set as ϕI varies over the range of permissible values (i.e. ϕI 2 [0, 2I 1]). The block addresses are defined by: ϕI þ 1 ϕ0 ¼ L 2 , ϕ1 ¼

ϕI 2

2

ð8:2Þ

L : 2

Additionally, we define ‘sample position’ indices s0 and s1 that are each associated with a respective memory block output and indicate the position of a corresponding data value within the ordered sample set (i.e. the first or second element in the two-element vector sample set). For example, s0 ¼ 0 indicates that the current sample from memory block B0 is the first sample in the set. Similarly, s0 ¼ 1 indicates that the current sample from memory block B0 is the second sample in the set. The logical to physical address transformation from ϕI to ϕ0 and ϕ1, causes the memory blocks to output the sample set {W[ϕI], W[ϕI þ 1]}, but with a sample order dependent 2

The reader should observe the distinction between the denotations of the first block address ϕ1 and the truncated phase index ϕI to avoid confusion.

280


Address translation

Data re-ordering s0

1

∑

φI (n)

Parallel memory

⎢x⎥ ⎢⎣ 2 ⎥⎦

B0 memory

0 Mux

W[φ I ]

1 p (n) 0

⎢x⎥ ⎢⎣ 2 ⎥⎦

Mux B1 memory

W[φ I + 1]

1 s1

Figure 8.7 Signal flow for a simple vector memory producing two consecutive samples. We consider a pipelined implementation of this architecture in Section 8.4.1.

on the value of ϕI as reflected in the values of s0 and s1. If ϕI is even or zero, W[ϕI] sample-types are output from block B0 and W[ϕI þ 1] sample-types are output from block B1. Conversely, if ϕI is odd, W[ϕI þ 1] sample-types are output from block B0 and W[ϕI] sample-types are output from block B1. For our present example we are therefore concerned with determining whether ϕI is odd or even and so s0 is the least significant bit of the phase index ϕI. Conversely, s1 is the inverted least significant bit of ϕI. In general, the quotient L/k must take on exact integer values to ensure that consecutive samples are unambiguously allocated across memory blocks. For example, with L ¼ 7 and hence L/2 2 = Z, we observe that W[0] and W[6], which are consecutive modulo-7, are both stored in memory block B0 and hence cannot be accessed simultaneously as required in subsequent interpolation processing. In general, constraining 2P L, L and k to radix-2 values, always guarantees unique allocation of waveform samples across memory blocks with modulo-L/k addressing wraparound. Figure 8.7 illustrates the signal flow architecture of a simple vector memory that produces a sample set of two consecutive samples on each read operation. This architecture implements the addressing and data re-ordering strategy described above.

8.2

Partitioned phase accumulation In this section we introduce a novel technique for partitioning the hardware implementation of a phase accumulator as first suggested by Goldberg [2]. The principal utility of this approach is that for a given sample clock frequency fs and frequency control resolution fr ¼ fs/2M, it provides a structured method for reducing the amount of logic

8.2 Partitioned phase accumulation

281

clocked at the sample frequency. The sample frequency sets the maximum synthesised frequency according to the Nyquist limit of fs/2, and can be arbitrarily high. The principal upper limitation on sample frequency (discounting the DAC) is the addition time in the phase accumulator, which is a function of word length and adder logic propagation time. In a conventional phase accumulator design, the phase additions must take place in a single sample period. Furthermore, all of the accumulator s must be clocked at the sample frequency, which increases power consumption leading to heat dissipation and clock distribution problems (i.e. potential clock skew) in very high speed implementations (i.e. high sample frequency). Pipelining the phase adder is one method for easing the size of addition in each sample period, at the expense of latency which can be tolerated in many applications. However, this exacerbates the power consumption and clock distribution problems since more pipeline s are now being clocked. This technique is primarily a method for minimising the amount of logic clocked at high frequencies and becomes more relevant as sample frequencies approach and exceed the gigahertz level. The fundamental idea is very simple. We have seen from Section 7.1.2 that the addition of two coherent phase sequences produces a new phase sequence whose frequency is the sum of the frequencies of the two component phase sequences. Here, coherency refers to both phase accumulators being clocked at the same sample frequency. However, this is actually not a strict requirement, provided the two phase accumulators have sample frequencies that are an exact radix-2 ratio with the same master clock (i.e. coherent) and that we observe certain subtleties in how the two phase sequences are combined. A specific example will help clarify application of the technique. Let us suppose we have an existing phase accumulator with word size M, phase increment φ and clocked at sampling frequency fs, that we wish to partition into two separate accumulators whose outputs are summed to form the phase sequence ϕI (n). We must also determine the degree of phase truncation required, and hence the number of output phase states 2I, where I is the output word size in bits. To partition this phase accumulator we require two phase accumulators with sample frequencies fs and fs/D, and corresponding word sizes denoted by M1 and M2, respectively. The clock division is typically implemented with a d ¼ log2 (D) bit counter (i.e. D ¼ 2d). In practice, we begin by choosing D (and hence d) to ensure that for a given value of fs, fs/D is low enough to not cause significant power consumption or logic design complexity in the low speed phase accumulator. This is largely a function of the implementation technology chosen for the low speed phase accumulator (e.g. CMOS). Next, the value of M1 is chosen according to the simple relationship M1 ¼ d þ I, and ensures that the frequency control weighting of the high speed phase accumulator phase increment LSB is fs/(2d þ I). We choose M2 according to M ¼ M2 þ d, which gives a frequency control resolution of fr ¼ fs =2M 2 þd that matches the M-bit design that we wish to replicate. The phase increment φ is partitioned into two fields φ1 and φ2, which control each phase accumulator. φ1 comprises the M1 MSBs of φ and controls the high speed phase accumulator directly. The remaining φ2 LSBs of φ control the low speed phase


fs 2

MSB 1 2

ϕ1

fs

16

fs 4

∑ 16

f s 215

15

f s 216

16

z-1 10

16

LSB

ϕ

10 MSBs = 0 24 f s 217

∑

10

MSB 11

10

φI (n)

f s 26

34

10

∑

z

-1

282

ϕ2

33

f s 239 fs 2

34

34

40

LSB Figure 8.8 A hypothetical phase accumulator partitioning, where the amount of logic clocked at fs is reduced from M ¼ 40 to M ¼ 16.

accumulator. However, since the low speed M2-bit phase accumulator is clocked at a lower frequency of fs/D, we must set the I ¼ M1 d MSBs to zero and align φ2 with the remaining M2 M1 þ d LSBs to effect proper frequency control. Effectively, the ‘new’ MSB of the low speed phase accumulator is now bit M1 d þ 1 or I þ 1, where the MSB is counted as bit 1. The frequency control weighting of the new MSB, as a fraction of fs, is now the next radix-2 fraction below the LSB of the high speed phase accumulator. This arrangement effectively implements an M2 þ d ¼ M bit phase accumulator. We observe that for correct operation, it is imperative that the I MSBs of the low speed phase accumulator are held at zero and not driven with phase increment information. Both phase accumulator output sequences are truncated to I-bits by taking the I MSBs of each output . The phase sequences are then summed together using an I-bit adder to form the output phase sequence, possibly with pipelined partitioning since this adder is operating at fs. This adder must operate at the high sample frequency fs, and so I should be chosen with this consideration in mind (i.e. minimisation of high speed logic and pipeline s). This arrangement is illustrated in Figure 8.8 for a specific hypothetical phase accumulator where M ¼ 40 that we partition with I ¼ 10, M1 ¼ 16,


283

M2 ¼ 34, D ¼ 64 and so d ¼ 6. Following the above discussion, the upper 10 MSBs of the low speed accumulator are set to zero, making bit 11 the new MSB with frequency weighting fs/217, which follows from the LSB of the high speed phase accumulator whose frequency weighting is fs/216. We have an effective phase accumulator width of 40-bits, as required, but only 16-bits are clocked at the fast sample rate. We have reduced the high speed logic requirement from 40-bits to 16-bits – a substantial saving. To set the design advantages of phase accumulator partitioning in context, if we set fs 1.0995 GHz, giving a frequency control resolution of 0.001 Hz, then fs/64 is only around 16 MHz and does not impose a significant power consumption or clock distribution problem in many applications. Clearly, the phase accumulator partitioning can be imposed in many ways according to the values of I, d, M1 and M2. There is fundamentally a trade-off between the amount of fast clocked logic (as determined by M1 and I) and slow clocked logic determined by d and M2, for a given value of I. In general, for a given I requirement (i.e. phase amplitude mapping accuracy), the value of M1 is determined by an acceptable value of d according to the speed at which we wish to clock the low speed phase accumulator. In effect, the number of unused fraction bits in the fast phase accumulator (i.e. M1 I) is determined by the fraction of fs at which we clock the slow phase accumulator. The more fraction bits (and hence fast clocked logic), the slower we can operate the low speed phase accumulator. Exact values depend on implementation technology (e.g. FPGA, ASIC, discrete logic, etc.) and invariably require trade-offs and compromises to be made which consider wider system-level requirements. Figure 8.9 illustrates a generic phase accumulator partitioning, which shows the ‘new’ MSB position I þ 1 in the low frequency phase accumulator, with the upper I bits always set to zero. The output phase adder which combines the two phase sequences is I bits wide. If we assume a baseline M-bit phase accumulator design with an I-bit truncated output sequence clocked at fs and phase increment φ, we can summarise the partitioning design process thus: determine a radix-2 value of D and hence d according to the required low frequency phase accumulator clock frequency fs/D; for a given value of I, determine the high speed phase accumulator word size from M1 ¼ d þ I; determine M2 from M2 ¼ M d; partition φ into two fields φ1 ¼ M1 and φ2 ¼ M2 1 comprising the MSBs and LSBs of φ, respectively.

8.3

Sinusoidal phase–amplitude mapping In this section we outline two phase interpolation methods specific to sinusoidal phase– amplitude mapping, before moving on to hardware processing architectures specific to DDS AWG in Section 8.4. The first is an efficient implementation of linear phase interpolation which, as we have seen from the simulation results presented in Chapter 4,

284


fs 2

MSB 1

2

fs 4

ϕ1

M1

f s 2 M 1 −1 fs 2

fs

M1

∑

M1 −1

I

M1

M1

z-1

M1

LSB

ϕ

I MSBs = 0

M2 − I

I

MSB I +1

d + I +2

I +2

ϕ2

fs 2

f s 2 M 2 +d −1

I

φ I (n)

f s 2d

M2

I

∑

z-1

d +I +1

fs 2

∑

M 2 −1

M2

M2

f s 2M 2 +d

LSB Figure 8.9 Phase accumulator partitioning for the generic case where we partition an M-bit design according to the design parameters fs, D and I.

provides near-ideal performance in almost all sinusoidal DDS applications. The second method shows implementations of the trigonometric phase interpolation algorithm which provides optimal quadrature sinusoidal phase-amplitude mapping, with spurious components bound only by amplitude quantisation noise. Alternative, more efficient hardware implementations3 based upon both of these approaches, such as the Hutchison and Sunderland algorithms, are well documented in the literature [3] and do not concern us further here.

8.3.1

Linear phase interpolation Linear phase interpolation of a sinusoidal wavetable may be implemented in essentially two ways – two consecutive read operations from a single wavetable memory, or two parallel read operations from two memories. Implementation of the first approach is straightforward, although slow, and requires a holding to store the first wavetable data value while the second read operation is taking place. An alternative and more 3

In this context, ‘efficient’ is measured in of logic gate count or equivalent silicon area in an ASIC or fully custom IC implementation.


285

Pipeline clocked at f s

φ I (n − 1) I φ (n)

M

⎡ φ (n − 3) ⎤ cos ⎢2π I I ⎥ 2 ⎣ ⎦

Cosine wavetable

I

b

I

First-order difference table

b′

∑ ∏

F

⎡ φ (n − 4) ⎤ ≈ cos ⎢2π 2 M ⎥⎦ ⎣

φF (n − 1) ⎡ (φ (n − 2) + 1)⎤ ⎡ φ I ( n − 2) ⎤ cos ⎢2π I ⎥⎦ − cos ⎢⎣2π ⎥⎦ 2I 2I ⎣

⎡ (φI (n − 3) + 1)⎤ ⎡ φ (n − 3) ⎤ ⎞ − cos⎢2π I I I ⎜⎜ cos⎢2π ⎥ ⎥⎦ ⎟⎟ 2 2 ⎦ ⎣ ⎠ ⎝ ⎣

φF ( n − 3) ⎛ 2F

Figure 8.10 A pipelined sinusoidal phase–amplitude mapping using a parallel memory

architecture. The cosine wavetable can be compressed fourfold using the compression techniques in Section 4.3.6.

efficient approach uses a parallel memory structure, as illustrated in Figure 8.10. This approach is effectively a simplified implementation of a vector memory introduced earlier. Here we have two wavetable memories. The first memory tabulates the entire sine waveform, although the lossless quadrature symmetry compression technique as discussed in Chapter 4 may be used to reduce the memory requirement by four. The second memory tabulates the first-order difference of the waveform over the entire sine waveform cycle, and for the cosine function is given by f 0 (n) ¼ cos [2π(ϕ1(n) þ 1)/2I] cos[2πϕI (n)/2I] for ϕI (n) 2 [0, 2I 1]. The lookup table, which we denote by the vector D, is tabulated according to: ð a þ 1Þ a D½a ¼ Q cos 2π cos 2π , 2I 2I

ð8:3Þ

where a 2 [0, 2I 1] and Q(x) is the fixed-point amplitude quantisation function to a specified number of bits according to the wavetable word size. This approach provides data parallelism and ensures the interpolated sample is computed with a single parallel table lookup operation as illustrated in the pipelined processing architecture of Figure 8.10. Linear phase interpolation is now the linear combination of the two data values according to the fractional phase value ϕF (n). It is evident that the interpolation multiplier requires asymmetrical operand word sizes which may realise cost savings in some hardware implementations (e.g. FPGA or VLSI). The phase fraction operand ϕF(n) requires F bits, yet the first-order difference operand always requires less than the b bits which represent the sinusoid samples. We estimate the word size required to represent the first-order difference samples by observing that max (j f 0 (n)j) sin(2π/2I) 2π/2I for 2I >> 1. Since b 1 bits represent

286


the sample magnitude in a fixed-point 2’s complement representation, the required word size b0 for the first-order difference lookup table samples is therefore b0 ¼ dlog2(2b1(2π/2I))e þ 1 bits, assuming 2I >> 1. For example, with I ¼ 10 and b ¼ 16 (i.e. a 1024 sample sine wavetable and 16-bit fixed-point number representation) we require only 9 bits to represent the first-order difference samples. Therefore, the interpolation multiplier need only be F 9 bits.

8.3.2

Trigonometric identity phase interpolation In Chapter 4 we introduced the concept of trigonometric identity phase interpolation as an optimum sinusoidal phase–amplitude mapping algorithm that effectively uses all M-bits of the phase accumulator output, with no arithmetic approximations. There are now no phase truncation errors and SNR is defined by quantisation noise alone. Here we present two pipelined implementations of this technique – one for a single sinusoid output and another which generates exactly quadrature sinusoids, but requires one less multiplier operation. Figure 8.11 illustrates a single sinusoid phase–amplitude mapping processor that uses trigonometric identity phase interpolation. In both implementations, the four wavetables are tabulated according to the expressions presented in Section 4.3.5. Figure 8.12 illustrates a reduced multiplier implementation based upon arithmetic manipulation of Eqs. (4.44) and (4.45). Arithmetic saving arises from identifying the common term cos(A)[cos(B) þ sin(B)], giving: sinðA þ BÞ ¼ cosðAÞ½ cosðBÞ þ sinðBÞ þ cosðBÞ½ sinðAÞ cosðAÞ:

ð8:4Þ

cosðA þ BÞ ¼ cosðAÞ½ cosðBÞ þ sinðBÞ sinðBÞ½ sinðAÞ þ cosðAÞ:

ð8:5Þ

Simultaneous execution of Eqs. (8.4) and (8.5) requires four wavetable read operations, three multiplications, three additions and two subtractions. In effect, this implementation exchanges one multiply operation for one addition and two subtraction operations, and may be advantageous in some applications. For the condition I ¼ F, the fractional phase ranges over smaller positive intervals as M increases. The corresponding sine and cosine fractional amplitude values are therefore always positive and tend to zero and one respectively as M increases. Hence, the fractional sine and cosine tabulated in lookup tables W4 and W3 require fewer bits for accurate representation within a fixed-point number system. It is clear from the Taylor series expansions of sin(x) and cos(x) that sin(x) ! x and cos(x) ! 1 as x ! 0. The maximum fractional phase angle is 2π(2F 1)/2M ffi 2π2I radians for 2F >> 1, and so the corresponding fractional sine and cosine amplitude values are sin(2π2I) 0 and cos(2π2I) 1, respectively. A 2’s complement fixed-point number representation of b-bits has a resolution (quantisation interval) of 2(b1) normalised to a full-scale range of [1, (1 2(b1))]. Hence, an arbitrary value x lying within the positive half of the range (i.e. x 2 [0, (1 2(b1))]) requires b0 ¼ log2dx/(2(b1))e bits of the available (b 1)-bit fraction field

287


Pipeline clocked at f s W1 wavetable

∏

φ I (n) ∑ W2 wavetable

⎛ 2π ⎞ sin ⎜ M φ ( n) ⎟ 2 ⎝ ⎠

∏

W3 wavetable

φ F (n) W4 wavetable Figure 8.11 A pipelined optimal sinusoidal phase–amplitude mapping processor using trigonometric identity phase interpolation.

to represent it, with the remaining b 1 b0 bits set to 0. Similarly, an arbitrary value a lying very close to positive full-scale (i.e. x ! (1 2(b1))), requires b0 ¼ log2d(1 x)/(2(b1))e bits of the available (b 1)-bit field to represent it, with the remaining b 1 b0 bits set to 1. We therefore observe a reduction in the number of bits required to accurately represent our fractional sine and cosine amplitude values, giving a corresponding memory saving. We can assess the saving in arithmetic word size by considering an example where b ¼ 24, M ¼ 24 and I ¼ 12 for optimum lookup table memory utilisation. We then have sin(2π2I) 0.001534 and cos(2π2I) 0.999999. The corresponding 24-bit 2’s complement fixed-point binary sample representations are therefore (0) 000 0000 0011 0010 0100 0100 and (0) 111 1111 1111 1111 1111 0110, respectively where (0) denotes the sign bit value and the shaded areas indicate the significant bits. Hence, we have b0 ¼ 14 and b0 ¼ 4 for the fractional sine and cosine amplitude values, respectively. This saving in arithmetic word size affords a significant reduction in wavetable memory and multiplier gate count in some implementations. For our above example, we now require 24 14 and 24 4 bit multipliers for the fractional sine and cosine , respectively. Finally, for arithmetic processing where b < 20, M ¼ 24 and I ¼ F ¼ 12, the fractional cosine term cannot be represented within the available resolution and so becomes superfluous, thereby removing one lookup table and multiplication operation.

Pipeline clocked at fs W1 wavetable

− φI (n)

∑

∑

+

∏

W2 wavetable

∑

⎛ 2π ⎞ sin ⎜ M φ ( n) ⎟ 2 ⎝ ⎠

∑

⎛ 2π ⎞ cos ⎜ M φ ( n) ⎟ 2 ⎠ ⎝

∏

−

W3 wavetable ∏

φF (n)

+

∑ W4 wavetable

Figure 8.12 A pipelined optimal quadrature sinusoidal phase–amplitude mapping processor using trigonometric identity phase interpolation.

8.4 Interpolated vector memory

8.4

289

Interpolated vector memory In this section we present several interpolated phase–amplitude mapping processor architectures that utilise the vector wavetable memory introduced in Section 8.1.7. These processors are amenable to sample-level pipelining and example pipelined partitioning is shown. We begin with linear phase interpolation and progress to cubic phase interpolation. As already discussed, this vector memory architecture is unsuitable for interpolation orders where N þ 1 (i.e. the number of wavetable samples in the interpolation sample set) is non radix-2 (i.e. 2, 4, 6, etc.). Throughout the following discussions, for clarity we do not show the data multiplexing logic that is associated with filing each vector block memory from a host system.

8.4.1

Linear interpolation architecture Figure 8.13 illustrates the pipelined arithmetic processing model for a two sample vector memory and linear interpolation processor, assuming a fractional phase address (ϕI þ α) and wavetable page index p. Two 2-to-1 multiplexers, controlled by s0 and s1, re-order the memory block outputs into a contiguous sequence of ordered sample pairs {W[ϕ], W[ϕI þ 1]} which feed the first-order difference subtraction block. The firstorder difference is multiplied by the phase fraction α and then added to W[ϕI] to compute the phase interpolated sample y(n). Each processing stage is partitioned with a pipeline , and for the implementation shown we observe a seven sample pipeline latency. In an actual implementation, some process stages may be combined thereby reducing the pipeline latency. In an alternative architecture, one of the multiplexers may be omitted if the output adder is modified to accept a control input which reverses the sign of the input fed from the multiplier according to the sense of s0 or s1, as illustrated in Figure 8.14.

8.4.2

Cubic interpolation architecture We now consider a cubic phase interpolation processing architecture that requires a sample set of four wavetable samples to compute the waveform at a fractional phase address (ϕI þ α). The corresponding vector memory now comprises four distinct memory blocks B0, B1, B2 and B3, and generates the data-parallel sample set {W[ϕI], W[ϕI þ 1], W[ϕI þ 2], W[ϕI þ 3]} required for a cubic interpolation of the wavetable vector W. Samples are allocated to individual memory blocks from W in increments of four, as illustrated in Figure 8.15 for our simple L ¼ 8 example. Memory blocks B0, B1, B2 and B3 are written with data from W according to: B0 ½n ¼ W½4n, B1 ½n ¼ W½4n þ 1, B2 ½n ¼ W½4n þ 2, B3 ½n ¼ W½4n þ 3,

ð8:6Þ

Pipeline clocked at fs

s0

1

∑

φI (n)

⎢ x⎥ ⎢⎣ 2 ⎥⎦

B0 memory

W [φI ]

0 Mux 1

p(n)

W [φI + 1]

0 ⎢ x⎥ ⎢⎣ 2 ⎥⎦

∑

− ∑

+

Mux B1 memory

1

s1

α (n) Figure 8.13 Pipelined data-parallel linear phase interpolation processor using vector wavetable memory.

∏

y(n)

∑

φI (n)


s0

1

⎢x⎥ ⎢⎣ 2 ⎥ ⎦

B0 memory

0

W [φI ]

Mux

+ ∑

1

(− 1)s +1(W[φI

p(n)

0

+ 1] − W[φI ])

− ⎢x⎥ ⎢2⎥ ⎣ ⎦

y (n)

+ /− s0 = 0 / 1

∑ B1 memory

+

∏

α (n) Figure 8.14 An alternative form of the processing architecture presented in Figure 8.13 with reduced multiplexer count and pipeline latency.

292


W[φI ] 2P L L

L 0

1

2

3

4

5

6

p=0

7

0

1

2

3

4

5

6

7

0

1

5

6

7

p =1

First sample in sample set 0

4

0

4

L 4 1

2

3

5

6

7

1

2

3

5

6

7

p = 0 p =1

B0 [φ0 ] ⇒ 0

4

4

4

4

s0 0

3

2

1

0

B1[φ1 ] ⇒ 1 s1 1

1

5

5

5

0

3

2

1

B 2 [φ2 ] ⇒ 2

2

2

6

6

s2 2

1

0

3

2

B3 [φ3 ] ⇒ 3

3

3

3

7

s3 3

2

1

0

3

φI

0

1

2

3

4

0

1

2

3

0

φI

4

Figure 8.15 Logical and physical memory structures for a vector memory that produces four consecutive samples in parallel on each read operation.

where n 2 [0, (2P L/4) 1]. We also have four sample-position indices si 2 {0, 1, 2, 3} with i 2 [0, 3]. The phase index ϕI is transformed into four physical block addresses ϕi 2 [0, (L/4) 1] with i 2 [0, 3], which address memory blocks Bi modulo-L/4 generating the sample set {W[ϕI], W[ϕI þ 1], W[ϕI þ 2], W[ϕI þ 3]} for ϕI 2 [0, 2I 1]. It is evident that the block addresses are obtained through modular division by four which is effected with a simple arithmetic shift operation. The value of ϕ3 is obtained by taking the integer part of ϕI/4, modulo-L/4 (i.e. hbϕI/4ciL/4), with ϕ2, ϕ1 and ϕ0 obtained by offsetting ϕI by integer increments before the modular division operation. Assuming L is exactly divisible by four, the block addresses are given by:


ϕ0 ¼ ϕ1 ¼ ϕ2 ¼ ϕ3 ¼

ϕI þ 3 4 ϕI þ 2 4 ϕI þ 1 4 ϕI 4

293

L 4

L 4

L 4

L 4

, , ,

ð8:7Þ

:

For ϕI 2 [0, 2I 1], the sample-position indices take values that follow a cyclic permutation of the set {0, 1, 2, 3}. The sample-type indices are obtained by offsetting ϕI prior to the modulo-4 operation and then subtracting the result from three. The sample-position indices are therefore given by: p0 p1 p2 p3

¼ 3 hϕI þ 3i4 , ¼ 3 hϕI þ 2i4 , ¼ 3 hϕI þ 1i4 , ¼ 3 hϕI i4 :

ð8:8Þ

Figure 8.16 illustrates the pipelined arithmetic processing model for a four sample vector memory and cubic interpolation processor assuming a fractional phase address (ϕI þ α) and wavetable page index p. The ϕi and si are dependent on a modular division by four operation which is effected with two consecutive arithmetic right shift operations and hence computationally trivial. Furthermore, this holds for all radix-2 values of the vector length k requiring log2 (k) consecutive right shift operations.

8.4.3

Interpolated vector memory design considerations The preceding discussion indicates a distinct pattern in the attributes of an order-k vector memory which we now summarise. It is evident that the vector memory block addresses and sample-position indices are dependent on a division-by-k operation which is problematic for all non radix-2 vector lengths (and hence even-order phase interpolations). For all radix-2 vector length architectures, this operation is implemented with an appropriate bit-wise right shift. A memory space W of length 2P L samples which contains an integer number of contiguous wavetables (i.e. pages) each of length L samples contains 2P distinct wavetables. An order-k vector memory partitions W into k distinct memory blocks denoted Bi with i 2 [0, k 1], each of length L/k 2 Z samples. We have a fractional addressing representation comprising the phase component (ϕI þ α) and a wavetable index component p bound according to:

3 ∑

φI (n)

⎢ x⎥ ⎢⎣ 4 ⎥⎦

B0 memory

B0

p(n)

s0 B0 B1 B 2 Mux B3 s1

2

∑

⎢ x⎥ ⎢4⎥ ⎣ ⎦

B1 memory

B1

B0 B1 B 2 Mux B3 s2

1

∑

⎢ x⎥ ⎢4⎥ ⎣ ⎦

B2 memory

B2

B0 B1 B 2 Mux B3 s3

⎢ x⎥ ⎢⎣ 4 ⎥⎦

Sample position processing

α (n)

B3 memory

B3

s0 s1 s2 s3

B0 B1 B 2 Mux B3


β 0 W[φI ] ∏

β0 β 1 W [φI + 1] ∏

β1 ∑

β 2 W [φI + 2] ∏

β2

β 3 W[φI + 3] ∏

β3

Coefficient processing

∑

β0 β1 β2 β3

Figure 8.16 Pipelined data-parallel cubic phase interpolation processor using vector wavetable memory.

∑

y(n)


ϕI 2 ½0, L 1, α 2 ½0, 1Þ, p 2 ½0, 2P 1:

295

ð8:9Þ

In general, for an order-k vector memory, the contents of the ith vector memory block are given by: Bi ½n ¼ W½kn þ i,

ð8:10Þ

where n 2 [0, (2P L/k) 1] and i 2 [0, k 1]. The vector memory block addresses ϕi are given by: ϕI þ ðk i 1Þ ϕi ¼ L k

ð8:11Þ

k

and the sample-position indices si are given by: si ¼ ðk 1Þ hϕI þ ðk i 1Þik ,

ð8:12Þ

where ϕI 2 [0, L 1] and i 2 [0, k 1]. An order-k vector memory produces the sample set for an order-N ¼ (k 1) phase interpolation. The interpolation coefficients βi(α), are defined by Eq. (5.35) and assume the vector memory is indexed with an offset integer phase component hϕI ⌊ðN 1Þ=2⌋i2I to provide a minimum interpolation error bound. The fractional phase component ϕF determines the fractional phase value α ¼ ϕF/2F 2 [0, 1), and ultimately the interpolation coefficients through Eq. (5.35). Interpolation coefficients may be computed directly using ϕF (and hence α) as an argument, requiring O(N2) multiplications. However, this incurs a significant computational imposition in real-time applications, particularly when N is large. An alternative technique uses lookup tables indexed by ϕF to determine the βi(α) . We require k ¼ (N þ 1) β coefficient lookup tables, each tabulating a particular interpolation coefficient according to Eq. (5.35) and indexed by ϕF 2 [0, 2F 1], which outputs the β coefficient. Each β lookup table contains 2F coefficients and imposes a memory requirement of (N þ 1)2F words. The ith coefficient lookup table which we denote by Ci[a], is tabulated according to: 1 0 a N 1 j N B F þ Y C 2 B2 C, C i ½ a ¼ ð8:13Þ @ A i j j¼0 j 6¼ i

where a 2 [0, 2F 1]. Each interpolation coefficient lookup table is indexed by ϕF and produces the coefficient Ci[ϕF] ¼ βi(α). We can extend the utility of the β coefficient lookup table to effectively integrate the data re-ordering function and thereby obviate N re-ordering multiplexers. For radix-2 k values, the k-sample set of cyclic permutations is uniquely addressed by the log2(k) least significant bits of the phase index ϕI. We can organise each coefficient lookup table into k pages of interpolation coefficient values, with ϕF indexing the F least significant bits and hϕIik indexing the log2(k) most significant bits to select a particular page.

296


The ordering of the k interpolation coefficients within the paginated lookup table reflects the k sample-position permutations from the memory blocks. In general, for an order-k vector memory employing this technique, the total coefficient memory overhead is 2F k2 words and requires d log2(k)e extra address bits (e.g. 2 additional bits for the k ¼ 4 case) indexed by hϕIik. In a typical hardware implementation, the k-fold coefficient memory increase must be assessed relative to the cost of k k-to-1 multiplexers and the associated bus connectivity, as exemplified in Figure 8.17 for the cubic phase interpolation k ¼ 4 case.

8.4.4

A paged wavetable interpolation memory We now present a vector memory implementation of the paged wavetable interpolation algorithm introduced in Section 6.1.3. This processor computes the output sample according to Eq. (6.1) as the linear interpolation of two consecutive wavetables indexed by pP and pP þ 1 according to the fractional page address γ. (As with our earlier discussion, we have omitted the discrete-time index n for clarity.) Our wavetable page index is now interpreted as a fractional quantity that we denote by ( pP þ γ), where pP 2 [0, 2P 1] and γ 2 [0, 1). Figure 8.18 illustrates the pipelined signal flow of this interpolating vector memory. Two phase interpolating vector memory blocks, which can employ any phase interpolation method, store even and odd wavetables from the consecutive sequence and produce phase interpolated output samples according to the M-bit phase accumulator sequence ϕ(n), which is fed to both blocks. The order of the phase interpolation polynomial is not important for an understanding of paged wavetable interpolation, which is inherently linear. In effect, we now consider the two phase interpolating vector memories as ‘black boxes’ which compute wavetable samples according to page and fractional phase index arguments. After re-ordering into the correct order, these samples are subsequently interpolated (or, equivalently, linearly combined) according to the 0 fractional page index γ. The fractional page index is defined by γ ¼ p F 0 /2F and is simply a fixed-point fractional interpretation of pF 0. The sample re-ordering multiplexers are controlled from the least significant bit of the page index pP and its Boolean complement which we denote by pP(LSB) and /pP(LSB).

8.5

Waveform generation by direct computation In this section we investigate three approaches for directly computing waveforms from a frequency domain specification. We have seen that the IDFT enables us to transform from the frequency to the time domain according to harmonic amplitude and phase parameters. The first two techniques presented compute the IDFT as a phase–amplitude mapping algorithm for a DDS phase accumulating frequency synthesiser and build upon techniques first introduced by Chamberlin in [4] and [5] in connection with computer music synthesis. The fundamental frequency is set by the DDS phase increment and the harmonic frequencies are computed within the phase–amplitude mapping


3 ∑

φI (n)

⎢x⎥ ⎢4⎥ ⎣ ⎦

B0 memory

φI

p(n)

β 0 W[φI ]

B0 ∏ 4

C0 table

2

∑

⎢x⎥ ⎢⎣ 4 ⎥ ⎦

B1 memory

β 1 W [φI + 1]

B1

φI

∏ 4

C1 table

1

∑

⎢x⎥ ⎢4⎥ ⎣ ⎦

B2 memory

⎢ x⎥ ⎢⎣ 4 ⎥⎦

B3 memory

∏ 4

C2 table

β 3 W[φI + 3]

B3

φI

∑

β 2 W [φI + 2]

B2

φI

∑

∑

∏ 4

C3 table

φF (n) Figure 8.17 An order-4 vector memory and phase interpolation processor using augmented coefficient lookup tables to eliminate the data re-ordering multiplexers.

y(n)

W0 W2 W4 W6 Pipeline clocked at fs pP ( LSB) ( n)

φ (n)

M

φ (n)

⎢ x⎥ ⎢⎣ 2 ⎥ ⎦

1

pP (n)

Even page vector memory and interpolator

0 Mux 1

∑ Wavetable page index

pP (n)

P

⎢ x⎥ ⎢⎣ 2 ⎥⎦

pP (n)

∑

0

φ (n) Odd page vector memory and interpolator

∑

− +

∏

Mux 1

/ pP ( LSB) ( n)

Wavetable page index W1 W3 W5 W7

γ (n)

F′

Figure 8.18 A schematic processor which computes a linear interpolation between two consecutive wavetables according to a fractional page address that we denote by ðpP þ γÞ.

y(n)

8.5 Waveform generation by direct computation

299

algorithm. This type of waveform synthesiser does, however, require many parameters to specify the waveform – amplitude and phase for each harmonic in addition to a fundamental frequency parameter. The principal advantages of IDFT phase–amplitude mapping may be summarised thus:

real-time control of individual harmonic amplitude and phase; non-consecutive harmonic sequences; independent control of fundamental frequency fo with all DDS attributes; harmonic SNR and SFDR of the output waveform are independent of harmonic number (unlike the pre-computed wavetable approach whose SNR reduces with harmonic number); a ‘pipeline-friendly’ signal flow. The principal disadvantage is computational complexity, since all component sinusoids must be computed, weighted and summed in every sample period. However, the nature of the IDFT algorithm allows it to be readily partitioned for pipelined execution. The control parameter problem must also be considered when applying this technique since this invariably incurs some level of metaparameter processing as outlined in Chapter 7. The third technique, which we call band- spectrum waveform synthesis, is effectively a time-division multiplexed sinusoidal DDS that generates multiple, phasecoherent sinusoids with independently programmable frequency and phase offset. These sinusoids are amplitude weighted and summed to produce a typically aperiodic composite waveform that has a band- spectrum. As this waveform synthesiser is not constrained to harmonic frequencies, it is strictly not correct to call it an implementation of the IDFT, which is only defined for exactly harmonic basis frequencies. However, because of its similarity to the IDFT we include it here (i.e. the summation of weighted amplitude sinusoids). Non-harmonic, band- spectra are generally manifest as aperiodic waveforms in the time domain, whose period is the lowest common multiple of the constituent sinusoid periods.

8.5.1

A contiguous harmonic IDFT waveform synthesiser The simplest waveform synthesiser uses the harmonic phase indexing introduced in Chapter 7 to generate an amplitude and phase weighted summation of contiguous harmonic sinusoids (i.e. fo, 2fo, 3fo, . . ., Nh fo). The processor partitions the sample period into Nh equal duration ‘time slots’ in which individual harmonics are generated and processed. Accordingly, there is a time slot address (TSA) which controls the sequential processing and indexing of parameters. The TSA is generated by a dlog2 Nhe counter clocked at Nhfs. We assume that Nh is radix-2 for simplicity, although this is not mandatory. The processing architecture illustrated in Figure 8.19 combines sample pipelining with block level pipelining. The generic phase–amplitude mapping block may take any form, from simple phase truncated wavetable indexing to a phase interpolated solution for maximum SNR and SFDR performance. If a particular harmonic is not required its amplitude is set to zero to remove it from the

θk

Ak

Harmonic phase offset DPM

TSA

fs 2

TSA

fs 2

⎛ 2π ⎞ ≈ A1 cos ⎜ M (φ ( n) + θ1 )⎟ ⎝2 ⎠

Harmonic amplitude DPM

Preload 2

φ (n) =1

M

ϕ

∑

Nh fs

z-1

z-1

Preload 1

fs

M

Nh fs

=1

z-1

Mux

∏

Nh fs z-1

M

∑

cos(φ k (n))

Mux

y (n)

∑ Preload 2

∑

M

φ k ( n) = k φ ( n) M

2M

⎛ 2π ⎞ ≈ Ak cos ⎜ M (kφ ( n) + θ k )⎟ ⎝2 ⎠

Figure 8.19 An implementation of the contiguous harmonic IDFT as a DDS phase–amplitude mapping processor based on that introduced by

Chamberlin [5]. The TSA controls the indexing of harmonic amplitude and phase parameters from the DPM blocks.

301

8.5 Waveform generation by direct computation

fs

T Nh Nh fs

Preload 1 Σ phase accumulator

φ (n)

z −1phase accumulator

φ (n − 1)

φk (n) = kφ (n)

2M

N hφ (n − 1)

φ (n)

φ (n)

2φ (n)

3φ (n)

k =1

k=2

k =3

N hφ (n) k = Nh

Preload 2 cos(φk (n) ) cos(φ ( n) + θ1 )

cos(2φ (n) + θ 2 )

z −1amplitude accumulator h ⎛ 2π ⎞ y (n − 1) ≈ ∑ Ak cos⎜ M (kφ (n − 1) + θ k )⎟ ⎝2 ⎠ k =1

N

y (n)

A1 cos(φ (n) + θ1 )

y ( n − 1)

Figure 8.20 Arithmetic timing diagram for the contiguous harmonic IDFT processor illustrated in Figure 8.19.

Fourier summation. However, a processing slot is now wasted since the sinusoid still has to be computed and multiplied by zero. Sample level pipelining is applied to the phase accumulator output and final amplitude sample. Block level pipelining allows transparent updating of harmonic parameters from a host control system where two ‘ping-pong’ dual-port memories (DPM) store the harmonic amplitude and phase parameters. The DPM ping-pong rate is fs/2 and incurs a pipeline latency of one sample period. The parameter DPMs can be memory mapped into a host processor’s memory space and allow transparent updating of harmonic amplitude and phase in real time with a latency of only one sample period. The DPMs are indexed by the TSA, which completes a full cycle every sample period. Each TSA value corresponds to a distinct harmonic in a contiguous sequence. If we denote the TSA value by Ts, the effective harmonic multiplier k is simply Ts þ 1. When Ts ¼ 0 the fundamental phase (i.e. first harmonic) is pre-loaded into the harmonic multiplying accumulator by assertion of the Preload 1 signal. Ts counts continuously from 0 to Nh 1, where Nh is the total number of harmonics in the IDFT computation. The multiplexed harmonic phase sequence is first offset by the corresponding parameter in the phase offset DPM and then phase–amplitude mapped. The harmonic amplitude

302


sample is then multiplied by the corresponding parameter in the harmonic amplitude DPM and placed in the amplitude accumulator where it is added to the running sum. At the beginning of the harmonic accumulation cycle, the output , clocked by Nhfs, is enabled by the Preload 2 control signal to transfer the accumulator sum which contains the y(n) harmonic waveform sample. Simultaneously, at the end of the fundamental (first harmonic) phase–amplitude mapping computation, the accumulator is preloaded with the amplitude-weighted sample value by the Preload 2 signal ahead of the next harmonic accumulation cycle. Subsequent harmonic computation cycles at the Nhfs rate are accumulated in the accumulator. This cycle repeats continuously, outputting a sequence of harmonic waveform samples y(n). Figure 8.20 shows a schematic timing diagram for the IDFT harmonic indexing and amplitude accumulation computations. This diagram is not intended to provide a detailed description of the processor timing, which will be specific to the chosen ‘target technology’ (e.g. FPGA) and exact design approach. Instead, it serves to demonstrate the logical flow of arithmetic events that will detailed logic design, which is beyond the scope of this book.

8.5.2

An arbitrary harmonic IDFT waveform synthesiser Figure 8.21 illustrates a modified processing architecture that computes the IDFT according to an arbitrary, -defined sequence of harmonics. The harmonic frequency is specified as an integer multiple of the fundamental frequency and is now an explicitly supplied parameter kj. The harmonic accumulator is replaced with an integer multiplier block that multiplies the phase accumulator output sequence ϕ(n) by the harmonic multiplier kj, modulo 2M. Given that we are always imposing integer multiples of ϕ(n) modulo 2M, implementation of the multiplier can be simplified as described in Section 7.3.2. Figure 8.22 illustrates a pipelined integer multiplier that multiplies an M-bit ϕ(n) by an 8-bit integer kj modulo 2M. Harmonic multiples anywhere on the interval [1, 255] can be imposed with this particular multiplier architecture. We see that this architecture is readily pipelined with s partitioning the time consuming addition stages. The modulo 2M left-shift operations may be hardwired and incur no processing overhead. Control timing and arithmetic flow of this waveform synthesiser are otherwise identical to the contiguous harmonic form described earlier.

8.5.3

A band- spectrum waveform synthesiser Figure 8.23 illustrates a band- spectrum waveform synthesiser that sums Ns independent amplitude and phase offset weighted sinusoids (where Ns is analogous to Nh in the IDFT case). As with the harmonic IDFT case, each sinusoidal component is computed, amplitude weighted, and accumulated sample by sample at the sample rate fs. In effect, this architecture is a TDM implementation of Ns sinusoidal DDS generators, each with a distinct phase offset and amplitude parameter. In this context, the ability to apply a phase offset to each sinusoid of the band- spectrum has only specific utility, which comprises the following cases:

θj

kj

Harmonic multiplier DPM

TSA

fs 2

Aj

Harmonic phase offset DPM

TSA

fs 2

TSA

fs 2

⎛ 2π ⎞ ≈ A1cos ⎜ M (k1φ ( n) + θ 1 )⎟ ⎝2 ⎠

Harmonic amplitude DPM

Preload 2

M

φ j ( n ) = k j φ ( n) kj

ϕ

fs

M ∑

z

-1

M

φ (n) M

∏

M

Aj 2M

θj

=1

∏ ∑

cos(φ j (n))

Mux

Nh fs

Nh fs

z-1

z-1

y(n)

∑ Preload 2

⎞ ⎛ 2π ≈ Aj cos ⎜ M (k j φ ( n) + θ j )⎟ ⎝2 ⎠

Figure 8.21 An implementation of the arbitrary harmonic IDFT as a DDS phase–amplitude mapping processor. A new parameter kj explicitly specifies the harmonic number (or harmonic multiplier relative to the fundamental). The TSA controls the indexing of harmonic multiplier, amplitude and phase parameters from the DPM blocks.

304


Figure 8.22 A pipelined integer phase multiplier which computes the kj multiple of a phase sequence ϕ(n) modulo 2M.

if the (non-harmonic) component phase must be specified relative to a start event (e.g. phase accumulator initialisation when n ¼ 0); if we wish to apply dynamic phase modulation to a specific component; of course, if we are synthesising an exact harmonic series with this architecture.

8.6

Summary In this section we have presented several hardware-oriented processor architectures that apply the techniques described in this book. They are intended to serve as the basis of bespoke implementations in -defined target technologies (e.g. FPGA or ASIC). It is also intended that these example designs will spawn further development and innovation. We have discussed throughput enhancing techniques, such as arithmetic pipelining, time division multiplexing and parallel vector memory, that enable

θ j (n)

TSA

fs 2

Aj (n)

TSA

Phase offset DPM

fs 2

Sine amplitude DPM Preload 2

=1

TSA fs 2

TSA fs 2 TSA fs 2

ϕ j (n)

Phase increment DPM

∑

State variable DPM

∑

Phase DPM

cos (φ j ( n))

∏

Mux

Ns fs

Ns fs

z-1

z-1

y (n)

∑ Preload 2

Figure 8.23 An implementation of a band- spectrum waveform synthesiser that computes Ns amplitude weighted sinusoids with independently controlled frequency by time division multiplexed DDS. The weighted sinusoids are summed into a composite waveform y(n) sample by sample at the rate Ns fs.

306


execution of the underlying algorithms at high sample frequency. This, in turn, increases waveform synthesis bandwidth. The concept of partitioned phase accumulation (or segmented phase accumulation as used by Goldberg in [2]) has also been discussed. This innovative idea, motivated by the properties of summed phase sequences, allows very high speed phase accumulators to be constructed with a significantly reduced amount of high speed logic. This approach is particularly useful in power and thermally constrained systems, or where high speed logic resources are scarce. The amalgamation of DDS and the IDFT allows waveform synthesis from a harmonic (i.e. frequency domain) specification in real time. Furthermore, the fundamental frequency may be programmed with all of the attributes of conventional sinusoidal DDS. Where real-time waveform synthesis using a frequency domain specification is an important requirement, this synthesis technique offers optimal flexibility. The fundamental frequency, harmonic number, amplitude and phase can be independently controlled in real time.

8.7

References 1. P. Pirsch, Architectures for Digital Signal Processing, John Wiley & Sons, 1998. 2. Bar-Giora Goldberg, Digital Frequency Synthesis Demystified – DDS and Fractional-N PLLs, LLH Technology Publishing, 1999. 3. J. Vankka, ‘Methods of mapping from phase to sine amplitude in direct digital synthesis’, IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, 44, No. 2, pp. 526–534, March 1997. 4. H. A. Chamberlin, ‘Experimental Fourier series tone generator’, Journal of the Audio Engineering Society, 24, No. 4, May 1976. 5. H. A. Chamberlin, Musical Applications of Microprocessors (2nd edition), Hayden Books, 1987.

9


In this chapter we discuss conversion of discrete-time digital signals to the continuoustime or analogue domain. So far we have only investigated generation of digitally represented signals that are sampled in time and quantised in amplitude to a specific number of bits b. Accordingly, in an ideal convertor there are 2b equally spaced quantisation levels that follow an exact linear relationship with the input code. We call this process digital to analogue conversion, and it comprises several distinct sequentially connected processing functions that we consider in this chapter:

the digital to analogue convertor (DAC); a glitch reduction stage, or ‘deglitcher’ (if required); a typically low- reconstruction filter; analogue post-processing (e.g. switched attenuation, DC offset control and output line driving).

Fundamentally, a DAC takes a b-bit digital input word and together with a reference voltage (or current) Vref computes a corresponding output voltage Vout or current iout, depending on its architecture. In effect, a DAC multiplies the reference voltage by a factor determined from the input word as a fraction of full-scale. Accordingly, the often overlooked DAC reference is a critical design consideration and for our present discussion we subsume it into the DAC function. There are many DAC architectures reported in the literature and available in ‘single chip form’ from commercial suppliers such as Analog Devices, Linear Technology and Texas Instruments. The so-called ‘R-2R DAC’ is one of the most common DAC structures and, as its name suggests, uses a resistor network comprising only two values with a resistance ratio of exactly 2:1. A b-bit DAC requires 2b resistors which are easily trimmed to the exact 2:1 ratio during manufacture using modern IC fabrication processes. There are also b analogue switches that route the ‘inputs’ of the R-2R network according to operating mode. R-2R DACs may be operated in voltage mode or current mode although the internal DAC structure is actually identical in both cases. Figure 9.1 illustrates both operating modes for a simple 3-bit R-2R DAC. In voltage mode, output switching transients (or glitches) are reduced, although the reference input impedance varies with input code, complicating the voltage reference design. However, the analogue switch design is complicated from an IC manufacture viewpoint due to the wide voltage swing seen by the switch elements. In current mode, the reference voltage input impedance is a constant impedance and the analogue

308


Voltage mode

R

R

2R

2R

Vout

R

2R

2R

2R

LSB

MSB

Vref

Current mode

Vref

R 2R

R 2R

R 2R

MSB

2R

2R

LSB

iout

Figure 9.1 Voltage and current mode R-2R DAC topologies.

switches only switch currents to ground or into the output amplifier virtual earth. This greatly simplifies their design and fabrication. Output switching transients are generally higher, however. The current mode R-2R DAC is a popular choice for the so-called multiplying DAC or MDAC where the reference voltage may be an AC signal. A development of the R-2R concept is the current-switching DAC which combines the R-2R network with binary-weighted current sources that are switched into the output port according to the binary input word using analogue switches. Another widely utilised DAC architecture is the segmented DAC, where two or more low resolution DACs are combined in some way to form a higher resolution DAC. The basic principle is that one DAC handles the MSBs and the other the LSBs of the input word. How the DAC outputs are combined depends on the exact segmented architecture, of which there are many reported. Kester [1] provides an illuminating summary of the segmented DAC technique and its history. The oversampling interpolating DAC architecture enables considerable simplification of the post-DAC reconstruction filter. In effect, some of the analogue reconstruction


309

filtering is moved to a digital interpolation filter applied before the DAC. The interpolation filter is clocked at the oversampling frequency, which is an integer multiple k of the input sample frequency. An important benefit of oversampling is to relax the roll-off requirements of the post DAC analogue reconstruction filter. However, we also observe an improvement in quantisation noise performance when oversampling. In the oversampled case, the quantisation noise is spread over a wider bandwidth with respect to the original (critically sampled) Nyquist bandwidth. For k ¼ 2 an improvement of 3 dB is observed in the SNR due to quantisation noise. This figure improves by a further 3 dB for each doubling of k. The input to the digital interpolation filter is b-bits, although the output can be usefully represented to more than b-bits. The ‘bit growth’ is a function of the oversampling ratio k. The oversampling DAC concept underpins an important development in DAC architecture – the sigma–delta (ΣΔ) DAC. The simplest architecture comprises an interpolation filter, followed by a digital ΣΔ modulator that can be thought of as applying a low- filtering operation to the signal and a high- filtering operation to the quantisation noise. The output of the ΣΔ modulator is a 1-bit stream that feeds a 1-bit DAC whose output switches between bipolar reference voltages. The 1-bit DAC output feeds an analogue reconstruction filter whose roll-off slope specification is relaxed considerably compared to the critically sampled case. The second, so-called ‘multi-bit’ ΣΔ DAC architecture is very similar to the 1-bit form just described, except that now the digital ΣΔ modulator produces m bits instead of one. Accordingly, the DAC must now be m-bits wide, although its linearity must be comparable with b-bits. This architecture is similar to the oversampling interpolating DAC with the addition of a digital ΣΔ modulator. Single and multi-bit ΣΔ DACs are the current state-of-the-art in low bandwidth, high resolution, low distortion applications such as digital audio. The DAC input digital word is characterised by essentially three parameters – the number of bits b, the logic level format (e.g. TTL, CMOS or ECL, etc.) and the coding format (e.g. sign-magnitude or 2’s complement). The number of DAC bits sets the dynamic range and quantisation uncertainty of the convertor and is a fundamental system design parameter. The logic level format defines the logic voltage levels that represent a logic 1 or 0. The coding format is principally about the unambiguous representation of bipolar digital signals. Historically, several formats have been used and their evolution is discussed in [1]. Many modern DACs use offset binary coding to represent bipolar signals. If we assume a 4-bit example DAC, the zero value is represented by 1000. The most negative value (– full-scale þ 1 least significant bit (LSB)) is represented by the code 0001 and the most positive value (þ full-scale – 1 LSB) by 1111. In order to maintain mid-scale symmetry, the input code 0000 is not used. In general, fixed-point computer and DSP arithmetic uses 2’s complement data coding since negative numbers are easily represented and the subtraction operation is trivial. Another benefit of 2’s complement coding is the unambiguous representation of zero, unlike some coding schemes (e.g. sign-magnitude which allows for a ‘ zero’ representation). 2’s complement coding comprises a straight binary code for positive numbers (sign bit set to 0) and the 2’s complement of a positive number to represent its negative value (sign bit


+FS 3/8 1/4

Analogue output

310

1/8 0 -1/8 -1/4 -3/8 -FS 000 001 010 011 100 101 110 111 Offset binary input word

Figure 9.2 An ideal bipolar DAC transfer function. In this example, the 3-bit DAC quantises the possible analogue outputs into eight equally spaced levels.

set to 1). The 2’s complement is computed by first 1’s complementing the number (i.e. inverting all of the bits) and then adding 1 to the LSB. We observe that 2’s complement coding is identical to offset binary coding except that the most significant bit (MSB) is inverted. Figure 9.2 illustrates an ideal 3-bit bipolar DAC transfer function based upon offset binary input coding. It is clear that the output voltage is quantised to eight levels and the transfer function graph contains eight points. It is essential that we the DAC transfer function is not a continuous line, but a collection of discrete points. Similarly, as we discuss later, the curve that es through these points is not straight and exhibits a variety of deviation behaviours in ‘real-world’ DACs. All DACs have several distinct error mechanisms that cause the transfer function to deviate from an ideal linear response. Outside of intrinsic DAC non-linearities, nonlinear behaviour can also be caused by specific and often subtle circuit characteristics (e.g. digital–analogue crosstalk and capacitor voltage dependence in the reconstruction filter). In dynamic (e.g. waveform generation) applications, non-linearity causes signal distortion that is manifest as error spurs in the amplitude spectrum and hence a reduction in spurious-free dynamic range (SFDR). All DACs produce some degree of transient disturbance or ‘glitch’ in the output signal following a change in the digital input word. Glitch reduction or ‘deglitching’ refers to the systematic removal of these transients using active switching circuitry after the DAC. The magnitude of the glitch transient is measured by the glitch impulse area1 1

In some literature the term glitch energy is used to quantify the area under the glitch. However, this is incorrect since the unit of measurement is not equivalent to energy.

9.1 Error mechanisms

311

metric in units of volts-time. There are essentially only two methods for reducing DAC glitch errors – use a DAC architecture that has inherently low glitch impulse area (e.g. a so-called segmented architecture DAC), or use a track-and-hold amplifier after the DAC to ‘gate out’ the glitch using a suitably timed track/hold control signal relative to the DAC input word. In some applications it may be prudent to apply both techniques. The reconstruction filter converts the ‘staircase’ or zero-order hold DAC output voltage into a smooth continuous-time signal. The reconstruction filter also serves to band-limit the output spectrum, eliminating alias images above the Nyquist frequency. Accordingly, the reconstruction filter must suppress alias images to a specified level by the stop band frequency. Typically, this level is a system design consideration and may be less than the in-band quantisation noise level or SFDR. The cut-off frequency is therefore typically less than the Nyquist frequency by some margin. Figure 9.3 illustrates a generic low- reconstruction filter response and defines the key specification parameters – -band ripple, cut-off frequency, transition bandwidth, stop-band frequency and stop-band suppression. For comparison, we also show an ideal low reconstruction filter response. There is an additional parameter, the filter phase response which describes how the phase shift through the filter changes with frequency through the -band and stopband. In a waveform generator context, the reconstruction filter phase response is an important consideration in preserving waveshape with frequency (particularly with pulse-like waveforms). Typically, a linear phase response equivalent to a constant group delay is desirable. Finally, we have the analogue post-processing that follows the DAC and reconstruction filter. Typically, this comprises switched attenuation to provide precise control of output amplitude, DC offset imposition and output line driving. In some specialised applications, high power amplification may be required to provide a large voltage swing into a low impedance load, possibly requiring a high current drive. All of these ‘analogue’ functions become increasingly challenging to design as bandwidth and dynamic range requirements increase. We therefore outline some of the design considerations for these functions. In Section 9.1 we review the principle static and dynamic DAC error mechanisms. Since a waveform generator typically has to operate from DC to near the Nyquist frequency, all of these error mechanisms are important. In Section 9.2 we review the key dynamic specifications of a DAC for use in a digital waveform generator application. In Section 9.3 we discuss the design of the reconstruction filter and consider some real-world mechanisms that contribute to reduced performance. In Section 9.4 we review several specific analogue design considerations that are necessary within a complete digital waveform generator.

9.1

Error mechanisms In this section we discuss the principal static and dynamic DAC error mechanisms. These errors affect both the DC (or low frequency) performance and the dynamic performance. DC errors generally affect waveform offset (or mean) voltage and output

312


Figure 9.3 A generic low- filter response showing qualitative performance attributes. The ideal low- reconstruction filter response is also shown.

amplitude stability over time and temperature. By themselves, DC errors do not affect the distortion or spectral purity of the waveform. However, in some applications, a signal with precisely adjustable amplitude and a stable DC offset voltage is a key requirement. In a digital waveform generator, the DC offset and amplitude control stability are determined entirely by the DAC and its analogue post-processing stages. Dynamic error mechanisms and their mitigation are critical design considerations in all digital waveform generation applications. These errors are particularly important


313

in those applications requiring very low distortion, or equivalently, high spectral purity in the synthesised signal, for example, high performance single or multi-tone sine wave generation for audio testing. The design challenge grows with increasing bandwidth and dynamic range. Although we may deliberately add controlled amounts of distortion or other signal anomalies to an ideal waveform using DDS arbitrary waveform techniques, it is important to that these assume an ideal (i.e. distortion-free) DAC stage. In sinusoidal or arbitrary waveform DDS systems, the DAC dynamic performance should always aim to exceed the worst case SFDR due to phase truncation effects in the phase–amplitude mapping (including any phase interpolation mitigation measures). However, this cannot always be achieved and the DAC is the limiting factor on overall system performance.

9.1.1

Offset error The ideal transfer function of a bipolar DAC is a straight line that es through the two full-scale end points. If we assume an offset binary coding and a hypothetical b-bit DAC, these two voltages may be denoted by V0 (all zeros input) and V1 (all ones input), corresponding to – full-scale and þ full-scale – 1 LSB, respectively. Figure 9.4a illustrates DAC offset error that we denote by Vos, and which is defined as a vertical translation of the straight line that es through the two full-scale end points. The preceding discussion outlines the definition of the static offset error which assumes a constant temperature and no variation over time (e.g. ageing). Static errors can be trimmed out during system test or removed by an auto-calibration methodology applied to the system as a whole. Static offset error is corrected by adding a compensating voltage somewhere in the post-DAC analogue processing. However, DAC offset errors always have an associated temperature coefficient that must be compensated for or specified to be acceptably small against requirements. All reputable DAC manufacturers specify both static and dynamic offset and gain errors. We should that DDS systems may easily generate signals down to near-DC and it is quite feasible in specialised applications that the lowest frequency of operation becomes comparable with quasi-cyclic temperature related drift (e.g. diurnal effects). In effect, the temperature coefficient of DAC offset can cause waveform distortion at very low frequencies. Of course, this concern applies to the whole analogue processing chain when precision DC performance is required. In addition to temperature related offset drift, we should also that such parameters, whether in DACs or op-amps, exhibit age-related drift phenomena that should be considered as part of a rigorous design. If the variation in offset error is a concern, irrespective of its cause, consideration should be given to periodic auto-calibration against a precision reference. Essentially, this involves ‘measuring’ the DAC output voltage using a precision ADC over several values of input code word including zero. It is then possible to calculate a ‘best fit’ correction factor that is applied to null the DAC offset error. Such techniques are widely applied in the test and measurement industry to maximise performance and extend calibration intervals.

314


Figure 9.4 An illustration of DAC static error mechanisms: (a) Offset error; (b) Gain error.


9.1.2

315

Gain error Figure 9.4b illustrates DAC gain error which is defined as a change in the slope of the straight line that es through the two full-scale end points. Assuming zero offset error, the ideal mid-code value should be exactly zero and any gain error will be manifest as a bipolar zero error as shown. However, real-world DACs exhibit both gain and offset errors as also illustrated in Figure 9.4b. These errors are manifest as a change in the slope and translation of the ideal DAC transfer function, respectively. DAC gain errors also vary with temperature and age. As with offset error, gain errors are an important design consideration in precision waveform generators, where gain error is manifest as an error in the amplitude of the synthesised waveform. However, just as with offset errors, it is possible to ‘null out’ gain errors using auto-calibration methods. Small static gain errors may be trimmed during test by adjusting the DAC reference voltage accordingly. To compensate for temperature and age-related gain drift, consideration should be given to the use of an ‘amplitude levelling loop’ as outlined in Chapter 1 for the amplitude stabilisation of specific types of analogue oscillator (e.g. the Wien bridge oscillator).

9.1.3

Settling time DAC settling time is defined as the time for the output to settle to within a specified error band relative to the 50% point of the input data strobe or the time at which the input data change. The error band is typically defined as either 1 LSB or a percentage of full-scale. For high resolution DACs (greater than 12-bits) the error band is usually defined as a percentage of full-scale since measurement relative to the LSB becomes increasingly difficult. An alternative definition takes the start reference point as the time when the output leaves the initial error band. Figure 9.5a illustrates the key phases and definition of DAC settling time. There are four distinct phases to settling time – dead time, slew time, recovery time and linear settling time [1]. These begin when the DAC output starts to change and end when the output has settled to within some error band around the new value. If the slew time is short compared to the recovery and linear settling time, the overall settling time is independent of the output step size. However, if this is not the case, settling time is dependent on step size. Generally, current-output DACs do not exhibit settling time dependence with output step size. Settling time is an important design parameter in waveform generation DACs. Its specification must consider the maximum voltage (or current) step size between adjacent samples, which is fundamentally determined by the synthesis bandwidth. By definition, this step must settle to well within one LSB of the new value in less than one sample period. The synthesis bandwidth is effectively the highest frequency harmonic in the synthesised waveform.

316


Figure 9.5 An illustration of DAC dynamic errors: (a) Settling time; (b) Output transition glitch.


9.1.4

317

Transition or ‘glitch’ errors The output of an ideal DAC should change monotonically with any change in input word. Real-world DACs exhibit fast transients or glitches coincident with a change in the input word as illustrated in Figure 9.5b. Essentially, glitches are caused by one of two mechanisms. Either capacitive coupling between the DAC digital inputs and the analogue output or, more typically, a timing mismatch between the internal DAC current steering switches. The latter mechanism leads to momentary spurious outputs until the switches settle to the correct state and causes the glitch magnitude to be codedependent. Glitches are characterised by the ‘glitch impulse area’ which is defined as the total area under the glitch transient curve measured in units of volts-time (typically pVs). The glitch impulse area for low distortion DACs as required in waveform generation applications, is usually less than 30 pVs [2]. The glitch impulse area is generally a strong function of the number of bits changing in the DAC input word and reaches a maximum when the MSB undergoes a major transition (e.g. from 0111 to 1000 in a 4-bit DAC). The glitch impulse area is therefore very data dependent and causes harmonic distortion and associated alias error spurs in the amplitude spectrum. For example, the MSB major transition glitch always occurs twice in a sinusoidal cycle (at the zero-crossing points) and therefore produces a strong second harmonic (or its alias image) leading to a reduction in SFDR. In general, code-dependent glitches cause both in-band (i.e. within the Nyquist interval) and out-of-band harmonics when the DAC is reconstructing DDS generated sinusoidal or arbitrary waveforms. Clearly, out-of-band harmonics appear as alias images in the Nyquist interval and are not removed by the reconstruction filter.

9.1.5

Linearity errors There are principally two DAC linearity error mechanisms that are of concern in waveform generation applications – integral non-linearity (INL), or relative accuracy, and differential non-linearity (DNL). Integral non-linearity is defined as the maximum deviation of the DAC output voltage from the ideal value at any point on its transfer function. The ideal transfer function is represented by the straight line that es through the full-scale end points. Differential non-linearity is defined as the maximum deviation of the DAC output voltage (or current) from the ideal 1 LSB value for a unit increment in input code. The 1 LSB value is chosen by taking of the overall DAC gain. If the DNL is more negative than -1 LSB, the DAC transfer function is nonmonotonic (i.e. exhibits a change in slope). Figure 9.6 illustrates a hypothetical nonideal 3-bit DAC which serves to exemplify INL and DNL definition as presented in [1]. In waveform generation applications, the absolute INL and DNL specifications only give an indication of DAC dynamic performance in a manner analogous to the nonlinearity of an amplifier. By themselves they cannot accurately predict the levels of harmonic distortion or SFDR, which are measured and specified in the frequency domain.

318


+FS

Analogue output

Non-monotonic transition

Ideal DAC transfer function

-FS 000 001 010 011 100 101 110 111 Offset binary input word Figure 9.6 A simple illustration of DAC linearity error.

9.1.6

DAC quantisation noise In DDS waveform generator applications, even an ideal DAC will produce harmonics whose amplitude is highly dependent on the ratio of synthesised output frequency to sample frequency (i.e. fo/fs). The spectral distribution of the DAC p quantisation ffiffiffiffiffi noise varies with this ratio although the RMS amplitude is equal to q= 12, where q is the weight of the LSB. From an SFDR perspective, it is therefore not always correct to assume that the DAC quantisation noise is uniformly spread across the Nyquist bandwidth in DDS systems [2]. If the synthesised frequency is set to an exact submultiple of the sample frequency (i.e. fo/fs is a rational fraction), the quantisation noise spurs are clustered at harmonic multiples of the synthesised frequency. This, in turn, leads to a degraded SFDR figure for these specific conditions. However, if the synthesised frequency is offset slightly from the sub-multiple value, the quantisation noise becomes more randomised. Under these conditions SFDR improves significantly. Unfortunately, in many instrumentation applications, the synthesised frequency can take on any value relative to the sampling frequency and this must be taken into when determining worst case SFDR performance. In Chapter 4 we introduced the concept of phase dithering to reduce DDS phase truncation error spurs and thereby improve SFDR. We may also apply dithering in the ‘amplitude domain’ to reduce corresponding DAC quantisation error spurs and hence improve SFDR at the expense of elevating the noise floor. A pseudo-random white noise sequence with a q/2 RMS amplitude is added to the DAC input word. The strong correlation between SFDR and the fo/fs ratio is now broken at the expense of a small elevation in noise power across the Nyquist bandwidth.

9.2 DAC dynamic specification considerations

9.2

319

DAC dynamic specification considerations In this section we review dynamic DAC specifications that are particularly important in digital waveform generation applications. Here we are concerned with the frequency domain (i.e. amplitude spectrum) effects of non-linear distortion mechanisms such as code-dependent glitches, integral non-linearity and differential non-linearity. Despite these non-linearity mechanisms being well specified in most commercially available DACs, it is difficult to predict their effects on harmonic distortion or SFDR using purely analytical techniques. In selecting a DAC for a specific waveform generation application, we therefore characterise a candidate DAC’s performance empirically from its output spectrum under specific test conditions. It is instructive to include the post-DAC analogue processing in these measurements although it is important to also test the DAC in isolation. Fortunately, today there are many manufacturers of high-performance DACs (and other data conversion devices) whose products are both designed and specified for DDS waveform generation applications (e.g. Analog Devices, Linear Technology, Texas Instruments and Maxim Integrated). All DAC test scenarios require that we synthesise discrete-time input test signals and then measure the DAC output on a spectrum analyser and interpret the results. From this spectrum we can easily determine established metrics such as harmonic and intermodulation distortion and SFDR under application-specific test conditions. However, an important question arises – how do we generate digital test signals? They are discretetime (by definition) and of arbitrary waveshape or spectrum depending on the purpose of the test (e.g. a single or multi-tone sine wave). As we have seen in earlier chapters, it is possible to implement ideal DDS phase–amplitude mapping if the phase-accumulator word size M is sufficiently small. This approach may be used to generate ideal discretetime sinusoidal (or other waveshape) test signals and the reduced frequency control resolution is usually tolerable. Alternatively, commercially available programmable digital word generators may be used to provide the DAC test word sequence (e.g. the Tektronix DG2020A). We now review the most important frequency domain metrics applicable to a waveform generation DAC. These metrics are the ones most commonly used by commercial manufacturers to characterise a DAC for wideband DDS applications.

9.2.1

Harmonic and intermodulation distortion Figure 9.7a illustrates a hypothetical DAC harmonic distortion spectrum that would be observed on a spectrum analyser. The spectrum only covers the Nyquist bandwidth and shows a typical harmonic distortion spectrum where no harmonics have aliased. We arrange for a sinusoidal test signal with a specific amplitude relative to full-scale and frequency low enough that the harmonics of interest (e.g. up to the 10th) are all below the Nyquist frequency. Typically, the test signal level is chosen to be near full-scale, but sufficiently offset to prevent clipping. However, to obtain an accurate distortion figure it is critical that the fundamental frequency of the test signal is not an


(a)

DAC output level (dB)

Full-scale (FS) Signal (carrier)

f

SFDR (dBFS) SFDR (dBc) Peak spur level

f1

f2

f3

f4

Noise floor

f5

Frequency

(b) Full-scale (FS)

DAC output level (dB)

320

f1

f2

SFDR (dBFS)

f1 − f 2

f1 + f 2

f1 − 2 f 2

f1 + 2 f 2

Frequency Figure 9.7 DAC distortion spectra: (a) Harmonic distortion; (b) Intermodulation distortion.

integer sub-multiple of the sample frequency. This ensures the quantisation noise is essentially random and not harmonically related to the fundamental. If this condition is not satisfied, the measured distortion is a by-product of the sampling process, as opposed to non-linearity in the DAC under test. Use of a sufficiently high test frequency

9.2 DAC dynamic specification considerations

321

may cause some of the higher harmonics to alias into the Nyquist band and appear non-harmonically related to the fundamental. However, they should still be ed for in any harmonic distortion calculation. For the kth harmonic, the first alias image lies at fs kfo, where fo is the fundamental frequency. If this alias image lies below the Nyquist frequency (i.e. fs kfo < fs/2) it will appear in the baseband region and will not be removed by the reconstruction filter. It must therefore be ed for in a harmonic distortion calculation. The total harmonic distortion figure is determined by calculating the root-sum-square (RSS) of each harmonic’s amplitude relative to the fundamental (or carrier) signal. A comprehensive discussion of DAC THD measurement is provided in [1]. In audio applications, the THD figure is often expressed as a percentage. Figure 9.7b illustrates a similar DAC output spectrum to Figure 9.7a, where we now use two carefully selected frequencies f1 and f2 in the digital test signal to measure the DAC intermodulation distortion (IMD). IMD products are caused by non-linearities within the DAC and take the form of erroneous spurs located at nf1 mf2, where m and n are positive integers. We express the total IMD as the dB ratio of the RMS sum of the distortion spur amplitudes to the RMS sum of the two input signals.

9.2.2

Spurious-free dynamic range (SFDR) The effects of both harmonic and intermodulation distortion spurs may be combined into a single metric called spurious-free dynamic range (SFDR) as illustrated in the harmonic spectrum of Figure 9.7a. SFDR is defined as the ratio of RMS signal amplitude to the RMS amplitude of the largest spurious component in the amplitude spectrum irrespective of frequency or cause. However, the chosen peak spurious component does not have to be harmonically related to the input signal – SFDR is only concerned with the single peak error spur in the amplitude spectrum irrespective of frequency. SFDR may be measured in dBc relative to the DAC input signal amplitude or dBFS relative to the DAC output full-scale.

9.2.3

Signal-to-noise ratio (SNR) Signal-to-noise ratio (SNR) is defined as the ratio of the near full-scale RMS signal amplitude to the RMS value of the sum of all other spectrum components, excluding harmonics measured at the DAC output. Here we are concerned with SNR specific to the DAC including its reference generator and output amplifier. In a complete DDS sinusoidal or arbitrary waveform generator, the residual spectrum components comprise quantisation noise, phase truncation error spurs, thermal noise and distortion due to the combined effects of the post-DAC analogue processing. It is important to measure SNR with a test signal whose amplitude is sufficiently clear of the clipping threshold to ensure no associated distortion products corrupt the measurement. A figure of 1 dB headroom is common in most specifications. Assuming a single sinusoidal input signal, the DAC SNR may be determined by first measuring the noise floor level in a ‘harmonic free’ part of the spectrum using a spectrum analyser. The SNR from DC to the Nyquist

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frequency (i.e. fs/2) is then calculated by subtracting the processing gain due to the spectrum analyser resolution bandwidth fBW which is typically significantly less than fs/2. A useful measurement verification technique is described in [1] that ensures the correct value of fBW has been used. A further SNR metric is often presented in manufacturers data. The signal-to-noiseand-distortion (SINAD) metric is defined as the ratio of the near full-scale RMS signal amplitude to the RMS value of the sum of all other spectrum components, including harmonics. In effect, SINAD is simply an SNR figure that includes deterministic and stochastic noise.

9.3

The reconstruction filter As a fundamentally sampled system, the spectrum of a DDS waveform generator DAC output is theoretically infinite in extent. For any synthesised waveform at a specific frequency, whose spectrum lies within the Nyquist band (i.e. is non-aliased), we observe replicated images at multiples of the sample frequency fs. The amplitude envelope of these images follows a sinc function with nulls at multiples of fs due to the zero-order hold response of the DAC. The function of the reconstruction filter is to attenuate these alias images to an acceptable level, leaving signals within the Nyquist band unaltered. Accordingly, the reconstruction filter usually follows a low- response. The ideal reconstruction filter response is unity over the Nyquist band and zero elsewhere. Of course, such a ‘brick wall’ filter is not physically realisable. Instead, a ‘real’ filter that is realisable may be represented by the approximating response shown in Figure 9.3. A real filter exhibits a nominally flat -band, possibly with some fluctuation or ‘ripple’, followed by a rapidly attenuating transition-band response to the stop-band with a finite attenuation level and possibly stop-band ripple. The finiteness of the stopband attenuation may be due to circuit imperfections or parasitic effects, or an intrinsic feature of the filter response (e.g. as with the elliptic class of filters). There are many choices for a so-called prototype filter response that we may scale to a particular cut-off frequency. In essence, prototype filters optimise one of several key performance parameters – phase response, -band ripple, roll-off slope (i.e. transition bandwidth) and stop-band attenuation. The phase response of a reconstruction filter is critical in applications requiring a constant (i.e. frequency invariant) group delay. Group delay is a measure of the time taken for signals of different frequencies to through the filter and is important in preserving waveform shape with frequency. A constant group delay is equivalent to a linear phase-frequency response. There is no one filter response that satisfies all requirements simultaneously (e.g. a constant group delay with flat -band or high roll-off slope). We are therefore forced to optimise a reconstruction filter response to application-specific requirements and thereby make calculated compromises or trade-offs.

9.3 The reconstruction filter

9.3.1

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Frequency and phase response There are numerous classes of prototype filter presented in the literature [3]. All analogue filters may be grouped and specified according to a few basic attributes: the general response shape of the filter (e.g. low- or band-); the class or type of filter response (e.g. Butterworth or Bessel); the order of the filter or the number of reactive circuit elements (i.e. capacitors and inductors); whether the filter is an active or ive implementation (i.e. uses amplifying elements such as operational amplifiers or comprises entirely ive components). Reconstruction filter design is nearly always concerned with a low- response, as shown in Figure 9.3. However, there are specialised applications where a band- reconstruction filter response is used. For example, in a narrowband DDS clock generator, as discussed in Section 5.4. Here we optimise clock jitter amplitude according to the band- reconstruction filter bandwidth at the expense of reduced frequency control dynamic range. The class of filter is an important design consideration and generally imposes a tradeoff between key parameters such as roll-off slope and -band ripple. In a low- filter, the number of reactive elements or poles sets the roll-off slope of the response. The poles represent the roots of the denominator of the filter’s transfer function. Each pole gives a 6 dB/octave or 20 dB/decade low- roll-off rate. Finally, implementation of the filter may be active or ive, where each has its own advantages and disadvantages. Active filters, for example, realise high-order filters without the need for inductors, which can be advantageous in some applications. However, ive filters are not constrained by the gain-bandwidth limitations of the amplifying elements used in active filters and are therefore advantageous in wideband applications. There are many standard filter responses each with their own advantages and disadvantages. Some of the more popular responses reported in the literature relating to reconstruction filter applications [3], are:

the the the the the the

Butterworth response; Chebyshev response; Bessel response; Cauer–Chebyshev (or so-called elliptical) response; inverse Chebyshev response; Equiripple group delay response.

The first three response classes are all-pole responses with zeros either at 0 or infinite frequency. For all low- responses the zeros are located at f ¼ ∞. Adding finite frequency zeros to the transfer function generates the Cauer–Chebyshev or so-called elliptical class of filters. Elliptical filters offer specific advantages in some applications, particularly those demanding high roll-off slopes. The Butterworth filter response provides the best compromise between stopband attenuation and phase response. The frequency response is monotonic with no

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-band or stop-band ripple, at the expense of a relatively wide transition region. The Butterworth response has the flattest -band region of all the standard filter responses and is therefore also known as the maximally flat response. Group delay varies across the -band and so the Butterworth filter exhibits overshoot and ringing in its step response whose severity increases with order. The Chebyshev response has a smaller transition region and therefore a faster initial roll-off slope than the Butterworth and Bessel responses, at the expense of -band ripple whose amplitude is a design parameter (e.g. a 0.1 dB Chebyshev response). Transition region width can be traded with -band ripple amplitude, where increasing -band ripple yields a smaller transition region. Group delay varies across the -band as a function of the filter order leading to poor step response. All Chebyshev filters have 0 dB relative attenuation at zero-frequency or DC. Odd-order filters exhibit -band ripple whose peak values all lie at 0 dB with the minimum -band gain equal to the ripple value. Conversely, even-order filters exhibit -band ripple whose peak value is the ripple amplitude and whose minima all lie at 0 dB. The Bessel response is optimised to provide linear phase and hence maximally flat group delay in the -band. The step response is therefore significantly better than the Butterworth and Chebyshev filters with minimal overshoot and ringing. The Bessel response is preferred in applications where waveshape invariance with frequency is an important design requirement. However, the penalty for an optimised phase response is a relatively poor transition region width and initial roll-off slope. The Cauer–Chebyshev or so-called elliptical response achieves a very narrow transition region (i.e. very high initial roll-off slope) at the expense of introducing ripples into both the -band and stop-band. Accordingly, the group delay varies across the band and so generally this filter has a poor step response. The inverse Chebyshev response, as its name suggests, has a monotonic ripple-free -band and ripples in the stop-band. The -band performance exceeds that of the Butterworth in of group delay variation with frequency. The transition region has the steepest roll-off slope within this group of filter classes. The Equiripple group delay response is optimised to provide ripples in the group delay response (as opposed to the frequency response) across the -band that are bounded to a specified value. The phase response is nominally linear with minimal overshoot and ringing in the step response. The choice of filter class and order is entirely dependent on system requirements, and in general no one filter response will satisfy all requirements. Many reconstruction filter requirements are mutually exclusive and so we must either compromise on a single response or use multiple filters selected according to specific operating modes. In a flexible (i.e. configurable) waveform generator architecture, we select the reconstruction filter to optimise its response to a specific application. For example, when generating low distortion sine waves or low jitter square waves based on hard-limited sine waves, we use an elliptic filter response of suitable order. This ensures good suppression of all alias spectrum components above the Nyquist frequency. Furthermore, we may design the filter to peak slightly just before cut-off to compensate for the sinc frequency response of the DAC and ensure amplitude flatness with frequency.


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Conversely, when generating arbitrary waveforms where waveshape is important, we use a Bessel filter response to maintain constant group delay.

9.3.2

Filter implementation – ive or active? A ive implementation of a linear filter uses only resistors (R), capacitors (C) and inductors (L) and therefore does not require any amplification elements or a power supply. Single pole RL and RC filters are widely applied, but higher-order responses require LC configurations. The number of reactive elements (i.e. inductors and capacitors) determines the order of the filter. In general, an active implementation of a linear filter uses only resistors, capacitors and an amplification element. In principle, an active filter may also use inductors, but one of the key benefits of an active topology is to provide filter structures that do not require inductive components. Inductors (like all components) can be particularly problematic in some cases, although they may be unavoidable in some filter topologies (e.g. very high frequency filters or where an amplification element is impractical). The amplification element may be required to provide gain or be unity gain depending on the filter topology. Irrespective of its gain, the amplifier also serves as an impedance convertor, buffering a high impedance circuit node and reproducing the node voltage from a low (ideally zero) impedance source. Active filters therefore require a power supply. The choice of implementing a reconstruction filter using an active or ive topology is governed by many interrelated factors, which include:

filter bandwidth (i.e. reconstruction filter cut-off frequency); filter transition region width (i.e. filter roll-off slope); filter stop-band attenuation; component sensitivity; noise susceptibility; linearity and distortion; SNR degradation (i.e. amplifier thermal noise or ive filter insertion loss); cost; size; power supply noise coupling considerations.

A key decision factor in determining an active or ive topology is the feasibility of using inductors. In low frequency filters, the physical size and number of inductors in a ive implementation may be prohibitive, particularly if the frequency response specification requires a high-order filter. The size and cost of an inductor generally increase with inductance and there comes a point where the size envelope becomes impractical, particularly if many are required. Furthermore, parasitic effects such as winding resistance, capacitance and core losses generally degrade filter performance, which assumes ideal component behaviour. Another consideration in the active or ive decision is the phenomenon of component sensitivity. Sensitivity describes the variation in an important filter parameter, such as cut-off frequency or -band ripple, with the variation of a specific

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component’s value due to finite tolerance. A comprehensive discussion of this topic is beyond the scope of this book, but the sensitivity of a potential filter topology should be investigated as part of the design process, particularly if it is to be produced in large quantities. In general, higher-order filters incur greater component sensitivity. Any ive filter comprising multiple inductors introduces the problem of noise susceptibility. An inductor (by definition) is inherently susceptible to oscillatory magnetic fields from any external source. These fields tend to induce a corresponding noise voltage in series with the inductor by mutual inductive coupling and thereby provide a noise-coupling mechanism onto the signal ing through the filter. If we also consider the inductor’s shunt parasitic capacitance, a parallel resonator is formed which will amplify any induced noise voltage at or near the self-resonant frequency. Parasitic effects are an important consideration in all ive circuit elements and lead to the metric of self-resonant frequency. A real inductor possesses series parasitic resistance and shunt parasitic capacitance making it a parallel damped resonant circuit at some (usually high) frequency. A similar property applies to real capacitors, which possess series resistance and inductance forming a damped series resonant circuit which resonates at some frequency. Even resistors are not exempt, possessing series inductance and shunt capacitance. In general, parasitic resonances tend to occur at high frequencies, but the self-resonant frequency of any component must be assessed before being designed into a reconstruction filter, whether active or ive. A simple rule is to always ensure that the reconstruction filter cut-off frequency is at least an order of magnitude less than the lowest self-resonant frequency of its components. An illuminating performance comparison of different ive filter designs and construction layouts is provided in [4]. In particular, for the high frequency example application investigated, the effect of filter implementation and PCB layout is striking. For low frequency reconstruction filters, inductors are undesirable due to their size and cost and so we use an active filter implementation requiring only resistors, capacitors and amplifiers. The penalty is that we now have new problems of amplifier nonlinearity (i.e. distortion), finite gain-bandwidth product and thermal noise, in addition to power consumption and power supply noise susceptibility. For the closed-loop amplifier to exploit the benefits of negative (e.g. flat gain response and reduced distortion), its gain-bandwidth product (GBP) must exceed the filter cut-off frequency by an adequate margin – at least an order of magnitude. This becomes progressively more difficult to achieve with increasing frequency (e.g. a 100 MHz active filter requires amplifiers with a GBP of at least 1 GHz). There is also a noise susceptibility mechanism analogous to the inductor case discussed earlier, namely capacitive coupling. This is a particular problem with high impedance circuit nodes within the filter networks. However, use of electrostatic screening and circuit partitioning to mitigate this problem is generally easier than with interfering magnetic fields. The introduction of many series-connected amplifiers in the signal chain introduces a cumulative thermal noise voltage and therefore degrades SNR. The amount of noise added into the filtered signal depends upon the amplifier itself (i.e. its input noise voltage), closed-loop gain, gain-setting resistor values


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(i.e. Johnson noise) and above all, bandwidth. Additionally, in some implementations, the effects of amplifier input noise current may also become significant. With increasing frequency, the amplifiers within an active filter become a more challenging design problem. Ensuring a flat closed-loop amplifier gain and phase response so that the amplifier does not significantly affect the frequency selective filter network becomes harder to achieve with increasing frequency. Eventually there comes a point where a ive implementation, that now requires much smaller inductors, becomes practical if not optimal when weighing-up all of the design considerations. Unfortunately, the transition frequency between active and ive reconstruction filter implementations is not clearly defined and there is generally a large ‘grey area’ where either solution is acceptable. Cost, size and component count may increasingly become the deciding factors.

9.3.3

Signal distortion pitfalls – maintaining SFDR Irrespective of active or ive implementation, real components in real filters exhibit non-ideal behaviour. Here we are concerned specifically with non-linear component behaviour that causes signal distortion and hence a degradation in SFDR. The SFDR of a high performance DAC can be ruined by subtle distortion mechanisms in the reconstruction filter or any of the analogue post processing stages. Indeed, ‘good’ 24-bit DAC parts are now commonplace in the audio bandwidth domain. One would not normally associate a low- reconstruction filter with a source of non-linearity and distortion. However, with the increasing dynamic range and bandwidth of modern DACs, subtle distortion mechanisms within the reconstruction filter and other post-DAC processing hitherto unseen become significant. It is well known and accepted that all amplifying devices, such as operational amplifiers, are not perfectly linear. This is a fundamental property of all open-loop amplifiers. To a degree, negative will always act to reduce open-loop distortion and other parameters (e.g. output resistance), but as open-loop gain reduces with frequency (at least with voltage-mode operational amplifiers) negative is not a panacea. It is better to select an amplifier that has been designed from scratch for low closed-loop distortion across a specified bandwidth and output voltage swing into a defined load. In general, amplifier distortion is minimised if we reduce output voltage swing and load current. However, reducing output voltage swing has to be balanced with maintaining SNR. A subtle distortion mechanism is observed specifically in FET input op-amps – input capacitance modulation. The amplifier input capacitance at either input terminal varies (or modulates) with common-mode voltage. When used in an inverting ‘virtual earth’ mode, the common-mode and differential input voltage are essentially zero and so this distortion mechanism cannot occur. So-called multiple filter configurations operate in this mode, although they have shortcomings which render them unsuitable in some applications. If the amplifier is used in a voltage follower or non-inverting mode, capacitance modulation in sympathy with the applied signal voltage may occur. This causes distortion if the filter network source impedance seen by the amplifier input

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is significant compared to that due to the modulating capacitance. With wide dynamic range systems, this effect can be very significant and a minute change in input capacitance can lead to significant distortion. A novel compensation scheme is suggested in [5] that is only applicable to the voltage follower amplifier configuration which is popular in many active filter topologies (e.g. the Sallen–Key configuration). This reference also presents measured distortion results due to this effect for a typical FET input op-amp, and shows the improvement afforded by compensation. If we assume that amplifier distortion within the reconstruction filter and other analogue processing is made negligible through good design and device selection, the most significant residual non-linearity mechanisms are due to ive component effects. All resistors and capacitors exhibit some degree of voltage dependency, which is defined as a variation in resistance or capacitance with the applied voltage across the component. If this voltage is oscillating (as in a filter), the variation in value causes distortion whose magnitude depends on the exact circuit configuration. Similarly, inductors may exhibit some degree of current dependency due to non-linear core material effects. Fortunately, ive component non-linearities are mitigated if not prevented by prescriptive measures. In general, the following guidelines should be observed when selecting ive components: Always check resistor and capacitor voltage dependence specifications. Metal film resistors offer good to excellent tolerance, temperature coefficient and voltage dependence. Bulk metal or metal foil resistors offer the best tolerance, temperature stability and voltage dependence performance. However, they are very expensive. Avoid carbon composition resistors. They have poor tolerance and temperature coefficient, and generally exhibit high voltage dependence causing non-linear behaviour. Use C0G or NP0 ceramic capacitors where possible. They offer very good tolerance, temperature coefficient and voltage dependence. Polystyrene, polypropylene and polycarbonate capacitors offer good tolerance and temperature coefficient and have low voltage dependence. Always prototype the exact filter design using the intended components and measure SFDR performance under all operating conditions.

9.3.4

Reconstruction filter design considerations – hints and tips Once the reconstruction filter specifications and acceptable trade-offs have been identified, the design can be undertaken using prototype filter design tables that are scaled according to cut-off frequency. Excellent filter design guidelines can be found in the established reference literature, for example [3]. For active filter designs, textbook design tables generally assume ideal amplifier elements. These do not exist in practice! The first amplifier selection consideration is GBP, ensuring there is sufficient closedloop performance at the highest frequency of operation – typically at least around the cut-off frequency of the filter. However, we must not forget that the active filtering


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process does not stop at the 3 dB cut-off point and continues into the stop-band. Subsequent amplifier selection criteria include thermal noise performance, distortion (to some extent also a function of GBP), slew rate (for distortion-free large signal performance) and unity-gain stability. Use of readily available filter design computer software (e.g. TI’s FILTERPRO or Linear Technology’s FilterCAD or PSPICE) is strongly recommended, particularly to investigate parasitic and component tolerance effects. However, there is no substitute for constructing the filter with the intended components and circuit layout and measuring its performance against specification and simulation results. Monte Carlo PSPICE simulation is highly recommended for high-order filters where component sensitivity becomes more significant. Finally, we list some important considerations for successful reconstruction filter design and implementation. These should not be too surprising and are part of good analogue design practice. However, it never hurts to be reminded! They come from many years (and tears) associated with endeavouring to make such systems work and meet specification: For a given specification, make the filter class selection (e.g. Bessel or Chebyshev) and ‘active/ive’ design decisions first. Use analysis and simulation to explore trade-offs, assess design performance and component tolerance effects. Be clear as to the required stop-band suppression level. Ideally, this should match or exceed the dynamic range of the DAC. An ideal filter (notwithstanding stop-band ripple or ‘bounce back’) will have infinite stop-band suppression. Real filters do not follow this behaviour and have finite suppression determined by filter class, circuit layout, component parasitic effects and non-ideal amplifier behaviour. For active filter implementations, carefully review the amplifier GBP, noise, distortion and slew-rate specifications. If possible, always use the manufacturers’ PSPICE models in any circuit simulations. that an amplifier’s power supply terminals are fortuitous signal inputs. Consider the amplifier’s power supply rejection ratio (PSRR) specification. This mechanism can easily corrupt -band and stop-band performance. For all medium and high frequency designs, always use a continuous ground plane below the filter components. (This rule also applies to the entire DAC and analogue post-processing.) This lowers ground inductance to the lowest practicable level. Always segregate analogue and digital grounds, and where appropriate partition analogue ground planes also. Think where the currents flow when estimating noise isolation and cross-coupling. With ive filter ladder structures, consider two ground planes on either side of the PCB tied together with multiple vias. Consider splitting shunt capacitors to ground as a mechanism for increasing selfresonant frequency and lowering inductance to ground. Consider relative component placement. Where possible, space out ive components (particularly inductors) to avoid fortuitous cross-coupling, which may degrade filter performance or cause instability in active designs. If necessary, electrostatically screen circuit sections to the local ground plane.

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Always use components with the highest self-resonant frequency and Q factor as possible. Observe the correct input and output termination impedances for ive filters. Most ive filter structures assume purely resistive source and load impedances (e.g. 50Ω).

9.4

Supplementary analogue design considerations In conjunction with the essential DAC and reconstruction filter stages, there are several further and often overlooked analogue signal processing operations associated with generation of continuous-time waveforms. For completeness, we now discuss the design considerations applicable to these operations.

9.4.1

The DAC reference voltage and output amplifier Many DACs have built-in reference voltage generators and output buffer amplifiers to form standalone functional blocks. However, to maximise flexibility and performance, some DACs require an external reference voltage and output amplifier. We now outline the important design considerations that apply to these functions. Failure to provide the required environment (e.g. a low reference voltage source impedance) can render a high performance DAC next to useless. The DAC reference voltage is the limiting factor in the absolute accuracy and spurious signal performance of the DAC. If the DAC reference voltage is noisy (e.g. contaminated with digital signals unrelated to the sample clock), this noise will invariably be ed onto the DAC output signal. The reference voltage is effectively multiplicatively scaled by the DAC digital input word to determine the output voltage or current. Most DACs specify their reference voltage within a narrow range to ensure specified static and dynamic performance. Exceeding this range can result in degraded performance or even damage to the device. Additionally, depending upon the internal DAC architecture, the reference input impedance can vary dynamically with input code. In turn, this requires that the reference voltage output impedance remain constant or settle sufficiently quickly following a transition in reference load current. The DAC conversion process can also inject transient noise onto the reference voltage pin necessitating local, wideband capacitive decoupling close to the DAC reference pin. In turn, the reference voltage buffer amplifier must remain unconditionally stable when driving a large capacitive load. If the DAC reference voltage is being taken from a DC voltage used elsewhere in the system, consideration must be given to the stability and fast settling of that reference under capacitive load. It is good practice, particularly in high performance (i.e. high dynamic range) applications, to provide a buffer amplifier and reference decoupling adjacent to the DAC reference pin. There are many unity-gain stable operational amplifiers designed specifically for this purpose available from the usual manufacturers. It is important to that the DAC reference port and power supply inputs are fortuitous noise inputs. Any noise coupled into the reference circuitry may appear on

9.4 Supplementary analogue design considerations

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the DAC output and seriously degrade SFDR performance. Similarly, noise appearing on the DAC power supplies combined with poor grounding may also corrupt the DAC output and seriously degrade performance relative to specification. Always , the layout, noise filtering and ground management of both the DAC and any off-chip reference voltage generator are as important as the signal path. Finally, it is essential to ensure proper ground management around the DAC, its reference voltage and output amplifier. Even if these components are integrated into a single DAC package, good ground management is still mandatory. Failure to properly manage analogue and digital grounds will nearly always turn a highly specified DAC into a near-useless one. Furthermore, the errors introduced cannot be removed by any amount of well-designed analogue post-processing. The key requirements are maintaining a low impedance analogue and digital ground reference and separating all analogue and digital current paths into respective ground structures. An excellent discussion of high resolution data convertor grounding and power supply provision is given in [1], which we summarise here: In general, ground and power planes are mandatory! Always separate analogue and digital ground planes. analogue and digital ground planes at a single system ‘star’ ground or reference ground plane (e.g. a backplane) where possible. Never overlap analogue and digital ground planes, to avoid noise contamination due to capacitive coupling. Be mindful of circuit susceptibility if a voltage differential should appear between analogue and digital ground planes (e.g. local to a DAC). This could occur under ‘hot swapping’ conditions, when a PCB is plugged into a backplane. Placing ‘back-to-back’ Schottky diodes between the two planes clamps differential voltages to less than 300 mV and prevents damage or component latch-up. Always decouple power supply and reference voltage pins to the correct ground plane. Always follow recommendations made on a data convertor’s data sheet or application note. Invariably, the recommended operating environment (i.e. supply decoupling, grounding, etc.) will have been used to performance and to underwrite the manufacturer’s data sheet. The output of a DAC may be a voltage or a current depending on its internal architecture. Most wideband, high resolution DACs are current-output devices and have differential outputs for improved common-mode rejection and to reduce even-harmonic distortion components. Some wideband devices include built-in termination resistors (often 50 Ω) and therefore look like voltage sources with exactly 50 Ω source impedance. This type of DAC is capable of driving a ive LC ladder filter directly, assuming the filter is matched to the source and load impedances. Such filters require that their source and load impedances are purely resistive (e.g. 50 Ω) and constant. The filter may be fully differential (and therefore balanced) to match the DAC output or single-ended and the DAC output run in single-ended mode by grounding one of its outputs. A post-filter impedance conversion amplifier may still be required to provide a low impedance output, however.

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A DAC current source output has an associated compliance voltage specification that determines the permissible output voltage swing for the DAC to remain within its linearity specification. Optimum linearity and hence distortion performance are often achieved and specified when the DAC current-output port feeds a virtual ground (i.e. a single-ended convertor) and so the output current source voltage swing is zero. However, some DACs are specified to drive a resistive load and therefore develop a small output voltage. Always consult manufacturers’ recommendations in the data sheet or application note. Device performance is often optimised under non-ideal conditions. In applications where a single-ended DAC output is required, an additional amplifier stage is needed to make the conversion. Figure 9.8 illustrates output amplifier configurations for a differential to single-ended convertor and a single-ended convertor. The latter configuration ensures a zero DAC common-mode output voltage and hence optimal linearity. A differential current-output DAC may also be used with a differential-to-differential convertor, providing a differential output voltage. If a suitable amplifier is used, this configuration also allows the output common-mode voltage to be set independently, which can be advantageous is some applications. Voltage output DACs may be buffered ‘on-chip’ and therefore require no further processing before feeding any deglitch circuitry or reconstruction filter. Unbuffered voltage output and current-output DACs have a relatively high output impedance comprising a resistive component and a reactive one. Some current-output DAC structures have an output impedance that varies with the digital input code and causes a corresponding variation in the noise gain of the current-to-voltage output amplifier.

9.4.2

Switched attenuation and output level control The signal which emerges from the DAC and reconstruction filter is normally at DAC full-scale level. This assumes a unity gain reconstruction filter. In many applications we may wish to control the amplitude of our synthesised waveform to some degree of accuracy. In this section we outline several methods for implementing waveform amplitude control. The simplest amplitude control method takes place entirely in the digital domain and involves multiplicative scaling of the discrete-time waveform signal before the DAC. This method introduces one significant drawback – reduced SNR due to the waveform being represented with fewer bits. In the limit, for very small amplitudes our waveform approaches a square wave! Obviously, for small amplitude control relative to full-scale, this method is effective and has the advantage of only requiring a multiplier block in the digital processing. There was a time when a digital multiply operation represented a significant overhead in the digital processing. However, today the abundance of high speed multiplier blocks in many FPGA families, for example, alleviates this concern significantly. An improved technique is to use a ‘floating point’ approach. The analogue (i.e. continuous-time) waveform is always generated at DAC full-scale and therefore has an SNR determined essentially by quantisation noise. Amplitude control is imposed by an analogue multiplier followed by a ‘switched gain amplifier’ (in arbitrarily fine steps).

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Generic differential current-output DAC

iout Rout Rout

b

iout

Differential DAC output

−

Vout

+

b DAC

Single-ended DAC output Virtual ground

−

+

Vout

b DAC Figure 9.8 Two buffer amplifier configurations for a current-output DAC. A fully differential

DAC output maximises common-mode rejection, but can cause common-mode voltage distortion in the output amplifier. This distortion mechanism is eliminated when the DAC is driven into a virtual ground.

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Amplitude control is now imposed entirely in the analogue domain. If we ignore thermal noise in the multiplier and switched gain amplifier, the SNR of the output signal remains constant with amplitude. In reality, this represents an oversimplification and the noise contributions from the multiplier and switched gain amplifier must be taken into . The switched gain amplifier may be switched to provide gain or attenuation. If the multiplier dynamic range matches the attenuation steps, a continuous variation in output amplitude can be obtained. This, of course, requires ‘intelligent’ control of the multiplier gain and switched amplifier gain according to a single amplitude parameter. In reality, the multiplier dynamic range should slightly exceed the attenuation step size. The SNR of the resultant signal will generally be dominated by the input voltage noise of the multiplier. Furthermore, the multiplier may contribute significant harmonic distortion compared to the DAC and therefore dominate SFDR performance. Several analogue component manufacturers produce wideband, high linearity multiplier ICs. For example, the AD835 from Analog devices which has a bandwidth of 250 MHz and 2nd harmonic distortion of around 70 dB at 10 MHz. For applications where the DAC resolution is 12-bits or less, the distortion performance of the analogue multiplier can generally be engineered to match that of the DAC, at least over a specified bandwidth. For higher resolution systems, the multiplier dominates distortion performance and the extra DAC bits are effectively wasted. The analogue multiplier may be replaced by a multiplying DAC (MDAC), assuming the chosen part is specified for low distortion. An attraction of the MDAC approach is that it is inherently more linear than an analogue multiplier, comprising only analogue switches and a resistor network. Typically, a SNR/SFDR trade-off has to be made to ensure that the MDAC reference voltage amplitude (which is now our waveform signal) operates the MDAC in its most linear region. The multiplier may be omitted entirely by using a finer resolution switched gain amplifier, perhaps with 1 dB resolution to control the waveform amplitude. This is the optimal approach for maximising SFDR performance, as the attenuator switching can be accomplished with relay switches that are intrinsically linear. Faster amplitude switching can be imposed by using electronic FET switches instead of relays. However, a degradation in SFDR can be excepted due to the intrinsic non-linearity of these devices. A series cascade of binary weighted ive attenuators with attenuation values following a 1, 2, 4, 8, 16,. . . dB sequence enables digitally programmable amplitude in 1 dB steps. Attenuator stages are switched in or out according to their respective binary bit value in the amplitude control word. The dynamic range is determined by the number of stages and for n stages the attenuation ranges over the interval [0, 2n 1] dB. A 6-stage switched attenuator provides up to 63 dB of attenuation in 1 dB steps. If followed by a þ20 dB gain amplifier, the switched gain range is now þ20 dB to -43 dB in 1 dB steps. If amplitude stability is paramount, an ‘amplitude levelling loop’ may be utilised. Servo-stabilised amplitude also provides the additional benefit of compensating for DAC gain error temperature drift in ‘amplitude critical’ applications. We introduced this technique in Chapter 1 when stabilising the amplitude of the Wien bridge and state


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variable sinusoidal oscillators. Figure 1.14 illustrates the amplitude levelling loop concept applied to the state variable oscillator. This application is analogous to our digital waveform generator DAC where the DAC reference voltage can be used to adjust the output signal amplitude within the loop. Two design considerations are evident – precise measurement of the output amplitude and continuous control of amplitude to ‘close the loop’. At low frequencies, a precision rectifier may be used to measure the peak-to-peak amplitude of the output waveform, and the servo action of the levelling loop acts to regulate peak-to-peak amplitude relative to a high stability setpoint reference voltage. A correction factor (the waveform crest factor) can be computed for a given waveform to calibrate the output amplitude in RMS. For higher frequencies, it may be preferable to use a thermal RMS-to-DC convertor to measure the RMS amplitude of the output signal. The levelling loop now acts to regulate RMS amplitude relative to a high stability set-point reference voltage. To complete the amplitude levelling loop, we need a high linearity voltage (or current) controlled gain block. Failure to observe the linearity requirement may result in reduced SFDR. Two solutions are evident – use a high linearity multiplier as with the continuous amplitude control discussed earlier, or servo the DAC reference voltage to regulate output amplitude. The design considerations of the multiplier option are already apparent and this is probably the simplest to design. Controlling the DAC reference over a small range allows amplitude stabilisation over an identical range and maintains SFDR or constrains its variation within acceptable limits. This assumes that the DAC reference is available to be controlled directly (i.e. not on-chip) and SFDR is specified over a suitable range of reference voltages. Servo amplitude stabilisation is best applied as a fine adjustment with a switched gain section providing coarse amplitude control. Finally, the loop bandwidth of the amplitude levelling loop tends to be a function of signal frequency (particularly with thermally based RMS amplitude measurement). As the signal frequency reduces, so too must the loop bandwidth. When deg an amplitude stabilisation loop for a DDS waveform synthesiser, we must that the minimum output frequency may be extremely small and the loop bandwidth should therefore adapt accordingly.

9.4.3

DC offset and output dynamic range considerations In many applications, we may require a particular waveform with a variable DC offset of either polarity. This, in turn, leads to output dynamic range considerations since the peak waveform voltage plus the DC offset must be within the saturation point of the output amplifier. For a given amplifier saturation voltage (i.e. the output voltage at the onset of clipping), the permissible DC offset and waveform amplitude are mutually exclusive. A large output amplitude can only have a small DC offset imposed before clipping, whereas a smaller output amplitude can have a larger DC offset before clipping. This situation is complicated further when we generate an arbitrary waveform with a large crest factor (i.e. peak to RMS amplitude ratio). If we specify the output amplitude in RMS and require a particular DC offset, we must ensure that the peak voltage plus the DC offset sits within the permissible headroom of the output

336


amplifier. An offset voltage may be added to the signal path using a precision summing amplifier, or a DC current injected into the constant source resistance amplitude attenuator network. Precision attenuators, particularly wideband ones, are designed to work with exact source and load resistances, typically 50 Ω (although any value can be chosen for design convenience). This characteristic can be exploited to add an offset current that produces a corresponding offset voltage when developed across the termination resistance.

9.4.4

The output drive amplifier The flexibility and potentially very low SFDR performance of a DDS arbitrary waveform generator enables the generation of highly precise waveforms and spectra. However, it is all too easy to forget the final output stage that has to drive a critically specified waveform into a load and faithfully preserve its waveshape or spectrum. Even if we assume a ‘tame’ purely resistive load (e.g. 50 Ω), the output amplifier design is still non-trivial, where the following design considerations are paramount: The full-power amplifier bandwidth must exceed the Nyquist frequency. The amplifier output voltage swing must accommodate the required DC offset range with sufficient headroom to minimise signal distortion. The amplifier must supply the peak output current under worst case load resistance. The amplifier slew rate specification must exceed the worst case signal slew rate considering bandwidth and full-scale output swing. The amplifier’s distortion specification, particularity under full load, must exceed the SFDR of the DAC. The amplifier transient response and overshoot specification must ensure a wellbehaved response for small and large output signals. An amplifier’s slew rate specification defines the maximum permissible rate of change in output voltage where the amplifier behaves as a linear system. It is therefore a large signal phenomenon. Slew rate is measured in volts per unit time, and so small amplitude signals have a smaller maximum slew rate than large amplitude ones. For a sinusoidal voltage waveform, the fastest rate of change occurs around the zero-crossing points, and for a peak amplitude A the maximum slew rate is given by 2πfA volts/second, where f is the waveform frequency in Hertz. If the signal slew rate exceeds the amplifier specification, slew rate limiting will occur where sine waves appear increasingly like rounded triangle waves. Full-power bandwidth, the output voltage swing requirement and slew rate specification are closely interrelated. If the output amplifier (or indeed any amplifier in the signal chain after the DAC) is slew rate limited, significant waveform distortion occurs and SFDR degrades due to harmonic distortion. In some bespoke applications the output amplifier may have to drive reactive loads, yet preserve waveform characteristics. This complicates the output amplifier design considerably, affecting stability and transient performance.


9.4.5

337

Square and pulse waveforms In this section we investigate methods for generating square and pulse waveforms whose transition times (i.e. rise and fall times) are inconsistent with the bandwidth of the waveform generation system. The bandwidth of a DDS arbitrary waveform generator is ultimately bound by the Nyquist frequency and set by the cut-off frequency of the post-DAC reconstruction filter. Accordingly, there is a lower limit on the transition time of any arbitrary waveform. If we do not require the waveshape definition flexibility afforded by arbitrary waveform generation, we may generate square and pulse waveforms by a different approach. The DDS waveform generator is configured to generate a pure sinusoid whose frequency and phase offset may be set according to the resolution of the phase accumulator and phase–amplitude mapping method, respectively. The reconstruction filter should be designed so as to provide maximum suppression of all stop-band alias images above the Nyquist frequency, suggesting an elliptic filter class. This ensures that phase jitter is minimised in the subsequent limiting operation that we consider next. The filtered sine wave is then fed to a fast comparator (or ‘amplitude limiter’) whose reference input is held at zero volts. The comparator function constrains the output voltage to one of two states, thereby generating a square waveform. If we assume that the input sine wave oscillates exactly about zero (i.e. there is no DC offset present) and the input offset voltage of the comparator is also zero, the output of the comparator is a square waveform with exactly 50% duty-cycle. The transition times of this square wave are bound only by the speed of the comparator output stage and the bandwidth of any subsequent amplification and offset processing. Phase jitter is determined by several design considerations:

phase truncation and quantisation noise in the DDS phase–amplitude mapping; residual alias signals above the Nyquist frequency after the reconstruction filter; DAC harmonic distortion; inherent sample clock phase noise; comparator switching jitter due to its inherent input noise voltage.

Ideally, the phase–amplitude mapping should be designed so that the last four error mechanisms dominate the overall phase jitter. The relationship between non-harmonic error spur magnitude relative to the fundamental and post-limiting phase jitter has already been presented in Section 5.4.2. For a given reconstruction filter design and hence residual magnitude of sub-Nyquist phase truncation error spurs, we can determine the theoretical peak-to-peak jitter assuming an ideal comparator and sample clock. This analysis also assumes no harmonic distortion in the sine wave signal fed to the comparator, which is predominantly a function of the DAC. The DAC should therefore be specified to have harmonic distortion below the worst case level of DDS phase truncation error spurs. In principle, the sample clock phase noise can be made vanishingly small compared to the magnitude of phase jitter due to the other mechanisms by suitable choice of reference oscillator. Finally, the inherent comparator phase jitter must be considered in the phase jitter budgeting.

338


Now that we have generated a near-ideal square waveform, how do we set about generating pulse waveforms whose pulse width remains constant with frequency? The answer is very simple – we apply the same techniques as used in ‘classic’ analogue pulse generators! A pulse waveform can be generated by a voltage-controlled monostable whose width is set by a control voltage provided by a DAC under digital control. Alternatively, the pulse generating monostable function could be implemented digitally. A high speed clock that is a synchronous integer multiple of the DDS sample frequency is used to clock a counter that determines pulse width. Each rising edge of the DDS square waveform sets a D-type flip-flop that enables a synchronous counter to count that is clocked at the high timing frequency. The counter is enabled to count by being taken out of a reset condition and hence counts upwards from zero. A digital comparator compares the counter output value with a parameter which sets the pulse width in integer multiples of the fast clock period. When the counter value matches the width setting parameter, the comparator output resets the D-type ready for the cycle to begin again on the next DDS cycle. The D-type counter enable pulse is the variable width pulse output signal. In principle, there is no upper bound on the fast clock frequency, which is determined by the required pulse width control resolution and logic speed. Finally, in keeping with a comprehensive square and pulse waveform generator, we consider control of pulse transition (i.e. ‘rise’ and ‘fall’) times. This is relatively straightforward to accomplish and borrows techniques first seen in Chapter 1 when we investigated analogue waveform generation based on switched integration. In essence, we adapt the switched integrator concept used in a positive relaxation oscillator to control the slew times of a pulse waveform. The switched integrator is used ‘open loop’ to provide what is effectively a current-controlled slew rate limiter. If the integration currents are controlled from a DAC we can digitally control the edge transition times. The pulse waveform is first clamped to precisely defined voltage levels using a ‘clamp amplifier’. A clamp amplifier is designed to operate normally when in its linear region, but saturate or clip at well-defined voltage levels. The symmetrical level pulse waveform controls a balanced diode ring switch that steers a current source into an integrating capacitor according to the pulse state. If the diodes are well-matched (in forward voltage drop), the capacitor voltage will stabilise at the input clamp level, producing a pulse of the same amplitude as the input, but with linearly slewed edges. Independent charge and discharge current sources allow the rise and fall times of the pulse waveform to be independently controlled.

9.5

Summary The DAC is the most performance-critical component in converting from the digital domain to the analogue (i.e. continuous-time) domain. As we have seen in earlier chapters, it is now possible to generate near-ideal discrete-time (i.e. digital) sinusoidal and arbitrary waveforms in of their quantisation noise, harmonic distortion and

9.5 Summary

339

SFDR. Phase jitter performance in the synthesised waveform is ultimately bound by the sample clock phase noise and can be made vanishingly small by appropriate design of reference oscillator. In principle, we can generate near-perfect (or at least very well-characterised) discrete-time or digital signals. The DAC is the first stage in realising a continuous-time representation of our discrete-time waveform and must therefore be chosen carefully. If we choose the wrong DAC for a particular application or, more likely, fail to apply the appropriate hardware design considerations to the ‘correct’ DAC, we generate an analogue signal inferior to that expected. In some instances, it is dramatically so. In this section we have reviewed the specific DAC error mechanisms that are most important in digital waveform generator applications. We have discussed how these mechanisms affect the key performance metrics of SNR, THD and SFDR that are used to measure the quality of electronically generated signals. The reader should now be suitably equipped to select the most appropriate DAC for a given specification or at least to make well-informed trade-offs between less optimal parts. The next stage in the conversion to a continuous-time signal is the low- reconstruction filter. As with the DAC, this seemingly simple function, that is easily designed using a ‘cookbook’ methodology, can contain many pitfalls which conspire to give less than optimal SFDR or even add distortion of their own. The selection and design of reconstruction filters are worthy of a whole book in their own right, and here we have only outlined the most important aspects. We have discussed the class and order of a reconstruction filter and considered how these attributes affect important trade-offs between frequency and phase response and the all-important suppression of alias signals above the Nyquist frequency. Occasionally, compromises have to be struck between the class, order and implementation method of a reconstruction filter, as dictated by cost and SFDR performance, for example. We have also discussed the relative merits and issues of active or ive filter implementation. This decision is driven by considerations of bandwidth, possible EMC susceptibility and component sensitivity (i.e. tolerance effects). In general, we observe that ive LC filters are the only practicable option for very high cut-off frequency filters, and active filters (which ‘design out’ the inductor elements) are optimal for lower frequency applications. The transition region between these two camps is not clearly defined, however. The non-ideal behaviour of ‘real’ ive components can act to deviate a filter’s frequency response from that intended or introduce harmonic distortion due to non-linear mechanisms. In essence, ive components within a reconstruction filter can, if not chosen correctly, add real distortion and hence degrade SFDR. Indeed, this is also true of any ive component in the signal path, particularly with very wide dynamic range convertors. We have concluded our discussion of reconstruction filter design considerations by presenting a selection of useful design ‘hints and tips’ that should help steer the wary designer away from the most serious pitfalls. Finally, we have discussed several supplementary analogue processing design considerations that affect the implementation of waveform generators for real-world applications.

340


9.6

References 1. 2. 3. 4.

W. Kester, The Data Conversion Handbook, Newnes, 2005. W. Kester, High Speed Design Techniques, Analog Devices, 1996. Wai-Kai. Chen, The Circuits and Filters Handbook, CRC Press, 1995. D. Brandon and K. Gentile, DDS-based clock jitter performance vs DAC reconstruction filter performance, Analog Devices Application Note AN837, http://www.analog.com/, 2006. 5. W. Jung, Op Amp Applications Handbook, Newnes, 2005.

Index

Accumulator Arithmetic 111 Modulo 53, 64–5, 273 Multiplexed 237, 252, 272 Partitioning 280–3 Segmentation – see accumulator partitioning Active filter 323, 326–9, 339 Analogue-to-digital convertor (ADC) 6, 222 Adder Carry look-ahead 274–5 Carry propagation 274 Pipelined 275 Arbitrary function generator (AFG) 18–19 Aliasing Amplitude envelope 112–14 Definition 73 Harmonic 170–2 Image frequencies 51, 54, 65 Mitigation 82, 86 Amplitude Accumulation 261 Control 76, 79 Definition 9 Modulation 133, 241, 243 Peak 9 Peak-to-peak 10 Quantisation 6, 55 RMS 10–11 Spectrum 28, 75, 77, 89, 122, 129, 135, 144 Stabilisation 335 Analogue oscillators Amplitude stabilisation 34–5 Charge-balancing 22, 38–9 Digital control 23, 34 Performance limitations 38–41 State variable 34 Switched integration 36 Voltage to frequency convertor (VFC), see chargebalancing Wien bridge 32 Analogue waveshaping 23–4, 32, 203–12 Anti-alias filter see reconstruction filter

Aperiodic signal 6–7 Arbitrary waveform Applications 41 Constraints 162 Regenerating DSO waveform 19, 62 Specification in the frequency domain 178 Specification in the time domain 172 Automatic test equipment (ATE) 32, 42 Auto-calibration 27 Arbitrary waveform generator (AWG) 2, 7, 18 Audio testing and measurement Crosstalk 223, 241 Frequency response 223 Harmonic and intermodulation distortion 222, 229 Multi-tone 223–5 Single-tone 223 Band- Filter 19, 34, 214, 323 Signal 82, 251 Spectrum synthesis 43, 299, 302, 305 Bandwidth Harmonic 73, 86 Nyquist 51, 85 Reconstruction filter 134, 216, 323 Waveform synthesis 45, 50, 160 Barkhausen stability criterion Continuous-time form 20, 33 Discrete-time form 90 Baseband signal 44 Bill Hewlett 34 Biquad-form see direct-form Block pipelining see pipelining Cardiac waveform 7, 10 Carrier signal 43–4, 87, 215, 228, 241–3, 248 Carry look-ahead see adder Chirp generation 246 Clock generator 30, 213

342

Index

Computer music Frequency and pitch 221–2 Harmonics and partials 220–1 Human perception considerations 221 Tuning 221–2 Continuous-time 5, 14–15, 27, 49 CORDIC 155 Coupled-form see recursive oscillators Crest factor 10–11, 133, 135, 160, 224, 335 Critical sampling 134, 160, 309 Cut-off frequency 31, 34, 114, 217–19, 311, 322, 325, 328, 337, 339 Digital to analogue convertor (DAC) Capacitive 23 Current output 208, 332–3 Non-linearity 317 Output amplifier 321, 330 Output glitch 307, 310–11, 317 Reference voltage 23, 208, 307, 315, 330–1 Settling time 315 Voltage output 332 DAC distortion mechanisms Capacitance modulation 327 Differential non-linearity 317 Harmonic distortion 317, 319, 331, 334, 336 Integral non-linearity 317 Intermodulation distortion 321 Output amplifier 327–8, 336 ive component effects 327–8 Power supply decoupling and grounding 40, 331 Reconstruction filter 327–8 DC offset 307, 311–12, 335–6 Direct digital frequency synthesis (DDFS) 2 Direct digital synthesis (DDS) 2 Deglitcher 307, 310, 332 Discrete Fourier transform (DFT) 15 Diagnostic testing 2, 19, 41 Direct synthesis 24 Direct-form see recursive oscillators Discontinuity Amplitude 16, 81, 97–8 Phase 163 Recursive oscillator frequency change 96–7 Discrete-time 5–6, 12, 50 Distortion Harmonic 34, 75, 82, 108, 126, 218, 222, 229, 238–9, 256, 317, 319, 331, 334, 336 Intermodulation 15, 39, 42 Dither 127–8, 138–43, 159–60, 187, 191, 203, 213–14, 226, 318 Dual port memory (DPM) 269–73, 301–2 Drift 23, 32–3, 38–40, 45, 102, 211, 313–15, 334 Digital signal processing (DSP) 5–6, 266, 273, 309

Dynamic range Amplitude control 10, 54, 75, 79 Defined 75 Frequency control 75, 77 Headroom 10, 134, 273 Noise floor 55 Phase offset control 78–9 Spurious-free – see sFDR Dynamic spectrum control 254–6 Dynamic waveshape control 228 ECG waveform 7 Error mitigation Frequency control 28, 32, 58 Noise shaping 127–8, 138 Phase dithering 127, 138 Phase offset control 78, 124 Phase truncation 122, 127, 138, 214, 223, 252 Error Aliasing 73, 77, 82 Amplitude 79 Amplitude quantisation 54 Control linearity 23, 38, 75, 82 DDS model 128 Phase noise 86 Phase truncation 28, 72, 83, 117 Spectrum 72, 85 Waveshape 83–6 Fast Fourier transform (FFT) 119, 135 Filter Active 323, 325–9, 339 Anti-alias, see reconstruction filter Class 323–4, 329, 337 Distortion mechanisms 327–8 Group delay 311, 322, 324–5 Order 323 -band ripple 322, 324 ive 323 Phase response 311, 322–3, 327 Reconstruction, see reconstruction filter Roll-off slope 322–5 Sensitivity 325, 329, 339 Stop band 311, 322 Transition band 325 Foldover see aliasing Fractional addressing 59, 64, 70 Fractional phase component 83, 144, 295 Fractional-N PLL 24, 26, 32, 45 Frequency Control range 99, 216 Control resolution 28, 32, 59 Definition 6 Modulation (FM) 31, 109, 111, 242, 274 Reference 24, 77 Frequency shift keying (FSK) 108, 244

Index

Frequency synthesiser 22, 24, 26, 32, 203, 205 Fundamental frequency 13, 30, 50, 82, 119, 163–4, 170, 172, 218, 237–9, 241, 249–50, 260, 302, 319 Gain error see DAC Generic form see recursive oscillators Gibbs phenomenon 170, 177–81 Glitch, see DAC output glitch Harmonic Contiguous phase indexing 258 Non-contiguous phase indexing 262 Phase offset 260 Hewlett–Packard 19, 31 History of digital waveform generation 17 Hybrid waveform synthesis 23 Ideal arbitrary waveform DDS 184 Ideal sinusoidal DDS 112 Inverse discrete Fourier transform (IDFT) 4–5, 16, 30, 60, 63, 82, 89, 239, 249–52 Initial conditions see recursive oscillators Initial phase 9, 12, 52, 116, 158, 243, 246 Instantaneous frequency 6, 11, 87, 110, 213, 246, 253 Instantaneous phase 10–14 Integer phase 71–2, 116, 128, 236, 295 Integrator 22–3, 34, 207, 211 Interleaved DAC 27 Intermodulation distortion see distortion Interpolation see phase interpolation Jitter Filter 207, 217–18 Phase noise 25, 28, 30, 86, 129, 205–6, 208, 213–17, 323–4, 337 Lagrange polynomial interpolation see phase interpolation Lanczos sigma factor 177, 179, 181 Linear wavetable combination 80, 228 Linearity errors see DAC non-linearity Lookup table see wavetable Multiplying DAC (MDAC) 23, 211–12, 219, 308, 334 Metaparameter 74–5, 82, 239, 254–5 Modified coupled-form see recursive oscillators

343

Modular arithmetic 12 Modulo integer multiplication 263–4 Numerically controlled oscillator (NCO) 2 Negative frequency 111, 274 Noise 6–7, 10, 20, 25, 28–9, 54, 60, 72, 75, 79, 83–4, 86 Non-harmonic signals 4, 7, 16, 82, 85, 138, 163, 215, 218, 224, 226, 241, 251, 299, 304, 321, 337 Nyquist bandwidth, see Nyquist interval Nyquist interval 51 Oscillator Analogue 32, 34, 36, 38 Recursive – see recursive oscillators Taxonomy 19 Oversampling interpolating DAC 27, 308 Oversampling ratio 134, 309 Paged addressing 80, 228–30, 233 Paged wavetable interpolation 80–1, 228, 233–6 Paged wavetable interpolation memory 296 Parallel processing 4, 30, 266–7 Performance metrics Amplitude error sequence 54, 83 Amplitude error spectrum 40, 85 Phase noise 86 Phase truncation noise 72, 83 SFDR 28, 40, 85 SNR 10, 43, 55, 83–4 Waveshape error 83–5 Period 6 Periodic signal 7 Permutation of error spurs 130, 135–6 Phase Accumulator 25, 27–8, 65, 110, 128, 132, 205–6, 213–14, 273, 281, 301 Continuity 16, 61, 68–70, 103 Discontinuity 96–7, 163 Dithering, see dithering Interpolation 4, 59, 88, 109, 115, 122–4, 144–52, 163, 166, 192, 195–203, 277–8, 283–96 Noise, see jitter Offset 9, 50, 52, 65, 72, 74, 78–9, 93, 124–7 Quantisation, see phase truncation Truncation 4, 72, 83–6, 115–22 Phase shift keying (PSK) 244–6 Phase shift oscillator see analogue oscillators Phase–amplitude mapping Arbitrary waveform 186–203 Error mechanisms 73, 84, 117, 123, 153 General 53, 59, 67–8 Optimal form 112–14, 184–5 Sine waveform 134–59 Using the IDFT 249

344

Index

Phase domain processing Definition 110, 127–8 High speed phase accumulators 280–3 Noise shaping 127 Computing the IDFT 249–50 Piecewise-continuous waveshaping 233–6 Pipelining Block 268–73 Sample 268–9 Latency 30, 76, 78, 81, 257, 268–9, 281, 289, 301 Throughput enhancement 257, 268–9 Phase-locked loop (PLL) 24 PLL testing example 45–7 Pole distribution see recursive oscillators Polynomial interpolation see phase interpolation Polyphase signals 126 Positive frequency 111 Processing overhead 88–9 Pseudo-random sequence 42, 141–3, 187, 318 Quadrant symmetry 134 Quadrature phase 101, 125–6 Quadrature up-conversion 44 Quantisation, see amplitude quantisation Quasi-periodic signal 8 R-2R DAC see DAC Reactive oscillators see analogue oscillators Reconstruction filter 6, 27–8, 31, 40–1, 54, 307–8, 311, 322 Recursive oscillators Amplitude instability 100, 105, 107 Coupled-form 99–101 Direct-form 93–9 Frequency control 102, 105–7 General properties 91–3 Initial conditions 102–4 Modified coupled-form 101 Phase continuity 90, 100–4 Quantisation effects 101, 104–6 Waveguide-form 101–2 Relaxation oscillator see analogue oscillators Rotation matrix see recursive oscillators Sample frequency 17, 25, 30, 51, 58–9, 61, 64–5, 67 Sample pipelining see pipelining Sample rate see sample frequency Sawtooth wave 6–7, 13, 31, 36

Settling time see DAC settling time Spurious-free dynamic range (SFDR) 28, 317–18, 321 Signal Definition 14–15 Emulation 41–3 Specification 14–17 Sinc function 29, 51, 73, 114, 169, 226, 322 Sine wavetable 61, 119, 152 Signal-to-noise ratio (SNR) 10, 43, 46, 55, 83–4 Spectrum synthesis, see band- spectrum synthesis Square and pulse waveforms 36, 181, 212, 214, 337–8 State variable analogue oscillator see analogue oscillators State variables, see recursive oscillators Stop-band see filter Stop-band suppression see filter Symmetry see quadrant symmetry Tabulation see wavetable Taylor series 129, 286 Time division multiplexing (TDM) 45, 257–8 Transition region/band see filter response Triangle wave 31, 36, 205, 211–12 Trigonometric identity phase–amplitude mapping 109, 125, 148–52 Unit delay 65, 91, 268 Unit-circle 17, 94, 98–100, 105 Unwrapped phase 12, 53, 69 Up-conversion 41, 43–4 Voltage-controlled oscillator (VCO) see analogue oscillators Vector memory Architectures 277–80 Definition 266 Interpolated 285, 289–96 Voltage to frequency convertor (VFC) see analogue oscillators Voltage-controlled function generator see analogue oscillators Waveform function 12–14, 59–63 Waveform specification see arbitrary waveform Waveguide-form see recursive oscillators Wavetable

Index

Addressing 88, 114–22 Amplitude quantisation 61 Concept 14, 49 Definition 55–6 Fill time 58–9, 277 Length 58–60 Phase–amplitude space 173

Wien-bridge oscillator see analogue oscillators Window function 169, 177 Wrapped phase 12, 53, 68, 70 z-domain 100 z-transform 17, 93, 96

345

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