Ecad And Vlsi Lab Manual 5l3x21
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Department Of ECE JYOTHISHMATHI INSTITUTE OF TECHNOLOGY & SCIENCE (Approved by A.I.C.T.E & d to JNTU, Hyderabad) NUSTULAPUR, KARIMNAGAR – 505481, ANDHRA PRADESH
Department of Electronics and Communication Engineering LAB MANUAL BASIC SIMULATION LAB- II B.Tech(ECE) I Sem Prepared by : A. Sabitha
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Department Of ECE HOD E-CAD AND VLSI LAB : List of Experiments Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate-level design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects ( temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitics and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS) E-CAD programs: Programming can be done using any complier. Down load the programs on FPGA/LD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools. 1. HDL code to realize all the logic gates 2. Design of 2-to-4 decoder 3. Design of 8-to-3 encoder (without and with parity) 4. Design of 8-to-1 multiplexer 5. Design of 4 bit binary to gray converter 6. Design of Multiplexer/ Demultiplexer, comparator 7. Design of Full adder using 3 modeling styles 8. Design of flip flops: SR, D, JK, T 9. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter 10. Finite State Machine Design
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Department Of ECE
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Department Of ECE VLSI programs: 1. Introduction to layout design rules 2. Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following: Basic logic gates -CMOS inverter -CMOS NOR/ NAND gates -CMOS XOR and MUX gates -CMOS 1-bit full adder -Static / Dynamic logic circuit ( cell) -Latch - transistor 3. Layout of any combinational circuit (complex CMOS logic gate)- Learning about data paths 4. Introduction to SPICE simulation and coding of NMOS/CMOS circuit 5. SPICE simulation of basic analog circuits: Inverter / Differential amplifier 6. Analog Circuit simulation (AC analysis) – CS & CD amplifier 7. System level design using PLL
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Department Of ECE EXPERIMENT -1 Simulation using all the modeling styles and Synthesis of all the logic gates usingVerilog HDL --------------------------------------------------------------------------------------------------------------------Aim: 1. Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural modeling style in Verilog using a Test bench. 2. Synthesize each one of them on two different EDA tools. Apparatus required: Electronics Design Automation Tools used: i) Xilinx Spartan 3E FPGA +LD Board ii) Model Sim simulation tool or Xilinx ISE Simulator tool iii) Xilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow fromSimulation to Implementation to onto FPGA). v) JTAG cable vi) Adator 5v/4A Boolean equations: And Gate:Y = (A.B) Or Gate: Y = (A + B) Nand Gate: Y = (A.B)’ Nor Gate: Y = (A+B)’ Xor Gate: Y = A.B’ + A’.B Xnor Gate: Y = A.B + A’.B’ JITS Page 5
Department Of ECE
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Department Of ECE Block diagram:
Verilog program for AND gate: // And Gate (In Dataflow, behavioral Modeling): Module andg(a,b,c); input a,b; output c; assign c = a & b; endmodule //behavioural modeling Module andg1(a,b,c); input a,b; always(a,b) begin if (a==1’b0 or b == 1’b0) c = 1’b0; JITS Page 7
Department Of ECE else if (a==1’b0 or b == 1’b1) c = 1’b0; else if (a==1’b1 or b == 1’b0) c = 1’b0; else if (a==1’b1 or b == 1’b1) c = 1’b1; endendmodule Verilog program for OR gate: //Or gate(Dataflow, behavioral modeling): Module org (a,b,c); input a,b; output c; assign c = a | b; endmodule Verilog program for nand gate: // Nand Gate (In Dataflow modeling): Module nandg (a,b,c); input a,b; output c; assign c = ~(a & b); endmodule Verilog program for NOR gate: // Nor Gate (In Dataflow modeling): Module norg (a,b,c); input a,b; JITS Page 8
Department Of ECE output c; assign c = ~(a | b); endmodule
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Department Of ECE Verilog program for XOR gate: Xor gate(In Dataflow modeling): Module xorg (a,b,c); input a,b; output c; assign c = a ^ b; endmodule (or) Module xorg2 (a,b,c); input a,b; output c; assign c = (~a & b) | (a & ~b); endmodule Verilog program for XNOR gate: //Xnor Gate (In Dataflow modeling): Module xnorg (a,b,c); input a,b; output c; assign c = ~(a ^ b); endmodule module notgate (a,b); input a; output b; assign b = ~ (a); endmodule
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Department Of ECE VHDL PROGRAM FOR ALL LOGIC GATES: library ieee; use ieee.std_logic_1164.all; entity digital_gates is port( x: in std_logic; y: in std_logic; sel:in std_logic_vector(1 downto 0); F: out std_logic); end digital_gates; architecture behav1 of digital_gates is begin process(x, y, sel) begin if (sel = "00") then F <= x and y; elsif (sel = "01") then F <= x or y; elsif (sel = "10") then F <= x nand y; elsif (sel = "11") then F <= x nor y; else F <= '0'; end if; end process; end behav1;
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Department Of ECE Test Bench: programmable digital gates library ieee; use ieee.std_logic_1164.all; entity tb_digital_gates is end tb_digital_gates; architecture behav1 of tb_digital_gates is component digital_gates is port( x: in std_logic; y: in std_logic; sel:in std_logic_vector(1 downto 0); F: out std_logic ); end component; signal x,y,F:std_logic; signal sel:std_logic_vector(1 downto 0); begin U1: digital_gates port map(x,y, sel,F); process begin x <= '0'; wait for 10 ns; x <= '1'; wait for 20 ns; end process; process begin y <= '0';
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Department Of ECE wait for 20 ns; y <= '1'; wait for 30 ns; end process; process begin sel <= "00","01" after 20 ns,"10" after 40 ns,"11" after 80 ns; wait for 120 ns; end process; end behav1;
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Department Of ECE EXPERIMENT -2 Design of decoder usingVerilog HDL --------------------------------------------------------------------------------------------------------------------Aim: 1. Perform Zero Delay Simulation of decodere in Verilog using a Test bench. 2. Synthesize each one of them on two different EDA tools. Apparatus required: Electronics Design Automation Tools used: i) Xilinx Spartan 3E FPGA +LD Board ii) Model Sim simulation tool or Xilinx ISE Simulator tool iii) Xilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow fromSimulation to Implementation to onto FPGA). v) JTAG cable vi) Adator 5v/4A Block diagram:
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Department Of ECE Verilog program: module decoder(a, y); input [1:0] a; output [3:0] y; reg [3:0] y; always @ (a) case(a) 2’b00: y<= 4’b1110; 2’b01: y<= 4’b1101; 2’b10: y<= 4’b1011; 2’b11: y<= 4’b0111; end case; endmodule ******************************************** //decoder using case statement module dec2to4(W, Y, En); input [1:0] W; input En; output [0:3] Y; reg [0:3] Y; always @(*) case ({en,W}) 3’b100: Y = 4’b1000; 3’b101: Y = 4’b0100; 3’b110: Y = 4’b0010; 3’b111: Y = 4’b0001; default: Y = 4’b0000; endcase JITS Page 17
Department Of ECE endmodule **************************************************** module decoder_2to4(Y3, Y2, Y1, Y0, A, B, en); output Y3, Y2, Y1, Y0; input A, B; input en; reg Y3, Y2, Y1, Y0; always @(A or B or en) begin if (en == 1'b1) case ( {A,B} ) 2'b00: {Y3,Y2,Y1,Y0} = 4'b1110; 2'b01: {Y3,Y2,Y1,Y0} = 4'b1101; 2'b10: {Y3,Y2,Y1,Y0} = 4'b1011; 2'b11: {Y3,Y2,Y1,Y0} = 4'b0111; default: {Y3,Y2,Y1,Y0} = 4'bxxxx; endcase if (en == 0) {Y3,Y2,Y1,Y0} = 4'b1111; end endmodule //***************test bench******************** module Test_decoder_2to4; wire Y3, Y2, Y1, Y0; reg A, B; reg en; // Instantiate the Decoder (named DUT {device under test}) JITS Page 18
Department Of ECE decoder_2to4 DUT(Y3, Y2, Y1, Y0, A, B, en); initial begin $timeformat(-9, 1, " ns", 6); #1; A = 1'b0; // time = 0 B = 1'b0; en = 1'b0; #9; en = 1'b1; // time = 10 #10; A = 1'b0; B = 1'b1; // time = 20 #10; A = 1'b1; B = 1'b0; // time = 30 #10; A = 1'b1; B = 1'b1; // time = 40 #5; en = 1'b0; // time = 45 #5; end always @(A or B or en) #1 $display("t=%t",$time," en=%b",en," A=%b",A," B=%b",B," Y=%b%b%b %b",Y3,Y2,Y1,Y0); endmodule ****************************************** module decode24(q, a); output[3:0] q; JITS Page 19
Department Of ECE input[1:0] a; assign q = (4’b0001) << a; endmodule ********************************** module dec2to4(W, Y, En); input [1:0] W; input En; output [0:3] Y; reg [0:3] Y; always @(*) case ({en,W}) 3’b100: Y = 4’b1000; 3’b101: Y = 4’b0100; 3’b110: Y = 4’b0010; 3’b111: Y = 4’b0001; default: Y = 4’b0000; endcase endmodule ***************************************************************************** 3 TO 8 DECODER ***************************************************************************** module decoder(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,A,B,C); output Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7; input A,B,C; wire s0,s1,s2; not (s0,A); not (s1,B); not (s2,C); JITS Page 20
Department Of ECE and (Q0,s0,s1,s2); and (Q1,A,s1,s2); and (Q2,s0,B,s2); and (Q3,A,B,s2); and (Q4,s0,s1,C); and (Q5,A,s1,C); and (Q6,s0,B,C); and (Q7,A,B,C); endmodule //*****TESTBENCH*******// module stimulus; // Set up variables reg A, B, C; // Instantiate the decoder. decoder FF(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,A,B,C); // Setup the monitoring for the signal values initial begin $monitor($time,"C=%b, =%b,A=%b ,Q=%b%b%b%b%b%b%b%b\n", C,B,A,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7); end // Stimulate inputs Initial begin C=1'b0; B =1'b0; A = 1'b0; #10 C =1'b0; B = 1'b0; A= 1'b1; #10 C =1'b0; B = 1'b1; A= 1'b0; #10 C =1'b0; B = 1'b1; A= 1'b1; #10 C =1'b1; B = 1'b0; A= 1'b0; JITS Page 21
Department Of ECE #10 C =1'b1; B = 1'b0; A= 1'b1; #10 C =1'b1; B = 1'b1; A= 1'b0; #10 C =1'b1; B = 1'b1; A= 1'b1; end endmodule ********************************************************** module decoder_3to8(Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0, A, B, C, en); output Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0; input A, B, C; input en; assign {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} = ( {en,A,B,C} == 4'b1000) ? 8'b1111_1110 : ( {en,A,B,C} == 4'b1001) ? 8'b1111_1101 : ( {en,A,B,C} == 4'b1010) ? 8'b1111_1011 : ( {en,A,B,C} == 4'b1011) ? 8'b1111_0111 : ( {en,A,B,C} == 4'b1100) ? 8'b1110_1111 : ( {en,A,B,C} == 4'b1101) ? 8'b1101_1111 : ( {en,A,B,C} == 4'b1110) ? 8'b1011_1111 : ( {en,A,B,C} == 4'b1111) ? 8'b0111_1111 : 8'b1111_1111; Endmodule //TESTBENCH module Test_decoder_3to8; wire Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0; reg A, B, C; reg en; // Instantiate the Decoder (named DUT {device under test}) decoder_3to8 DUT(Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0, A, B, C, en); initial begin JITS Page 22
Department Of ECE $timeformat(-9, 1, " ns", 6); #1; A = 1'b0; // time = 0 B = 1'b0; C = 1'b0; en = 1'b0; #9; en = 1'b1; // time = 10 #10; A = 1'b0; B = 1'b1; C = 1'b0; // time = 20 #10; A = 1'b1; B = 1'b0; C = 1'b0; // time = 30 #10; A = 1'b1; B = 1'b1; C = 1'b0; // time = 40 #5; en = 1'b0; // time = 45 #5; end always @(A or B or C or en) $display("t=%t en=%b ABC=%b%b%b Y=%b%b%b%b%b%b%b%b", $time,en,A,B,C,Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0); Endmodule ******************************************************** JITS Page 23
Department Of ECE module decoder (in,out); input [2:0] in; output [7:0] out; wire [7:0] out; assign out = (in == 3'b000 ) ? 8'b0000_0001 : (in == 3'b001 ) ? 8'b0000_0010 : (in == 3'b010 ) ? 8'b0000_0100 : (in == 3'b011 ) ? 8'b0000_1000 : (in == 3'b100 ) ? 8'b0001_0000 : (in == 3'b101 ) ? 8'b0010_0000 : (in == 3'b110 ) ? 8'b0100_0000 : (in == 3'b111 ) ? 8'b1000_0000 : 8'h00; endmodule
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Department Of ECE ******************************************************** module decoder_always (in,out); input [2:0] in; output [7:0] out; reg [7:0] out; always @ (in) begin out = 0; case (in) 3'b001 : out = 8'b0000_0001; 3'b010 : out = 8'b0000_0010; 3'b011 : out = 8'b0000_0100; 3'b100 : out = 8'b0000_1000; 3'b101 : out = 8'b0001_0000; 3'b110 : out = 8'b0100_0000; 3'b111 : out = 8'b1000_0000; endcase end endmodule //USING FOR LOOP module Decode3To8For(yOut, aIn, enable); output [7:0]yOut; input [2:0]aIn; input enable; reg [7:0] yOut; integer k; always@(aIn or enable) begin JITS Page 25
Department Of ECE if(enable == 1) begin for(k=0;k<8;k=k+1)
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Department Of ECE begin if(aIn == k) yOut[k] = 0; else yOut[k] = 1; end end end endmodule ***************************************************************************
BCD decoder **************************************************************** This circuit has four binary inputs and ten binary outputs. The ith output is asserted if the binary inputs are the binary number i, where 0 ≤ i ≤ 9. The inputs will never be a number greater than 9 (or if they are, we don’t care what the output is). module (X, Y); input [3:0] X; output [0:9] Y; reg [0:9] Y; always @(*) begin Y = 0; case (X) 0: Y[0] = 1; 1: Y[1] = 1; 2: Y[2] = 1; 3: Y[3] = 1; 4: Y[4] = 1; 5: Y[5] = 1; JITS Page 27
Department Of ECE 6: Y[6] = 1; 7: Y[7] = 1; 8: Y[8] = 1; 9: Y[9] = 1; default: Y = ’bx; endcase end endmodule
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Department Of ECE EXPERIMENT -3 Design of 8-to-3 encoder (without and with parity) usingVerilog HDL --------------------------------------------------------------------------------------------------------------------Aim: 1. Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural modeling style in Verilog using a Test bench. 2. Synthesize each one of them on two different EDA tools. Apparatus required: Electronics Design Automation Tools used: i) Xilinx Spartan 3E FPGA +LD Board ii) Model Sim simulation tool or Xilinx ISE Simulator toolXilinx XST iii) Synthesis tool or LeonardoSpectrum Synthesis Tool iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow fromSimulation to Implementation to onto FPGA). v) JTAG cable vi) Adator 5v/4A THEORY: An encoder is a digital circuit which performs the inverse of decoder.An encoder has 2^N input lines and N output lines.In encoder the output lines genrate the binary code corresponding to input value.The decimal to bcd encoder usually has 10 input lines and 4 ouput lines.The decoder decimal data as an input for decoder an encoded bcd ouput is available at 4 output lines.
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Y2 = w7 + w6 + w5 + w4 Y1 = w7 + w6 + w3 + w2 Y0 = w7 + w5 + w3 + w1 Verilog program for 8x3 encoder: module encoder (din, dout); input [7:0] din; output [2:0] dout; reg [2:0] dout; always @(din) begin if (din ==8'b00000001) dout=3'b000; else if (din==8'b00000010) dout=3'b001; else if (din==8'b00000100) dout=3'b010; else if (din==8'b00001000) dout=3'b011; else if (din==8'b00010000) dout=3'b100; else if (din ==8'b00100000) dout=3'b101; else if (din==8'b01000000) dout=3'b110; else if (din==8'b10000000) dout=3'b111; else dout=3'bX; end endmodule
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Department Of ECE Priority Encoders -A priority encoder has n inputs and ⎡log2n⎤ outputs. -The output signals are a binary number such that its valueis the highest index value of all the inputs that are 1. Example: 4-to-2 priority encoder: y1 = w3’•w2 + w3 y2 = w3’•w2’•w1 + w3 z = w0 + w1 + w2 + w3 Priority encoder is a special type of encoder in which multiple bits at the input can be asserted. The response at the output is however defined by the priority rule, defined previously. Priority encoders have vast application in different client-server systems. In client-server systems decision is made to grant a service based on the priority of any specific client. Here is a verilog code for an 8:3 priority encoder. It grants the highest priority to the "most left sided bit in the input word". For example in data word "00010101" the highest priority is carried by the most left sided one, appearing at the fourth (counting from left side). So all the other bits that come next to it will be discarded or in other words will not be taken into . Verilog implementation has been done using "casex" statement. an 8-bit priority encoder. This circuit basically converts a one-hot encoding into a binary representation. If input n is active, all lower inputs (n-1 .. 0) are ignored. Please read the description of the 4:2 encoder for an explanation.
module priority_encoder (code, valid_data, data); JITS Page 31
Department Of ECE output [2:0] code; output valid data; input [7:0] data; reg [2:0] code; assign valid_data= |data; // Use of "reduction or" operator always @ (data) begin casex (data) 8'b1xxxxxxx : code=7; 8'b01xxxxxx : code=6; 8'b001xxxxx : code=5 8'b0001xxxx : code=4; 8'b00001xxx : code=3; 8'b000001xx : code=2; 8'b0000001x : code=1; 8'b00000001 : code=0; dafault : code=3'bx; endcase endmodule Verilog program for 4 x2 priority encoder module priority (W, Y, z); input [3:0] W; output [1:0] Y; output z; reg [1:0] Y; reg z; always @(*) begin z = 1; JITS Page 32
Department Of ECE casex (W) 4’b1xxx: Y = 3; 4’b01xx: Y = 2; 4’b001x: Y = 1; 4’b0001: Y = 0; default: begin z=0; Y = 2’bxx; end endcase end endmodule Verilog code for a 3-bit 1-of-9 Priority Encoder: module priority (sel, code); input [7:0] sel; output [2:0] code; reg [2:0] code; always @(sel) begin if (sel[0]) code = 3’b000; else if (sel[1]) code = 3’b001; else if (sel[2]) code = 3’b010; else if (sel[3]) code = 3’b011; JITS Page 33
Department Of ECE else if (sel[4]) code = 3’b100; else if (sel[5]) code = 3’b101; else if (sel[6]) code = 3’b110; else if (sel[7]) code = 3’b111; else code = 3’bxxx; end endmodule Pri-Encoder - Using if-else Statement ------------------------------------------------module pri_encoder_using_if ( binary_out , // 4 bit binary output encoder_in , // 16-bit input enable // Enable for the encoder ); output [3:0] binary_out ; input enable ; input [15:0] encoder_in ; reg [3:0] binary_out ; always @ (enable or encoder_in) begin binary_out = 0; if (enable) begin JITS Page 34
Department Of ECE if (encoder_in[0] == 1) begin binary_out = 1; end else if (encoder_in[1] == 1) begin binary_out = 2; end else if (encoder_in[2] == 1) begin binary_out = 3; end else if (encoder_in[3] == 1) begin binary_out = 4; end else if (encoder_in[4] == 1) begin binary_out = 5; end else if (encoder_in[5] == 1) begin binary_out = 6; end else if (encoder_in[6] == 1) begin binary_out = 7; end else if (encoder_in[7] == 1) begin binary_out = 8; end else if (encoder_in[8] == 1) begin binary_out = 9; end else if (encoder_in[9] == 1) begin binary_out = 10; end else if (encoder_in[10] == 1) begin binary_out = 11; end else if (encoder_in[11] == 1) begin binary_out = 12; end else if (encoder_in[12] == 1) begin binary_out = 13; end else if (encoder_in[13] == 1) begin binary_out = 14; JITS Page 35
Department Of ECE end else if (encoder_in[14] == 1) begin binary_out = 15; end end end endmodule
Encoder - Using assign Statement module pri_encoder_using_assign ( binary_out , // 4 bit binary output encoder_in , // 16-bit input enable // Enable for the encoder ); output [3:0] binary_out ; input enable ; input [15:0] encoder_in ; wire [3:0] binary_out ; assign binary_out = ( ! enable) ? 0 : ( (encoder_in[0]) ? 0 : (encoder_in[1]) ? 1 : (encoder_in[2]) ? 2 : (encoder_in[3]) ? 3 : (encoder_in[4]) ? 4 : (encoder_in[5]) ? 5 : (encoder_in[6]) ? 6 : (encoder_in[7]) ? 7 : (encoder_in[8]) ? 8 : (encoder_in[9]) ? 9 : JITS Page 36
Department Of ECE (encoder_in[10]) ? 10 : (encoder_in[11]) ? 11 : (encoder_in[12]) ? 12 : (encoder_in[13]) ? 13 : (encoder_in[14]) ? 14 : 15); endmodule
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Department Of ECE EXPERIMENT -4 Design of multiplexer usingVerilog HDL --------------------------------------------------------------------------------------------------------------------Aim: 3. Perform Zero Delay Simulation of multiplexerin Verilog using a Test bench. 4. Synthesize each one of them on two different EDA tools. Apparatus required: Electronics Design Automation Tools used: vii) Xilinx Spartan 3E FPGA +LD Board viii) Model Sim simulation tool or Xilinx ISE Simulator toolXilinx XST ix) Synthesis tool or LeonardoSpectrum Synthesis Tool x) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow fromSimulation to Implementation to onto FPGA). xi) JTAG cable xii) Adator 5v/4A Block Diagram:
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Department Of ECE
Verilog program for 2x1 multiplexer:
module mux2to1 (w0, w1, s, f); input w0, w1, s; JITS Page 39
Department Of ECE output f; assign f = s ? w1: w0; endmodule ***************************** module mux21(q, sel, a, b); input sel, a, b; output q; assign q = (~sel & a) | (sel & b); endmodule ****************************** module mux21(q, sel, a, b); input sel, a, b; output q; assign q = sel ? b : a; endmodule ************************* module mux21(q, sel, a, b); wire[3:0] a, b, q; wire sel; assign q = sel ? b: a; endmodule ***************************** module mux_2to1(Y, A, B, sel); output [15:0] Y; input [15:0] A, B; input sel; reg [15:0] Y; always @(A or B or sel) JITS Page 40
Department Of ECE if (sel == 1'b0) Y = A; else Y = B; endmodule ********************************** module mux2(out,i0,i1,s0); output out; input i0,i1,s0; //internal wires wire sbar,y1,y2; not g1(sbar,s0); and g2(y1,i0,sbar); and g3(y2,i1,s0); or g4(out,y1,y2); endmodule //test bench module text_mux2; reg i0,i1; reg s0; wire out; mux2 mymux(out,i0,i1,s0); initial $monitor($time,"s0=%b,i0=%b,i1=%b,out=%b\n",s0,i0,i1,out); initial begin s0=0;i0=0;i1=0; #50 s0=0;i0=0;i1=1; JITS Page 41
Department Of ECE #50 s0=1;i0=0;i1=1; #50 s0=0;i0=1;i1=0; #50 s0=1;i0=1;i1=0; end endmodule ************************************************************ module mux21(q, sel, a, b); input sel; input[15:0] a, b; output[15:0] q; assign q = sel ? b : a; endmodule ******************* module mux21n(q, sel, a, b); parameter WID = 16; input sel; input[WID-1:0] a, b; output[WID-1:0] q; assign q = sel ? b : a; endmodule *****************************************************************
4 X 1 MULTIPLEXER ******************************************************* module mux4to1 (w0, w1, w2, w3, S, f); input w0, w1, w2, w3; input [1:0] S; output f; assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0); JITS Page 42
Department Of ECE endmodule ******************************** module mux4to1 (W, S, f); input [0:3] W; input [1:0] S; output f; reg f; always @(*) if (S == 0) f = W[0]; else if (S == 1) f = W[1]; else if (S == 2) f = W[2]; else if (S == 3) f = W[3]; endmodule ******************************************** module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); // Port declarations from the I/O diagram output out; input i0, i1, i2, i3; input s1, s0; // Internal wire declarations wire s1n, s0n; wire y0, y1, y2, y3; // Gate instantiations not (s1n, s1); JITS Page 43
Department Of ECE not (s0n, s0); and (y0, i0, s1n, s0n); and (y1, i1, s1n, s0); and (y2, i2, s1, s0n); and (y3, i3, s1, s0); or (out, y0, y1, y2, y3); endmodule /////TEST BENCH module stimulus; // Declare variables to be connected to inputs reg IN0, IN1, IN2, IN3; reg S1, S0; // Declare output wire wire OUTPUT; // Instantiate the multiplexer mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0); // Stimulate the inputs initial begin IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0; #1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3); S1 = 0; S0 = 0; #50 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); S1 = 0; S0 = 1; #50 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); S1 = 1; S0 = 0; #50 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); S1 = 1; S0 = 1; JITS Page 44
Department Of ECE #50 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); end endmodule **************************************** module mux41(q, sel, a, b, c, d); parameter WID=16; input[1:0] sel; input[WID-1:0] a, b, c, d; output[WID-1:0] q; assign q = (sel==2'b00) ? a:(sel==1) ? b:(sel==2’b10) ? c:d; endmodule **************************************** module mux41n(q, sel, a, b, c, d); parameter WID=16; input[1:0] sel; input[WID-1:0] a, b, c, d; output[WID-1:0] q; wire[WID-1:0] tmp1, tmp2; mux21n #(WID) M0(tmp1, sel[0], a, b); mux21n #(WID) M1(tmp2, sel[0], c, d); mux21n #(WID) M2(q, sel[1], tmp1, tmp2); endmodule module mux_4to1(Y, A, B, C, D, sel); output [15:0] Y; input [15:0] A, B, C, D; input [1:0] sel; reg [15:0] Y; always @(A or B or C or D or sel) JITS Page 45
Department Of ECE case ( sel ) 2'b00: Y = A; 2'b01: Y = B; 2'b10: Y = C; 2'b11: Y = D; default: Y = 16'hxxxx; endcase endmodule ////////TEST BENCH module Test_mux_4to1; wire [15:0] MuxOut; //use wire data type for outputs from instantiated module reg [15:0] A, B, C, D; //use reg data type for all inputs reg [1:0] sel; // to the instantiated module reg clk; //to be used for timing of WHEN to change input values // Instantiate the MUX (named DUT {device under test}) mux_4to1 DUT(MuxOut, A, B, C, D, sel); //This block generates a clock pulse with a 20 ns period always #10 clk = ~clk; //This initial block will provide values for the inputs // of the mux so that both inputs/outputs can be displayed initial begin $timeformat(-9, 1, " ns", 6); clk = 1’b0; // time = 0 A = 16'hAAAA; B = 16'h5555; C = 16'h00FF; D = 16'hFF00; sel = 2'b00; @(negedge clk) //will wait for next negative edge of the clock (t=20) A = 16'h0000; @(negedge clk) //will wait for next negative edge of the clock (t=40) JITS Page 46
Department Of ECE sel = 2'b01; @(negedge clk) //will wait for next negative edge of the clock (t=60) B = 16'hFFFF; @(negedge clk) //will wait for next negative edge of the clock (t=80) sel = 2'b10; A = 16'hA5A5; @(negedge clk) //will wait for next negative edge of the clock (t=100) sel = 2'b00; @(negedge clk) //will wait for next negative edge of the clock (t=120) $finish; // to shut down the simulation end //initial // this block is sensitive to changes on ANY of the inputs and will // then display both the inputs and corresponding output always @(A or B or C or D or sel) #1 $display("At t=%t / sel=%b A=%h B=%h C=%h D=%h / MuxOut=%h", $time, sel, A, B, C, D, MuxOut); endmodule
****************************************************************** 16 x 1 MULTIPLEXER ***************************************************************** module mux16to1 (W, S, f, M); input [0:15] W; input [3:0] S; output f; output [3:0] M; wire [0:3] M; mux4to1 Mux1 (W[0:3], S[1:0], M[0]); mux4to1 Mux2 (W[4:7], S[1:0], M[1]); JITS Page 47
Department Of ECE mux4to1 Mux3 (W[8:11], S[1:0], M[2]); mux4to1 Mux4 (W[12:15], S[1:0], M[3]); mux4to1 Mux5 (M[0:3], S[3:2], f); endmodule ********************************************* module mux_16to1(Y, In, sel); output Y; input [15:0] In; input [3:0] sel; wire lo8, hi8, out1; // Instantiate the 8-to-1 muxes and the 2-to-1 mux mux_8to1 mux_lo (lo8, In[7:0], sel[2:0]); mux_8to1 mux_hi (hi8, In[15:8], sel[2:0]); mux_2to1 mux_out (out1, lo8, hi8, sel[3]); // equate the wire out of the 2-to-1 with // the actual output (Y) of the 16-to-1 mux assign Y = out1; endmodule module Test_mux_16to1; wire MuxOut; reg [15:0] In; reg [3:0] sel; // Instantiate the MUX (named DUT {device under test}) mux_16to1 DUT(MuxOut, In, sel); initial begin $timeformat(-9, 1, " ns", 6); $monitor("At t=%t sel=%b In=%b_%b MuxOut=%b",$time,sel,In[15:8],In[7:0],MuxOut); In = 16'b1100_0011_1011_0100; // time = 0 JITS Page 48
Department Of ECE sel = 4'b0000; #10; sel = 4'b0001; // time = 10 #10; sel = 4'b0010; // time = 20 #10; sel = 4'b0011; // time = 30 #10; In = 16'b1100_0011_1011_1111; sel = 4'b0100; // time = 40 #10; sel = 4'b0101; // time = 50 #10; sel = 4'b0110; // time = 60 #10; sel = 4'b0111; // time = 70 #10; In = 16'b1100_0011_1111_1111; // time = 80 sel = 4'b1000; #10; sel = 4'b1001; // time = 90 #10; sel = 4'b1010; // time = 100 #10; sel = 4'b1011; // time = 110 #10; In = 16'b1100_1111_1111_1111; sel = 4'b1100; // time = 120 JITS Page 49
Department Of ECE #10; sel = 4'b1101; // time = 130 #10; sel = 4'b1110; // time = 140 #10; sel = 4'b1111; // time = 150 #5; $finish; end endmodule
Demultiplexor A demultiplexor is the converse of a multiplexor. It takes one input and directs it to any of N inputs, based on the number specified in the select lines. It could be captured either using procedural code or continuous assignment. Both of the following statements describe identical behavior. VERILOG PROGRAM: module (in1, sel, out2); input [1:0] in1; input [2:0] sel; output [13:0] out2; reg [15:0] out2; integer I; always@(in1 or sel) begin out2 = 14’h0; /* default = 00 */ for (I=0; I<=7; I=I+1) if (I == sel) begin JITS Page 50
Department Of ECE out2[I] = in1[0]; out2[I+1] = in1[1]; end end endmodule /*----------------------------*/ module (in1, sel, out2); input [1:0] in1; input [2:0] sel; output [15:0] out2; reg [7:0] select; /* address decoder */ always@(sel) case (sel) 3’b000 : select = 8’b00000001; 3’b001 : select = 8’b00000010; 3’b010 : select = 8’b00000100; 3’b011 : select = 8’b00001000; 3’b100 : select = 8’b00010000; 3’b101 : select = 8’b00100000; 3’b110 : select = 8’b01000000; 3’b111 : select = 8’b10000000; endcase assign out2[1:0] = in1 & select[0]; assign out2[3:2] = in1 & select[1]; assign out2[5:4] = in1 & select[2]; assign out2[7:6] = in1 & select[3]; assign out2[9:8] = in1 & select[4]; JITS Page 51
Department Of ECE assign out2[11:10] = in1 & select[5]; assign out2[13:12] = in1 & select[6]; assign out2[15:14] = in1 & select[7]; endmodule VERilog code for 1-bit fill adder: //define a 1bit fulladder module fulladd(sum, c_out, a, b, c_in); output sum, c_out; input a, b, c_in; wire s1, c1, c2; xor (s1, a, b); and (c1, a, b); xor (sum, s1, c_in); and (c2, s1, c_in); or (c_out, c2, c1); endmodule module stimulus; //declare variables to be connected reg A, B; reg C_IN; wire SUM; wire C_OUT; // Instantiate the 4-bit full adder. call it FA1_4 fulladd FA1(SUM, C_OUT, A, B, C_IN); // Setup the monitoring for the signal values initial begin JITS Page 52
Department Of ECE $monitor($time," A= %b, B=%b, C_IN= %b, C_OUT=%b,SUM= %b\n",A,B,C_IN,C_OUT,SUM); end initial begin A = 4'd0; B = 4'd0; C_IN = 1'b0; #50 A = 4'b0; B = 4'b0;C_IN=1'b1; #50 A = 4'b0; B = 4'b1;C_IN=1'b0; #50 A = 4'b0; B = 4'b1;C_IN=1'b1; #50 A = 4'b1; B = 4'b0;C_IN=1'b0; #50 A = 4'b1; B = 4'b0;C_IN=1'b1; #50 A = 4'b1; B = 4'b1;C_IN=1'b1; end endmodule //define a 4-bit full adder module fulladd4(sum, c_out, a, b, c_in); //i/o port declaration output [3:0] sum; output c_out; input[3:0] a, b; input c_in; //internal net wire c1, c2, c3; fulladd fa0(sum[0], c1, a[0], b[0], c_in); fulladd fa1(sum[1], c2, a[1], b[1], c1); fulladd fa2(sum[2], c3, a[2], b[2], c2); fulladd fa3(sum[3], c_out, a[3], b[3], c3); endmodule JITS Page 53
Department Of ECE define the stimulus module module stimulus; //declare variables to be connected reg [3:0] A, B; reg C_IN; wire [3:0] SUM; wire C_OUT; fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN); verilog code for dff module dff(clk, d, q); input clk, d; output reg q; always @(posedge clk) q <= d; endmodule module DFFAsyncClr(D, clk, resetn, Q, presetn); input D, clk, resetn, presetn; output Q; reg Q; always@(posedge clk or negedge resetn or negedge presetn) if(!resetn) Q <= 0; else if(!presetn) Q <= 1; else Q <= D; endmodule module Reg32(Q, D, clk, reset_); JITS Page 54
Department Of ECE //********************************************************* output [31:0] Q; input [31:0] D; input clk, reset_; reg [31:0] Q; always @(posedge clk or negedge reset) if (!reset_) Q <= 32'b0; else Q <= D; Endmodule module Test_Reg1; //********************************************************* wire [31:0] OutReg; reg [31:0] Din; reg clk, reset_; // Instantiate Reg32 (named DUT {device under test}) Reg32 DUT(OutReg, Din, clk, reset_); initial begin $timeformat(-9, 1, " ns", 6); clk = 1’b0; reset_ = 1’b1; // deassert reset t=0 #3 reset_ = 1’b0; // assert reset t=3 #4 reset_ = 1’b1; // deassert reset t=7 @(negedge clk) //will wait for next negative edge of the clock (t=20) Din = 32'hAAAA5555; @(negedge clk) //will wait for next negative edge of the clock (t=40) Din = 32'h5F5F0A0A; JITS Page 55
Department Of ECE @(negedge clk) //will wait for next negative edge of the clock (t=60) Din = 32'hFEDCBA98; @(negedge clk) //will wait for next negative edge of the clock (t=80) reset_ = 1’b0; @(negedge clk) //will wait for next negative edge of the clock (t=100) reset_ = 1’b1; @(negedge clk) //will wait for next negative edge of the clock (t=120) Din = 32'h76543210; @(negedge clk) //will wait for next negative edge of the clock (t=140) $finish; // to kill the simulation end // This block generates a clock pulse with a 20 ns period. // Rising edges at 10, 30, 50, 70 .... Falling edges at 20, 40, 60, 80 .... always #10 clk = ~ clk; // this block is sensitive to changes on clk or reset and will // then display both the inputs and corresponding output always @(posedge clk or reset_) #1 $display("At t=%t / Din=%h OutReg=%h" , $time, Din, OutReg); Endmodule Verilog program for seven segment module SevSegCase(aIn, sOut); input [3:0]aIn; output [6:0]sOut; reg [6:0]sOut; always @(aIn) begin JITS Page 56
Department Of ECE case (aIn) // abcdefg 4'b0000:sOut = 7'b0000001; //0 4'b0001:sOut = 7'b1001111; //1 4'b0010:sOut = 7'b0010010; //2 4'b0011:sOut = 7'b0000110; //3 4'b0100:sOut = 7'b1001100; //4 4'b0101:sOut = 7'b0100100; //5 4'b0110:sOut = 7'b0100000; //6 4'b0111:sOut = 7'b0001111; //7 4'b1000:sOut = 7'b0000000; //8 4'b1001:sOut = 7'b0001100; //9 4'b1010:sOut = 7'b0001000; //A 4'b1011:sOut = 7'b1000010; //B 4'b1100:sOut = 7'b0000111; //C 4'b1101:sOut = 7'b0000001; //D 4'b1110:sOut = 7'b0110000; //E 4'b1111:sOut = 7'b0000110; //F endcase end endmodule jk ff:
module jkff(J, K, clk, Q); JITS Page 57
Department Of ECE input J, K, clk; output Q; reg Q; reg Qm; always @(posedge clk) if(J == 1 && K == 0) Qm <= 1; else if(J == 0 && K == 1) Qm <= 0; else if(J == 1 && K == 1) Qm <= ~Qm; // always @(negedge clk) Q <= Qm; endmodule
//n-bit parallel in/parallel out // with tri-state out. module RegnBit(dIn, dOut, clk, enable); JITS Page 58
Department Of ECE parameter n = 8; input [n-1:0]dIn; input clk, enable; output [n-1:0] dOut; reg [n-1:0] dOut; reg [n-1:0] state; always @(enable) begin if(enable) dOut = state; //data to out else dOut = n'bz; //tri-state out end always @(posedge clk) state <= dIn; endmodule //n-bit parallel in/parallel out // with tri-state out. module RegnBit(dIn, dOut, clk, enable); parameter n = 8; input [n-1:0]dIn; input clk, enable; output [n-1:0] dOut; reg [n-1:0] dOut; reg [n-1:0] state; always @(enable) begin if(enable) JITS Page 59
Department Of ECE dOut = state; //data to out else dOut = n'bz; //tri-state out end always @(posedge clk) state <= dIn; endmodule //n-bit parallel in/parallel out // with tri-state out. module RegnBit(dIn, dOut, clk, enable); parameter n = 8; input [n-1:0]dIn; input clk, enable; output [n-1:0] dOut; reg [n-1:0] dOut; reg [n-1:0] state; always @(enable) begin if(enable) dOut = state; //data to out else dOut = n'bz; //tri-state out end always @(posedge clk) state <= dIn; endmodule //n-bit parallel in/parallel out // with tri-state out. JITS Page 60
Department Of ECE module RegnBit(dIn, dOut, clk, enable); parameter n = 8; input [n-1:0]dIn; input clk, enable; output [n-1:0] dOut; reg [n-1:0] dOut; reg [n-1:0] state; always @(enable) begin if(enable) dOut = state; //data to out else dOut = n'bz; //tri-state out end always @(posedge clk) state <= dIn; endmodule //CntSeq.v //Sequence counter module CntSeq(clk, reset, state); parameter n = 4; input clk, reset; output [n-1:0]state; reg [n-1:0]state; // always @(posedge clk) if(reset) state = 0; else JITS Page 61
Department Of ECE begin case (state) 4'b0000:state = 4'b0001; //0 -> 1 4'b0001:state = 4'b0010; //1 -> 2 4'b0010:state = 4'b0100; //2 -> 4 4'b0100:state = 4'b1001; //4 -> 9 4'b1001:state = 4'b1010; //9 -> 10 4'b1010:state = 4'b0101; //10-> 5 4'b0101:state = 4'b0110; //5 -> 6 4'b0110:state = 4'b1000; //6 -> 8 4'b1000:state = 4'b0111; //8 -> 7 default:state = 4'b0000; endcase end endmodule Figure 14 A case statement is used to implement a sequence counter //ShiftMultiple //This file uses multiple modules for dual shift s // of differing lengths module ShiftMultiple(sIn, sOut, clk); input [2:0] sIn; input clk; output [2:0]sOut; Shiftn Shift4 (clk, sIn[0], sOut[0]); //defaults to n = 4 Shiftn Shift6(clk, sIn[1], sOut[1]); defparam Shift6.n = 6; //resets n to 6 Shiftn Shift12(clk, sIn[2], sOut[2]); JITS Page 62
Department Of ECE defparam Shift12.n = 12; //resets n to 12 endmodule // //Shiftn //n-bit shift serial in serial out module Shiftn(clk, sIn, sOut); parameter n = 4; //number of stages input sIn, clk; output sOut; reg sOut; reg [n-1:0]state; always @(posedge clk) // sIn -> [0|1|...|n-1] -> sOut begin sOut <= state[n-1]; state <= {state[n-2:0], sIn}; end endmodule module fundecode(aIn, yOut, enable); input [1:0] aIn; input enable; output [3:0]yOut; reg [3:0] yOut; // function [3:0]FindOutput; input [1:0]xIn; if(~xIn[1] && ~xIn[0]) FindOutput = 4'b0111; if(~xIn[1] && xIn[0]) FindOutput = 4'b1011; if(xIn[1] && ~xIn[0]) FindOutput = 4'b1101; JITS Page 63
Department Of ECE if(xIn[1] && xIn[0]) FindOutput = 4'b1110; endfunction // always@(aIn or enable) begin if(enable == 1) begin yOut = FindOutput(aIn); end else yOut = 4'b1111; end endmodule module taskdecode(aIn, yOut, enable); input [1:0] aIn; input enable; output [3:0]yOut; reg [3:0] yOut; // task FindOutput; input [1:0]xIn; output [3:0] tOut if(~xIn[1] && ~xIn[0]) tOut = 4'b0111; if(~xIn[1] && xIn[0]) tOut = 4'b1011; if(xIn[1] && ~xIn[0]) tOut = 4'b1101; if(xIn[1] && xIn[0]) tOut = 4'b1110; endtask // JITS Page 64
Department Of ECE always@(aIn or enable) begin if(enable == 1) begin FindOutput(aIn, yOut); end else yOut = 4'b1111; end endmodule module flif_flop (clk,reset, q, d); 2 input clk, reset, d; 3 output q; 4 reg q; 5 6 always @ (posedge clk ) 7 begin 8 if (reset == 1) begin 9 q <= 0; 10 end else begin 11 q <= d; 12 end 13 end 15 endmodule VHDL CODE FOR FULL AADDER DATAA FLOW: Full Adder A B C Ci S Co 00000 JITS Page 65
Department Of ECE EXXPRESSIONS: 00 110 01 010 B Ci S= =A 01 101 B)Ci + AB CO O = (A 10 010 10 101 11 001 11 111 Libraary IEEE; use IEEE.STD_LOOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; JITS Page 66
Department Of ECE entity fa1 is Port ( a,b,ci : in STD_LOGIC; s,,co : out STD_LOGIC); end fa1; architecture Behavioral of fa1 is begin s<=a xor b xor ci; co<=(a and b)or (b and ci)or (ci and a); end Behavioral; VHDL CODE FOR FULL ADDER BEHAVIORAL: : libraary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fa1 is Port ( a,b,ci : in STD_LOGIC; s,,co : out STDD_LOGIC); end fa1; archhitecture Behavioral of fa1 is begin process(a,b,ci) begin s<=a xor b xor ci; co<=(a and b)or (b and ci)or (ci and a); end process; JITS Page 67
Department Of ECE end Behavioral; VHDL CODE FOR FULL ADDER STRUCTURAL: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fa1 is Port ( a,b,cin : in STD_LOGIC; s,cout : out STD_LOGIC); end fa1; architecture struct of fa1 is component and21 port(a,b:in std_logic; ---components, entity and architecture c:out std_logic); --- must be declared separately end component; component xor21 port(a,b:in std_logic; ---components, entity and architecture --- must be declared separately c:out std_logic); end component; component or31 port(a,b:in std_logic; ---components, entity and architecture d:out std_logic); --- must be declared separately end component; signal s1,s2,s3:std_logic; begin u1:xor21 port map(a,b,s1); u2:xor21 port map(s1,cin,s); JITS Page 68
Department Of ECE u3:and21 port map(a,b,s2); u4:and21 port map(s1,cin,s3); u6:or31 port map(s2,s3,cout); end struct; VHDL CODE FOR MULTIPLEXER (8:1): INPUTS SELECTLINES O/P d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) s(2) s(1) s(0) f XX X X X X X 0 0 0 0 0 XXXXXXX10001 XXXXXX0X0010 XXXXXX1X0011 XXXXX0XX0100 XXXXX1XX0101 XXXX0XXX0110 XXXX1XXX0111 XXX0XXXX1000 XXX1XXXX1001 XX0XXXXX1010 XX1XXXXX1011 X0XXXXXX1100 X1XXXXXX1101 0XXXXXXX1110 1XXXXXXX1111 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux1 is JITS Page 69
Department Of ECE Port ( d : in STD_LOGIC_VECTOR (7 downto 0); s : in STD_LOGIC_VECTOR (2 downto 0); f : out STD_LOGIC); end mux1; architecture Behavioral of mux1 is begin f<= d(0) when s="000" else d(1) when s="001" else d(2) when s="010" else d(3) when s="011" else d(4) when s="100" else d(5) when s="101" else d(6) when s="110" else d(7) when s="111"; end Behavioral; VHDL CODE FOR Demultiplexer (1:8): SELECT LINES I/P OUTPUT s(2) s(1) s(0) f d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) 0000XXXXXXX0 0001XXXXXXX1 0010XXXXXX0X 0011XXXXXX1X 0100XXXXX0XX 0101XXXXX1XX 0110XXXX0XXX 0111XXXX1XXX 1000XXX0XXXX 1001XXX1XXXX JITS Page 70
Department Of ECE 1010XX0XXXXX 1011XX1XXXXX 1100X0XXXXXX 1101X1XXXXXX 11100XXXXXXX 11111XXXXXXX
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dmux is port(f:in std_logic; s:in std_logic_vector(2 downto 0); y:out std_logic_vector(7 downto 0)); end demux; architectural behavioral of dmux is begin y(0)<=f when s="000"else'0'; y(1)<=f when s="001"else'0'; y(2)<=f when s="010"else'0'; y(3)<=f when s="011"else'0'; y(4)<=f when s="100"else'0'; y(5)<=f when s="101"else'0'; y(6)<=f when s="110"else'0'; y(7)<=f when s="111"else'0'; end behavioral; JITS Page 71
Department Of ECE VHDL CODE FOR ENCODER WITHOUT PRIORITY (8:3): SELECT LINES OUTPUT s(2) s(1) s(0) y(7) y(6) y(5) y(4) y(3) Y(2) y(1) y(0) 00000000001 00100000010 01000000100 01100001000 10000010000 10100100000 11001000000 111XXXXXXXX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity enco is Port ( i : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0)); end enco; architecture Behavioral of enco is begin with i select y<="000" when "00000001", "001" when "00000010", "010" when "00000100", "011" when "00001000", "100" when "00010000", "101" when "00100000", JITS Page 72
Department Of ECE "110" when "01000000", "111" when others; end Behavioral; VHDL CODE FOR ENCODER WITH PRIORITY (8:3): SELECT LINES OUTPUT s(2) s(1) s(0) y(7) y(6) y(5) y(4) y(3) y(2) y(1) y(0) 00000000111 00100000110 01000000101 01100000001 10000000110 1 0 1 0- 0 0 0 0 0 1 0 11000000100 111XXXXXXXX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity enco1 is Port ( i : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0)); end enco1; architecture Behavioral of enco1 is begin with i select y<="000" when "00000111", "001" when "00000110", "010" when "00000101", JITS Page 73
Department Of ECE "011" when "00000100", "100" when "00000011", "101" when "00000010", "110" when "00000001", "111" when others; end Behavioral; 7.VHDL CODE FOR 3:8 DECODER: SELECT LINES OUTPUT s(2) s(1) s(0) y(7) y(6) y(5) y(4) y(3) y(2) y(1) y(0) 00000000001 00100000010 01000000100 01100001000 10000010000 10100100000 11001000000 11110000000 XXX00000000 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec1 is Port ( s : in STD_LOGIC_VECTOR (2 downto 0); y : out STD_LOGIC_VECTOR (7 downto 0)); end dec1; architecture Behavioral of dec1 is JITS Page 74
Department Of ECE begin with sel select y<="00000001" when "000", "00000010" when "001", "00000100" when "010", "00001000" when "011", "00010000" when "100", "00100000" when "101", "01000000" when "110", "10000000" when "111", "00000000" when others; end Behavioral;
8.VHDL CODE FOR 2-bit comparator: A1 A0 B1 B0 Y1 (A > B) Y2 (A = B) Y3 (A < B) 0000010 0001001 0010001 0011001 0100100 0101010 JITS Page 75
Department Of ECE 0110001 0111001 1000100 1001100 1010010 1011001 1100100 1101100 1110100 1111010 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp is Port ( a,b : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0)); end comp; architecture Behavioral of comp is begin y<= "100" when a>b else "001" when a
Department Of ECE G(1)=B(1) B(2) G(2)=B(2) B(3) G(3)=B(3) Inputs Outputs B (3) B (2) B (1) B (0) G (3) G (2) G (1) G (0) 00000000 00010001 00100011 00110010 01000110 01010111 01100101 01110100 10001100 10011101 10101111 10111110 11001010 11011011 11101001 11111000
library IEEE; use IEEE.STD_LOGIC_1164.ALL; JITS Page 77
Department Of ECE use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Binary_Gray is port( b: in std_logic_vector(3 downto 0); --Binary Input g: out std_logic_vector(3 downto 0)); --Gray Output end binary_gray; architecture behavioral of Binary_gray is begin b(3)<= g(3); b(2)<= g(3) xor g(2); b(1)<= g(2) xor g(1); b(0)<= g(1) xor g(0); end behavioral; VHDL CODE FOR GRAY TO BINARY: CIRCUIT DIAGRAM:
EXPRESSIONS:
B(0)=G(0) G(1) G(2) G(3) B(1)=G(1) G(2) G(3) B(2)=G(2) G(3) B(1)=G(3) INPUT OUTPUT G(3) G(2) G(1) G(0) B (3) B (2) B (1) B (0) JITS Page 78
Department Of ECE 00000000 00010001 00110010 00100011 01100100 01110101 01010110 01000111 11001000 11011001 11111010 11101011 10101100 10111101 10011110 10001111 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gb1 is Port ( g : in STD_LOGIC_VECTOR (3 downto 0); b : out STD_LOGIC_VECTOR (3 downto 0)); end gb1; architecture Behavioral of gb1 is begin b(3)<= g(3); b(2)<= g(3) xor g(2); JITS Page 79
Department Of ECE b(1)<= g(3) xor g(2) xor g(1); b(0)<= g(3) xor g(2) xor g(1) xor g(0); end behavioral; VHDL CODE FOR JK FLIP FLOP WITH ASYNCHRONOUS RESET: (Master Slave JK Flip-Flop) Reset J K Clock Qn+1 Status Qn + 1 1 X X X 0 1 Reset 0 0 0 Qn No Change Qn 0 0 1 0 1 Reset 0 1 0 1 0 Set 011 Qn Toggle Qn library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff1 is Port ( j,k,clk,reset : in STD_LOGIC; Q : inout STD_LOGIC); end jkff1; JITS Page 80
Department Of ECE architecture Behavioral of jkff1 is signal div:std_logic_vector(22 downto 0); signal clkd:std_logic; begin process(clk) begin if rising_edge(clk)then div<= div+1; end if; end process; clkd<=div(22); process(clkd,reset) begin if(reset='1')then Q<= '0'; elsif(clkd'event and clkd='1')then if(j='0' and k ='0')then Q<= Q; elsif(j='0' and k='1')then Q<= '0'; elsif(j='1' and k='0')then Q<= '1'; elsif(j='1' and k='1')then Q<= not Q; end if; end if; end process; end Behavioral; JITS Page 81
Department Of ECE VHDL CODE FOR T FLIP FLOP: + Qn 1 Clear T Clock Qn+1 Qn 1000 Qn 01 Qn library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t,clk,rst : in STD_LOGIC; q : inout STD_LOGIC); end tff; architecture Behavioral of tff is signal div:std_logic_vector(22 downto 0); signal clkd:std_logic; begin process(clk) begin if rising_edge(clk)then div<= div+1; end if; JITS Page 82
Department Of ECE end process; clkd<=div(20); process(clkd,rst) begin if(rst='1')then q<='0'; elsif (clkd'event and clkd='1' and t='1') then q<= not q; else q<=q; end if; end process; end Behavioral; VHDL CODE FOR D FLIP FLOP: + Qn 1 Clear D Clock Qn+1 10001 0110 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is Port ( d,res,clk : in STD_LOGIC; q : out STD_LOGIC); end dff; JITS Page 83
Department Of ECE architecture Behavioral of dff is begin process(clk) begin if (res ='1')then q<='0'; elsif clk'event and clk='1' then q<=d; end if; end process; end Behavioral; ASYNCHRON NOUS BINARRY UP COUNTER: 3-bit t Asynchrono ous up countter Cloock QC QB Q QA 0 00 00 0 1 10 01 1 2 20 10 0 JITS Page 84
Department Of ECE 3 30 11 1 4 41 00 0 5 51 01 1 6 61 10 0 7 71 11 1 8 80 00 0 9 90 01 1 JITS Page 85
Department Of ECE libraary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity asybin1 is Port ( rs,clk : in STD_LOGIC; q : inout STD__LOGIC_VECTOR (3 downto 0)); end asybin1; architecture Behavioral of asybin1 is signal div:std_logic_vector(22 downto 0); signal temp:STD_LOGIC_VECTOR (3 downto 0); signal clkd:std_logic; begin process(clk) begin if rising_edge(clk)then div<= div+1; end if; end process; clkd<=div(22); proccess(clkd,rs) begin if(rs='1'))then temp<=(others=>'00'); --for down counnter temp=>"1111"; elsif(clkdd='1' and clkd'event) then JITS Page 86
Department Of ECE temp<=t temp+1; --for down counter temp<= temp-1; q<= temp; end if; end process; end Behavioral; SYNCHRONOOUS BINARYY UP COUNTER: 3-bit t Asynchronous up counter Clock QC QB QAA 0 00 00 0 1 10 01 1 2 20 10 0 3 30 11 1 JITS Page 87
Department Of ECE 4 41 00 0 5 51 01 1 6 61 10 0 7 71 11 1 8 80 00 0 9 90 01 1 libraary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; JITS Page 88
Department Of ECE use IEEE.STD_LOGIC_UNSIGNED.ALL; entity synbicount is Port ( rs,clk : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 down to 0)); end synbicount; architecture Behavioral of synbicount is signal div:std_logic_vector(22 downto 0); signal temp:STD_LOGIC_VECTOR (3 downto 0); signal clkd:std_logic; begiin process(clk) begin if rising edge(clk)then div<= div+1; end if; end process; clkd<=div(22); process(clkd) begin if(clkd='1' and clkd'event) then if(rs='1'))then temp<=(others=>'00'); ---for down counter temp<="11111" ---for do own counter else temp<=temp+1; temp<= temp-1; end if; q<= temp; JITS Page 89
Department Of ECE end if; end process; end Behavioral; BCD UP COUNTER: Clock QD QC QB QA 00000 10001 20010 30011 40100 50101 60110 70111 81000 91001 10 0 0 0 0 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcdupcount is Port ( clk,rst : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end bcdupcount; architecture Behavioral of bcdupcount is signal div:std_logic_vector(22 downto 0); signal clkd:std_logic; JITS Page 90
Department Of ECE begin process(clkd) begin if rising_edge(clk)then div<= div+1; end if; end process; clkd<=div(22); process(clkd,rst) begin if rst='0' or q="1010" then q<="0000"; elsif clkd'event and clkd='1' then q<=q+1; end if; end process; q<=q; end Behavioral; BCD DOWN COUNTER: Clock QD QC QB QA 01001 11000 20111 30110 40101 50100 60011 70010 JITS Page 91
Department Of ECE 80001 90000 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcddowncounter1 is Port ( clk,rst : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end bcddowncounter1; architecture Behavioral of bcddowncounter1 is signal div:std_logic_vector(22 downto 0); signal clkd:std_logic; begin process(clkd) begin if rising_edge(clk)then div<= div+1; end if; end process; clkd<=div(22); process(clkd,rst) begin if rst='0' or q="1111" then q<="1001"; elsif clkd'event and clkd='1' then q<=q-1; JITS Page 92
Department Of ECE end if; end process; q<=q; end Behavioral; VHDL CODE FOR SEVEN SEGMENT DISPLAY INTERFACE Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Use ieee.std_logic_arith.all; Entity mux_disp is Port (clk:in std_logic ---4mhz
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Department Of ECE rst: in std_logic; seg: out std_logic_vector(6 downto 0) base: out std_logic_vector(3 downto 0)); end mux_disp; architecture mux_disp_arch of mux_disp is signal count : std_logic_vector(25 downto 0); signal base_cnt: std_logic_vector(1 downto 0); signal seg_cnt: std_logic_vector(3 downto 0); begin process(clk,rst) begin if rst = '1' then count<=(others=>'0'); elsif clk='1' and clk'event then count<= + '1'; end if; end process; base_cnt<=count(12 downto11); seg_cnt<=count(25 downto 22); Base<= "1110" when base_cnt="00" else "1101" when base_cnt="01" else "1011" when base_cnt="10" else "0111" when base_cnt="11" else "1111"; Seg<= "0111111" when seg_cnt="0000" else ---0 "0000110" when seg_cnt="0001" else ---1 "1011011" when seg_cnt="0010" else ---2 JITS Page 94
Department Of ECE "1001111" when seg_cnt="0011" else ---3 "1100110" when seg_cnt="0100" else ---4 "1101101" when seg_cnt="0101" else ---5
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Department Of ECE "1111101" when seg_cnt="0110" else ---6 "0000111" when seg_cnt="0111" else ---7 "1111111" when seg_cnt="1000" else ---8 "1100111" when seg_cnt="1001" else ---9 "1110111" when seg_cnt="1010" else ---A "1111100" when seg_cnt="1011" else ---B "0111001" when seg_cnt="1100" else ---C "1011110" when seg_cnt="1101" else ---D "1111001" when seg_cnt="1110" else ---E "1110001" when seg_cnt="0000" else ---F "0000000"; End mux_disp_arch; VHDL CODE FOR MULTIPLEXER (4:1)(STRUCTURAL): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( i0,i1,i2,i3,s0,s1 : in STD_LOGIC; y : out STD_LOGIC); end mux; architecture struct of mux is component and1 ----components, entity and architecture port (l,m,u:in std_logic;n:out std_logic); --- must be declared separately end component; component or1 ----components, entity and architecture port (o,p,x,y:in std_logic;q:out std_logic); --- must be declared separately JITS Page 96
Department Of ECE end component; component not1 ----components, entity and architecture port (r:in std_logic;s:out std_logic); --- must be declared separately end component; signal s2,s3,s4,s5,s6,s7:std_logic; begin u1:and1 port map(i0,s2,s3,s4); u2:and1 port map(i1,s2,s1,s5); u3:and1 port map(i2,s0,s3,s6); u4:and1 port map(i3,s0,s1,s7); u5:not1 port map(s0,s2); u6:not1 port map(s1,s3); u7:or1 port map(s4,s5,s6,s7,y); end struct; VHDL CODE FOR BINARY TO GRAY (Structural): library IEEE; use IEEE E.STD_LOGIC _1164.ALL; use IEEE E.STD_LOGIC _ARITH.ALL; use IEEE E.STD_LOGIC _UNSIGNED .ALL; entity bg is Port ( b : in STD_LOGIC__VECTOR (3 downto 0); g : out STD__LOGIC_VECT TOR (3 downto 0)); end bg; architecture struct of bg is component xor1 port(a, b:in std_logic; ----components, entity and architecture c:out std_logic); JITS Page 97
Department Of ECE --- must be declared separately end compon nent; component and1 port(d,e:in std_logic; ----components, entity and architecture --- must f:out std_logic); must be declared separately end component; begin u1:and1 porrt map(b(3),bb(3),g(3)); u2:xor1 portt map(b(3),bb(2),g(2)); u3:xor1 portt map(b(2),b b(1),g(1)); u4:xor1 portt map(b(1),bb(0),g(0)); end struuct; VHDL CODE : FOR GRAY TO BINARY (Structural): library IEEE; use IEEE.STD D_LOGIC_11 64.ALL; use IEEE.STD _LOGIC_AR ITH.ALL; use IEEE.STD _LOGIC_UN SIGNED.ALL; entity gb is Port( g : in STD_ _LOGIC_VEC CTOR (3 downto 0); b : out STD_LOGIC_VECTOR R (3 downto 0)); end gb; architecture struct of gb is ----component xor1 port(a,b:in std_logic; JITS Page 98
Department Of ECE architecture c:ouut std_logic); --- must be declared separately end component ; component and 1 port(d,e:in std_logic; components, entity and architecture --- must be d f:out std_logic); declared separately end component; component xor1 12 port(g,h,i: :in std_logic; ; ---components, entity and architecture --- must be d k:out std_logic); declared separately end component; component xor13 port(l,m,n,o:in std_logic; ----components, entity and architecture:out std_logic); --- must be declared separately end component ; begin u1:and1 port map(g(3),g(3),b(3)); u2:xor1 port map(g(3),g(2),b(2)); u3:xor12 port map(g(3), g(2),g(1),b(1)); u4:xor13 port map(g(3), g(2),g(1),g(0),b(0)); end struct; JITS Page 99
Department Of ECE VHDL CODE FOR DECODER (Structural): Y (0 ) Y (1 ) Y (2 ) Y (3 ) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec is Port ( a,b : in STD_LOGIC; y: out STD_LOGIC_VECTOR (3 downto 0)); end dec; architecture Behavioral of dec is component and1 is ----components, entity and architecture port(p,q:in std_logic;r:out std_logic); --- must be declared separately end component; component not1 is ----components, entity and architecture port (d:in std_logic;e:out std_logic); --- must be declared separately end component; signal s1,s2:std_logic; begin u1:and1 port map(s1,s2,y(0)); u2:and1 port map(s1,b,y(1)); u3:and1 port map(a,s2,y(2)); u4:and1 port map (a,b,y(3)); JITS Page 100
Department Of ECE u5:not1 port map(a,s1); u6:not1 port map(b,s2); end Behavioral 26. VHDL CODE FOR D FLIP FLOP (Structural): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff1 is Port ( d,clk,pr,clr : in STD_LOGIC; q,qn : inout STD_LOGIC); end dff1; architecture struct of dff1 is component clkdiv is ----components, entity and architecture port(clk:in std_logic;clk_d:out std_logic); --- must be declared separately end component; component nand1 is port(a,b,c:in std_logic; ----components, entity and architecture d:out std_logic); --- must be declared separately end component; component nand12 is port(x,y:in std_logic; ----components, entity and architecture z:out std_logic); --- must be declared separately end component; component nand13 is port(e:in std_logic; ----components, entity and architecture f:out std_logic); --- must be declared separately JITS Page 101
Department Of ECE end component; signal s1,s2,s3,s4,s5,s6,s7,s8,s9:std_logic; begin u10:clkdiv port map(clk,s7); u1:nand1 port map(d,s7,qn,s1); u2:nand1 port map(s9,s7,q,s2); u3:nand1 port map(pr,s1,s4,s3); u4:nand1 port map(s2,clr,s3,s4); u5:nand12 port map(s3,s8,s5); u6:nand12 port map(s8,s4,s6); u7:nand12 port map(s5,qn,q); u8:nand12 port map(s6,q,qn); u9:nand13 port map(s7,s8); u11:nand13 port map(d,s9); end struct;
27. VHDL CODE FOR JK FLIP FLOP (Structural): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff is Port ( j,k,clk,pr,clr : in STD_LOGIC; q,qn : inout STD_LOGIC); end jkff; architecture struct of jkff is JITS Page 102
Department Of ECE component clkdiv is ----components, entity and architecture port(clk:in std_logic;clk_d:out std_logic); --- must be declared separately end component; component nand1 is ----components, entity and architecture port(a,b,c:in std_logic; --- must be declared separately d:out std_logic); end component; component nand12 is ----components, entity and architecture port(x,y:in std_logic; --- must be declared separately z:out std_logic); end component; component nand13 is port(e:in std_logic; ----components, entity and architecture f:out std_logic); --- must be declared separately end component; signal s1,s2,s3,s4,s5,s6,s7,s8:std_logic; begin u10:clkdiv port map(clk,s7); u1:nand1 port map(j,qn,s7,s1); u2:nand1 port map(k,s7,q,s2); u3:nand1 port map(pr,s1,s4,s3); u4:nand1 port map(s2,clr,s3,s4); u5:nand12 port map(s3,s8,s5); u6:nand12 port map(s8,s4,s6); u7:nand12 port map(s5,qn,q); u8:nand12 port map(s6,q,qn); u9:nand13 port map(s7,s8); end struct; JITS Page 103
Department Of ECE VHDL CODE FOR T FLIP FLOP (Structural): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff1 is Port ( t,clk,pr,clr : in STD_LOGIC; q,qn : inout STD_LOGIC); end tff1; architecture struct of tff1 is component clkdiv is ----components, entity and architecture port(clk:in std_logic;clk_d:out std_logic); --- must be declared separately end component; component nand1 is port(a,b,c:in std_logic; ----components, entity and architecture d:out std_logic); --- must be declared separately end component; component nand12 is port(x,y:in std_logic; ----components, entity and architecture z:out std_logic); --- must be declared separately end component;
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Department Of ECE component nand13 is port(e:in std_logic; ----components, entity and architecture f:out std_logic); --- must be declared separately end component; signal s1,s2,s3,s4,s5,s6,s7,s8:std_logic; begin u10:clkdiv port map(clk,s7); u1:nand1 port map(t,qn,s7,s1); u2:nand1 port map(t,s7,q,s2); u3:nand1 port map(pr,s1,s4,s3); u4:nand1 port map(s2,clr,s3,s4); u5:nand12 port map(s3,s8,s5); u6:nand12 port map(s8,s4,s6); u7:nand12 port map(s5,qn,q); u8:nand12 port map(s6,q,qn); u9:nand13 port map(s7,s8); end struct; 1 BIT COMPARATOR (structural): Y2 Y3 A B Y1 (A>B) (A = B) (A < B) 00010 01001 10100 11010 JITS Page 105
Department Of ECE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp is Port ( a,b : in STD_LOGIC; y : out STD_LOGIC_VECTOR (2 downto 0)); end comp; architecture struct of comp is component and1 port(l,m:in std_logic; ----components, entity and architecture n:out std_logic); --- must be declared separately end component; component xnor1 is port(p,q:in std_logic; ----components, entity and architecture r:out std_logic); --- must be declared separately end component; component notgate1 is port(s:in std_logic; ----components, entity and architecture t:out std_logic); --- must be declared separately end component; signal s1,s2:std_logic; begin u1:and1 port map(a,s2,y(0)); u2:and1 port map(s1,b,y(1)); u3:xnor1 port map(a,b,y(2)); u4:notgate1 port map(a,s1); JITS Page 106
Department Of ECE u5:notgate1 port map(b,s2); end struct;
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Department of Electronics and Communication Engineering LAB MANUAL BASIC SIMULATION LAB- II B.Tech(ECE) I Sem Prepared by : A. Sabitha
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Department Of ECE HOD E-CAD AND VLSI LAB : List of Experiments Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate-level design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects ( temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitics and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS) E-CAD programs: Programming can be done using any complier. Down load the programs on FPGA/LD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools. 1. HDL code to realize all the logic gates 2. Design of 2-to-4 decoder 3. Design of 8-to-3 encoder (without and with parity) 4. Design of 8-to-1 multiplexer 5. Design of 4 bit binary to gray converter 6. Design of Multiplexer/ Demultiplexer, comparator 7. Design of Full adder using 3 modeling styles 8. Design of flip flops: SR, D, JK, T 9. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter 10. Finite State Machine Design
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Department Of ECE
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Department Of ECE VLSI programs: 1. Introduction to layout design rules 2. Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following: Basic logic gates -CMOS inverter -CMOS NOR/ NAND gates -CMOS XOR and MUX gates -CMOS 1-bit full adder -Static / Dynamic logic circuit ( cell) -Latch - transistor 3. Layout of any combinational circuit (complex CMOS logic gate)- Learning about data paths 4. Introduction to SPICE simulation and coding of NMOS/CMOS circuit 5. SPICE simulation of basic analog circuits: Inverter / Differential amplifier 6. Analog Circuit simulation (AC analysis) – CS & CD amplifier 7. System level design using PLL
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Department Of ECE EXPERIMENT -1 Simulation using all the modeling styles and Synthesis of all the logic gates usingVerilog HDL --------------------------------------------------------------------------------------------------------------------Aim: 1. Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural modeling style in Verilog using a Test bench. 2. Synthesize each one of them on two different EDA tools. Apparatus required: Electronics Design Automation Tools used: i) Xilinx Spartan 3E FPGA +LD Board ii) Model Sim simulation tool or Xilinx ISE Simulator tool iii) Xilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow fromSimulation to Implementation to onto FPGA). v) JTAG cable vi) Adator 5v/4A Boolean equations: And Gate:Y = (A.B) Or Gate: Y = (A + B) Nand Gate: Y = (A.B)’ Nor Gate: Y = (A+B)’ Xor Gate: Y = A.B’ + A’.B Xnor Gate: Y = A.B + A’.B’ JITS Page 5
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Department Of ECE Block diagram:
Verilog program for AND gate: // And Gate (In Dataflow, behavioral Modeling): Module andg(a,b,c); input a,b; output c; assign c = a & b; endmodule //behavioural modeling Module andg1(a,b,c); input a,b; always(a,b) begin if (a==1’b0 or b == 1’b0) c = 1’b0; JITS Page 7
Department Of ECE else if (a==1’b0 or b == 1’b1) c = 1’b0; else if (a==1’b1 or b == 1’b0) c = 1’b0; else if (a==1’b1 or b == 1’b1) c = 1’b1; endendmodule Verilog program for OR gate: //Or gate(Dataflow, behavioral modeling): Module org (a,b,c); input a,b; output c; assign c = a | b; endmodule Verilog program for nand gate: // Nand Gate (In Dataflow modeling): Module nandg (a,b,c); input a,b; output c; assign c = ~(a & b); endmodule Verilog program for NOR gate: // Nor Gate (In Dataflow modeling): Module norg (a,b,c); input a,b; JITS Page 8
Department Of ECE output c; assign c = ~(a | b); endmodule
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Department Of ECE Verilog program for XOR gate: Xor gate(In Dataflow modeling): Module xorg (a,b,c); input a,b; output c; assign c = a ^ b; endmodule (or) Module xorg2 (a,b,c); input a,b; output c; assign c = (~a & b) | (a & ~b); endmodule Verilog program for XNOR gate: //Xnor Gate (In Dataflow modeling): Module xnorg (a,b,c); input a,b; output c; assign c = ~(a ^ b); endmodule module notgate (a,b); input a; output b; assign b = ~ (a); endmodule
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Department Of ECE VHDL PROGRAM FOR ALL LOGIC GATES: library ieee; use ieee.std_logic_1164.all; entity digital_gates is port( x: in std_logic; y: in std_logic; sel:in std_logic_vector(1 downto 0); F: out std_logic); end digital_gates; architecture behav1 of digital_gates is begin process(x, y, sel) begin if (sel = "00") then F <= x and y; elsif (sel = "01") then F <= x or y; elsif (sel = "10") then F <= x nand y; elsif (sel = "11") then F <= x nor y; else F <= '0'; end if; end process; end behav1;
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Department Of ECE Test Bench: programmable digital gates library ieee; use ieee.std_logic_1164.all; entity tb_digital_gates is end tb_digital_gates; architecture behav1 of tb_digital_gates is component digital_gates is port( x: in std_logic; y: in std_logic; sel:in std_logic_vector(1 downto 0); F: out std_logic ); end component; signal x,y,F:std_logic; signal sel:std_logic_vector(1 downto 0); begin U1: digital_gates port map(x,y, sel,F); process begin x <= '0'; wait for 10 ns; x <= '1'; wait for 20 ns; end process; process begin y <= '0';
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Department Of ECE wait for 20 ns; y <= '1'; wait for 30 ns; end process; process begin sel <= "00","01" after 20 ns,"10" after 40 ns,"11" after 80 ns; wait for 120 ns; end process; end behav1;
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Department Of ECE EXPERIMENT -2 Design of decoder usingVerilog HDL --------------------------------------------------------------------------------------------------------------------Aim: 1. Perform Zero Delay Simulation of decodere in Verilog using a Test bench. 2. Synthesize each one of them on two different EDA tools. Apparatus required: Electronics Design Automation Tools used: i) Xilinx Spartan 3E FPGA +LD Board ii) Model Sim simulation tool or Xilinx ISE Simulator tool iii) Xilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow fromSimulation to Implementation to onto FPGA). v) JTAG cable vi) Adator 5v/4A Block diagram:
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Department Of ECE
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Department Of ECE Verilog program: module decoder(a, y); input [1:0] a; output [3:0] y; reg [3:0] y; always @ (a) case(a) 2’b00: y<= 4’b1110; 2’b01: y<= 4’b1101; 2’b10: y<= 4’b1011; 2’b11: y<= 4’b0111; end case; endmodule ******************************************** //decoder using case statement module dec2to4(W, Y, En); input [1:0] W; input En; output [0:3] Y; reg [0:3] Y; always @(*) case ({en,W}) 3’b100: Y = 4’b1000; 3’b101: Y = 4’b0100; 3’b110: Y = 4’b0010; 3’b111: Y = 4’b0001; default: Y = 4’b0000; endcase JITS Page 17
Department Of ECE endmodule **************************************************** module decoder_2to4(Y3, Y2, Y1, Y0, A, B, en); output Y3, Y2, Y1, Y0; input A, B; input en; reg Y3, Y2, Y1, Y0; always @(A or B or en) begin if (en == 1'b1) case ( {A,B} ) 2'b00: {Y3,Y2,Y1,Y0} = 4'b1110; 2'b01: {Y3,Y2,Y1,Y0} = 4'b1101; 2'b10: {Y3,Y2,Y1,Y0} = 4'b1011; 2'b11: {Y3,Y2,Y1,Y0} = 4'b0111; default: {Y3,Y2,Y1,Y0} = 4'bxxxx; endcase if (en == 0) {Y3,Y2,Y1,Y0} = 4'b1111; end endmodule //***************test bench******************** module Test_decoder_2to4; wire Y3, Y2, Y1, Y0; reg A, B; reg en; // Instantiate the Decoder (named DUT {device under test}) JITS Page 18
Department Of ECE decoder_2to4 DUT(Y3, Y2, Y1, Y0, A, B, en); initial begin $timeformat(-9, 1, " ns", 6); #1; A = 1'b0; // time = 0 B = 1'b0; en = 1'b0; #9; en = 1'b1; // time = 10 #10; A = 1'b0; B = 1'b1; // time = 20 #10; A = 1'b1; B = 1'b0; // time = 30 #10; A = 1'b1; B = 1'b1; // time = 40 #5; en = 1'b0; // time = 45 #5; end always @(A or B or en) #1 $display("t=%t",$time," en=%b",en," A=%b",A," B=%b",B," Y=%b%b%b %b",Y3,Y2,Y1,Y0); endmodule ****************************************** module decode24(q, a); output[3:0] q; JITS Page 19
Department Of ECE input[1:0] a; assign q = (4’b0001) << a; endmodule ********************************** module dec2to4(W, Y, En); input [1:0] W; input En; output [0:3] Y; reg [0:3] Y; always @(*) case ({en,W}) 3’b100: Y = 4’b1000; 3’b101: Y = 4’b0100; 3’b110: Y = 4’b0010; 3’b111: Y = 4’b0001; default: Y = 4’b0000; endcase endmodule ***************************************************************************** 3 TO 8 DECODER ***************************************************************************** module decoder(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,A,B,C); output Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7; input A,B,C; wire s0,s1,s2; not (s0,A); not (s1,B); not (s2,C); JITS Page 20
Department Of ECE and (Q0,s0,s1,s2); and (Q1,A,s1,s2); and (Q2,s0,B,s2); and (Q3,A,B,s2); and (Q4,s0,s1,C); and (Q5,A,s1,C); and (Q6,s0,B,C); and (Q7,A,B,C); endmodule //*****TESTBENCH*******// module stimulus; // Set up variables reg A, B, C; // Instantiate the decoder. decoder FF(Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,A,B,C); // Setup the monitoring for the signal values initial begin $monitor($time,"C=%b, =%b,A=%b ,Q=%b%b%b%b%b%b%b%b\n", C,B,A,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7); end // Stimulate inputs Initial begin C=1'b0; B =1'b0; A = 1'b0; #10 C =1'b0; B = 1'b0; A= 1'b1; #10 C =1'b0; B = 1'b1; A= 1'b0; #10 C =1'b0; B = 1'b1; A= 1'b1; #10 C =1'b1; B = 1'b0; A= 1'b0; JITS Page 21
Department Of ECE #10 C =1'b1; B = 1'b0; A= 1'b1; #10 C =1'b1; B = 1'b1; A= 1'b0; #10 C =1'b1; B = 1'b1; A= 1'b1; end endmodule ********************************************************** module decoder_3to8(Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0, A, B, C, en); output Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0; input A, B, C; input en; assign {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} = ( {en,A,B,C} == 4'b1000) ? 8'b1111_1110 : ( {en,A,B,C} == 4'b1001) ? 8'b1111_1101 : ( {en,A,B,C} == 4'b1010) ? 8'b1111_1011 : ( {en,A,B,C} == 4'b1011) ? 8'b1111_0111 : ( {en,A,B,C} == 4'b1100) ? 8'b1110_1111 : ( {en,A,B,C} == 4'b1101) ? 8'b1101_1111 : ( {en,A,B,C} == 4'b1110) ? 8'b1011_1111 : ( {en,A,B,C} == 4'b1111) ? 8'b0111_1111 : 8'b1111_1111; Endmodule //TESTBENCH module Test_decoder_3to8; wire Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0; reg A, B, C; reg en; // Instantiate the Decoder (named DUT {device under test}) decoder_3to8 DUT(Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0, A, B, C, en); initial begin JITS Page 22
Department Of ECE $timeformat(-9, 1, " ns", 6); #1; A = 1'b0; // time = 0 B = 1'b0; C = 1'b0; en = 1'b0; #9; en = 1'b1; // time = 10 #10; A = 1'b0; B = 1'b1; C = 1'b0; // time = 20 #10; A = 1'b1; B = 1'b0; C = 1'b0; // time = 30 #10; A = 1'b1; B = 1'b1; C = 1'b0; // time = 40 #5; en = 1'b0; // time = 45 #5; end always @(A or B or C or en) $display("t=%t en=%b ABC=%b%b%b Y=%b%b%b%b%b%b%b%b", $time,en,A,B,C,Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0); Endmodule ******************************************************** JITS Page 23
Department Of ECE module decoder (in,out); input [2:0] in; output [7:0] out; wire [7:0] out; assign out = (in == 3'b000 ) ? 8'b0000_0001 : (in == 3'b001 ) ? 8'b0000_0010 : (in == 3'b010 ) ? 8'b0000_0100 : (in == 3'b011 ) ? 8'b0000_1000 : (in == 3'b100 ) ? 8'b0001_0000 : (in == 3'b101 ) ? 8'b0010_0000 : (in == 3'b110 ) ? 8'b0100_0000 : (in == 3'b111 ) ? 8'b1000_0000 : 8'h00; endmodule
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Department Of ECE ******************************************************** module decoder_always (in,out); input [2:0] in; output [7:0] out; reg [7:0] out; always @ (in) begin out = 0; case (in) 3'b001 : out = 8'b0000_0001; 3'b010 : out = 8'b0000_0010; 3'b011 : out = 8'b0000_0100; 3'b100 : out = 8'b0000_1000; 3'b101 : out = 8'b0001_0000; 3'b110 : out = 8'b0100_0000; 3'b111 : out = 8'b1000_0000; endcase end endmodule //USING FOR LOOP module Decode3To8For(yOut, aIn, enable); output [7:0]yOut; input [2:0]aIn; input enable; reg [7:0] yOut; integer k; always@(aIn or enable) begin JITS Page 25
Department Of ECE if(enable == 1) begin for(k=0;k<8;k=k+1)
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Department Of ECE begin if(aIn == k) yOut[k] = 0; else yOut[k] = 1; end end end endmodule ***************************************************************************
BCD decoder **************************************************************** This circuit has four binary inputs and ten binary outputs. The ith output is asserted if the binary inputs are the binary number i, where 0 ≤ i ≤ 9. The inputs will never be a number greater than 9 (or if they are, we don’t care what the output is). module (X, Y); input [3:0] X; output [0:9] Y; reg [0:9] Y; always @(*) begin Y = 0; case (X) 0: Y[0] = 1; 1: Y[1] = 1; 2: Y[2] = 1; 3: Y[3] = 1; 4: Y[4] = 1; 5: Y[5] = 1; JITS Page 27
Department Of ECE 6: Y[6] = 1; 7: Y[7] = 1; 8: Y[8] = 1; 9: Y[9] = 1; default: Y = ’bx; endcase end endmodule
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Department Of ECE EXPERIMENT -3 Design of 8-to-3 encoder (without and with parity) usingVerilog HDL --------------------------------------------------------------------------------------------------------------------Aim: 1. Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural modeling style in Verilog using a Test bench. 2. Synthesize each one of them on two different EDA tools. Apparatus required: Electronics Design Automation Tools used: i) Xilinx Spartan 3E FPGA +LD Board ii) Model Sim simulation tool or Xilinx ISE Simulator toolXilinx XST iii) Synthesis tool or LeonardoSpectrum Synthesis Tool iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow fromSimulation to Implementation to onto FPGA). v) JTAG cable vi) Adator 5v/4A THEORY: An encoder is a digital circuit which performs the inverse of decoder.An encoder has 2^N input lines and N output lines.In encoder the output lines genrate the binary code corresponding to input value.The decimal to bcd encoder usually has 10 input lines and 4 ouput lines.The decoder decimal data as an input for decoder an encoded bcd ouput is available at 4 output lines.
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Y2 = w7 + w6 + w5 + w4 Y1 = w7 + w6 + w3 + w2 Y0 = w7 + w5 + w3 + w1 Verilog program for 8x3 encoder: module encoder (din, dout); input [7:0] din; output [2:0] dout; reg [2:0] dout; always @(din) begin if (din ==8'b00000001) dout=3'b000; else if (din==8'b00000010) dout=3'b001; else if (din==8'b00000100) dout=3'b010; else if (din==8'b00001000) dout=3'b011; else if (din==8'b00010000) dout=3'b100; else if (din ==8'b00100000) dout=3'b101; else if (din==8'b01000000) dout=3'b110; else if (din==8'b10000000) dout=3'b111; else dout=3'bX; end endmodule
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Department Of ECE Priority Encoders -A priority encoder has n inputs and ⎡log2n⎤ outputs. -The output signals are a binary number such that its valueis the highest index value of all the inputs that are 1. Example: 4-to-2 priority encoder: y1 = w3’•w2 + w3 y2 = w3’•w2’•w1 + w3 z = w0 + w1 + w2 + w3 Priority encoder is a special type of encoder in which multiple bits at the input can be asserted. The response at the output is however defined by the priority rule, defined previously. Priority encoders have vast application in different client-server systems. In client-server systems decision is made to grant a service based on the priority of any specific client. Here is a verilog code for an 8:3 priority encoder. It grants the highest priority to the "most left sided bit in the input word". For example in data word "00010101" the highest priority is carried by the most left sided one, appearing at the fourth (counting from left side). So all the other bits that come next to it will be discarded or in other words will not be taken into . Verilog implementation has been done using "casex" statement. an 8-bit priority encoder. This circuit basically converts a one-hot encoding into a binary representation. If input n is active, all lower inputs (n-1 .. 0) are ignored. Please read the description of the 4:2 encoder for an explanation.
module priority_encoder (code, valid_data, data); JITS Page 31
Department Of ECE output [2:0] code; output valid data; input [7:0] data; reg [2:0] code; assign valid_data= |data; // Use of "reduction or" operator always @ (data) begin casex (data) 8'b1xxxxxxx : code=7; 8'b01xxxxxx : code=6; 8'b001xxxxx : code=5 8'b0001xxxx : code=4; 8'b00001xxx : code=3; 8'b000001xx : code=2; 8'b0000001x : code=1; 8'b00000001 : code=0; dafault : code=3'bx; endcase endmodule Verilog program for 4 x2 priority encoder module priority (W, Y, z); input [3:0] W; output [1:0] Y; output z; reg [1:0] Y; reg z; always @(*) begin z = 1; JITS Page 32
Department Of ECE casex (W) 4’b1xxx: Y = 3; 4’b01xx: Y = 2; 4’b001x: Y = 1; 4’b0001: Y = 0; default: begin z=0; Y = 2’bxx; end endcase end endmodule Verilog code for a 3-bit 1-of-9 Priority Encoder: module priority (sel, code); input [7:0] sel; output [2:0] code; reg [2:0] code; always @(sel) begin if (sel[0]) code = 3’b000; else if (sel[1]) code = 3’b001; else if (sel[2]) code = 3’b010; else if (sel[3]) code = 3’b011; JITS Page 33
Department Of ECE else if (sel[4]) code = 3’b100; else if (sel[5]) code = 3’b101; else if (sel[6]) code = 3’b110; else if (sel[7]) code = 3’b111; else code = 3’bxxx; end endmodule Pri-Encoder - Using if-else Statement ------------------------------------------------module pri_encoder_using_if ( binary_out , // 4 bit binary output encoder_in , // 16-bit input enable // Enable for the encoder ); output [3:0] binary_out ; input enable ; input [15:0] encoder_in ; reg [3:0] binary_out ; always @ (enable or encoder_in) begin binary_out = 0; if (enable) begin JITS Page 34
Department Of ECE if (encoder_in[0] == 1) begin binary_out = 1; end else if (encoder_in[1] == 1) begin binary_out = 2; end else if (encoder_in[2] == 1) begin binary_out = 3; end else if (encoder_in[3] == 1) begin binary_out = 4; end else if (encoder_in[4] == 1) begin binary_out = 5; end else if (encoder_in[5] == 1) begin binary_out = 6; end else if (encoder_in[6] == 1) begin binary_out = 7; end else if (encoder_in[7] == 1) begin binary_out = 8; end else if (encoder_in[8] == 1) begin binary_out = 9; end else if (encoder_in[9] == 1) begin binary_out = 10; end else if (encoder_in[10] == 1) begin binary_out = 11; end else if (encoder_in[11] == 1) begin binary_out = 12; end else if (encoder_in[12] == 1) begin binary_out = 13; end else if (encoder_in[13] == 1) begin binary_out = 14; JITS Page 35
Department Of ECE end else if (encoder_in[14] == 1) begin binary_out = 15; end end end endmodule
Encoder - Using assign Statement module pri_encoder_using_assign ( binary_out , // 4 bit binary output encoder_in , // 16-bit input enable // Enable for the encoder ); output [3:0] binary_out ; input enable ; input [15:0] encoder_in ; wire [3:0] binary_out ; assign binary_out = ( ! enable) ? 0 : ( (encoder_in[0]) ? 0 : (encoder_in[1]) ? 1 : (encoder_in[2]) ? 2 : (encoder_in[3]) ? 3 : (encoder_in[4]) ? 4 : (encoder_in[5]) ? 5 : (encoder_in[6]) ? 6 : (encoder_in[7]) ? 7 : (encoder_in[8]) ? 8 : (encoder_in[9]) ? 9 : JITS Page 36
Department Of ECE (encoder_in[10]) ? 10 : (encoder_in[11]) ? 11 : (encoder_in[12]) ? 12 : (encoder_in[13]) ? 13 : (encoder_in[14]) ? 14 : 15); endmodule
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Department Of ECE EXPERIMENT -4 Design of multiplexer usingVerilog HDL --------------------------------------------------------------------------------------------------------------------Aim: 3. Perform Zero Delay Simulation of multiplexerin Verilog using a Test bench. 4. Synthesize each one of them on two different EDA tools. Apparatus required: Electronics Design Automation Tools used: vii) Xilinx Spartan 3E FPGA +LD Board viii) Model Sim simulation tool or Xilinx ISE Simulator toolXilinx XST ix) Synthesis tool or LeonardoSpectrum Synthesis Tool x) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow fromSimulation to Implementation to onto FPGA). xi) JTAG cable xii) Adator 5v/4A Block Diagram:
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Verilog program for 2x1 multiplexer:
module mux2to1 (w0, w1, s, f); input w0, w1, s; JITS Page 39
Department Of ECE output f; assign f = s ? w1: w0; endmodule ***************************** module mux21(q, sel, a, b); input sel, a, b; output q; assign q = (~sel & a) | (sel & b); endmodule ****************************** module mux21(q, sel, a, b); input sel, a, b; output q; assign q = sel ? b : a; endmodule ************************* module mux21(q, sel, a, b); wire[3:0] a, b, q; wire sel; assign q = sel ? b: a; endmodule ***************************** module mux_2to1(Y, A, B, sel); output [15:0] Y; input [15:0] A, B; input sel; reg [15:0] Y; always @(A or B or sel) JITS Page 40
Department Of ECE if (sel == 1'b0) Y = A; else Y = B; endmodule ********************************** module mux2(out,i0,i1,s0); output out; input i0,i1,s0; //internal wires wire sbar,y1,y2; not g1(sbar,s0); and g2(y1,i0,sbar); and g3(y2,i1,s0); or g4(out,y1,y2); endmodule //test bench module text_mux2; reg i0,i1; reg s0; wire out; mux2 mymux(out,i0,i1,s0); initial $monitor($time,"s0=%b,i0=%b,i1=%b,out=%b\n",s0,i0,i1,out); initial begin s0=0;i0=0;i1=0; #50 s0=0;i0=0;i1=1; JITS Page 41
Department Of ECE #50 s0=1;i0=0;i1=1; #50 s0=0;i0=1;i1=0; #50 s0=1;i0=1;i1=0; end endmodule ************************************************************ module mux21(q, sel, a, b); input sel; input[15:0] a, b; output[15:0] q; assign q = sel ? b : a; endmodule ******************* module mux21n(q, sel, a, b); parameter WID = 16; input sel; input[WID-1:0] a, b; output[WID-1:0] q; assign q = sel ? b : a; endmodule *****************************************************************
4 X 1 MULTIPLEXER ******************************************************* module mux4to1 (w0, w1, w2, w3, S, f); input w0, w1, w2, w3; input [1:0] S; output f; assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0); JITS Page 42
Department Of ECE endmodule ******************************** module mux4to1 (W, S, f); input [0:3] W; input [1:0] S; output f; reg f; always @(*) if (S == 0) f = W[0]; else if (S == 1) f = W[1]; else if (S == 2) f = W[2]; else if (S == 3) f = W[3]; endmodule ******************************************** module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); // Port declarations from the I/O diagram output out; input i0, i1, i2, i3; input s1, s0; // Internal wire declarations wire s1n, s0n; wire y0, y1, y2, y3; // Gate instantiations not (s1n, s1); JITS Page 43
Department Of ECE not (s0n, s0); and (y0, i0, s1n, s0n); and (y1, i1, s1n, s0); and (y2, i2, s1, s0n); and (y3, i3, s1, s0); or (out, y0, y1, y2, y3); endmodule /////TEST BENCH module stimulus; // Declare variables to be connected to inputs reg IN0, IN1, IN2, IN3; reg S1, S0; // Declare output wire wire OUTPUT; // Instantiate the multiplexer mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0); // Stimulate the inputs initial begin IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0; #1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3); S1 = 0; S0 = 0; #50 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); S1 = 0; S0 = 1; #50 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); S1 = 1; S0 = 0; #50 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); S1 = 1; S0 = 1; JITS Page 44
Department Of ECE #50 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); end endmodule **************************************** module mux41(q, sel, a, b, c, d); parameter WID=16; input[1:0] sel; input[WID-1:0] a, b, c, d; output[WID-1:0] q; assign q = (sel==2'b00) ? a:(sel==1) ? b:(sel==2’b10) ? c:d; endmodule **************************************** module mux41n(q, sel, a, b, c, d); parameter WID=16; input[1:0] sel; input[WID-1:0] a, b, c, d; output[WID-1:0] q; wire[WID-1:0] tmp1, tmp2; mux21n #(WID) M0(tmp1, sel[0], a, b); mux21n #(WID) M1(tmp2, sel[0], c, d); mux21n #(WID) M2(q, sel[1], tmp1, tmp2); endmodule module mux_4to1(Y, A, B, C, D, sel); output [15:0] Y; input [15:0] A, B, C, D; input [1:0] sel; reg [15:0] Y; always @(A or B or C or D or sel) JITS Page 45
Department Of ECE case ( sel ) 2'b00: Y = A; 2'b01: Y = B; 2'b10: Y = C; 2'b11: Y = D; default: Y = 16'hxxxx; endcase endmodule ////////TEST BENCH module Test_mux_4to1; wire [15:0] MuxOut; //use wire data type for outputs from instantiated module reg [15:0] A, B, C, D; //use reg data type for all inputs reg [1:0] sel; // to the instantiated module reg clk; //to be used for timing of WHEN to change input values // Instantiate the MUX (named DUT {device under test}) mux_4to1 DUT(MuxOut, A, B, C, D, sel); //This block generates a clock pulse with a 20 ns period always #10 clk = ~clk; //This initial block will provide values for the inputs // of the mux so that both inputs/outputs can be displayed initial begin $timeformat(-9, 1, " ns", 6); clk = 1’b0; // time = 0 A = 16'hAAAA; B = 16'h5555; C = 16'h00FF; D = 16'hFF00; sel = 2'b00; @(negedge clk) //will wait for next negative edge of the clock (t=20) A = 16'h0000; @(negedge clk) //will wait for next negative edge of the clock (t=40) JITS Page 46
Department Of ECE sel = 2'b01; @(negedge clk) //will wait for next negative edge of the clock (t=60) B = 16'hFFFF; @(negedge clk) //will wait for next negative edge of the clock (t=80) sel = 2'b10; A = 16'hA5A5; @(negedge clk) //will wait for next negative edge of the clock (t=100) sel = 2'b00; @(negedge clk) //will wait for next negative edge of the clock (t=120) $finish; // to shut down the simulation end //initial // this block is sensitive to changes on ANY of the inputs and will // then display both the inputs and corresponding output always @(A or B or C or D or sel) #1 $display("At t=%t / sel=%b A=%h B=%h C=%h D=%h / MuxOut=%h", $time, sel, A, B, C, D, MuxOut); endmodule
****************************************************************** 16 x 1 MULTIPLEXER ***************************************************************** module mux16to1 (W, S, f, M); input [0:15] W; input [3:0] S; output f; output [3:0] M; wire [0:3] M; mux4to1 Mux1 (W[0:3], S[1:0], M[0]); mux4to1 Mux2 (W[4:7], S[1:0], M[1]); JITS Page 47
Department Of ECE mux4to1 Mux3 (W[8:11], S[1:0], M[2]); mux4to1 Mux4 (W[12:15], S[1:0], M[3]); mux4to1 Mux5 (M[0:3], S[3:2], f); endmodule ********************************************* module mux_16to1(Y, In, sel); output Y; input [15:0] In; input [3:0] sel; wire lo8, hi8, out1; // Instantiate the 8-to-1 muxes and the 2-to-1 mux mux_8to1 mux_lo (lo8, In[7:0], sel[2:0]); mux_8to1 mux_hi (hi8, In[15:8], sel[2:0]); mux_2to1 mux_out (out1, lo8, hi8, sel[3]); // equate the wire out of the 2-to-1 with // the actual output (Y) of the 16-to-1 mux assign Y = out1; endmodule module Test_mux_16to1; wire MuxOut; reg [15:0] In; reg [3:0] sel; // Instantiate the MUX (named DUT {device under test}) mux_16to1 DUT(MuxOut, In, sel); initial begin $timeformat(-9, 1, " ns", 6); $monitor("At t=%t sel=%b In=%b_%b MuxOut=%b",$time,sel,In[15:8],In[7:0],MuxOut); In = 16'b1100_0011_1011_0100; // time = 0 JITS Page 48
Department Of ECE sel = 4'b0000; #10; sel = 4'b0001; // time = 10 #10; sel = 4'b0010; // time = 20 #10; sel = 4'b0011; // time = 30 #10; In = 16'b1100_0011_1011_1111; sel = 4'b0100; // time = 40 #10; sel = 4'b0101; // time = 50 #10; sel = 4'b0110; // time = 60 #10; sel = 4'b0111; // time = 70 #10; In = 16'b1100_0011_1111_1111; // time = 80 sel = 4'b1000; #10; sel = 4'b1001; // time = 90 #10; sel = 4'b1010; // time = 100 #10; sel = 4'b1011; // time = 110 #10; In = 16'b1100_1111_1111_1111; sel = 4'b1100; // time = 120 JITS Page 49
Department Of ECE #10; sel = 4'b1101; // time = 130 #10; sel = 4'b1110; // time = 140 #10; sel = 4'b1111; // time = 150 #5; $finish; end endmodule
Demultiplexor A demultiplexor is the converse of a multiplexor. It takes one input and directs it to any of N inputs, based on the number specified in the select lines. It could be captured either using procedural code or continuous assignment. Both of the following statements describe identical behavior. VERILOG PROGRAM: module (in1, sel, out2); input [1:0] in1; input [2:0] sel; output [13:0] out2; reg [15:0] out2; integer I; always@(in1 or sel) begin out2 = 14’h0; /* default = 00 */ for (I=0; I<=7; I=I+1) if (I == sel) begin JITS Page 50
Department Of ECE out2[I] = in1[0]; out2[I+1] = in1[1]; end end endmodule /*----------------------------*/ module (in1, sel, out2); input [1:0] in1; input [2:0] sel; output [15:0] out2; reg [7:0] select; /* address decoder */ always@(sel) case (sel) 3’b000 : select = 8’b00000001; 3’b001 : select = 8’b00000010; 3’b010 : select = 8’b00000100; 3’b011 : select = 8’b00001000; 3’b100 : select = 8’b00010000; 3’b101 : select = 8’b00100000; 3’b110 : select = 8’b01000000; 3’b111 : select = 8’b10000000; endcase assign out2[1:0] = in1 & select[0]; assign out2[3:2] = in1 & select[1]; assign out2[5:4] = in1 & select[2]; assign out2[7:6] = in1 & select[3]; assign out2[9:8] = in1 & select[4]; JITS Page 51
Department Of ECE assign out2[11:10] = in1 & select[5]; assign out2[13:12] = in1 & select[6]; assign out2[15:14] = in1 & select[7]; endmodule VERilog code for 1-bit fill adder: //define a 1bit fulladder module fulladd(sum, c_out, a, b, c_in); output sum, c_out; input a, b, c_in; wire s1, c1, c2; xor (s1, a, b); and (c1, a, b); xor (sum, s1, c_in); and (c2, s1, c_in); or (c_out, c2, c1); endmodule module stimulus; //declare variables to be connected reg A, B; reg C_IN; wire SUM; wire C_OUT; // Instantiate the 4-bit full adder. call it FA1_4 fulladd FA1(SUM, C_OUT, A, B, C_IN); // Setup the monitoring for the signal values initial begin JITS Page 52
Department Of ECE $monitor($time," A= %b, B=%b, C_IN= %b, C_OUT=%b,SUM= %b\n",A,B,C_IN,C_OUT,SUM); end initial begin A = 4'd0; B = 4'd0; C_IN = 1'b0; #50 A = 4'b0; B = 4'b0;C_IN=1'b1; #50 A = 4'b0; B = 4'b1;C_IN=1'b0; #50 A = 4'b0; B = 4'b1;C_IN=1'b1; #50 A = 4'b1; B = 4'b0;C_IN=1'b0; #50 A = 4'b1; B = 4'b0;C_IN=1'b1; #50 A = 4'b1; B = 4'b1;C_IN=1'b1; end endmodule //define a 4-bit full adder module fulladd4(sum, c_out, a, b, c_in); //i/o port declaration output [3:0] sum; output c_out; input[3:0] a, b; input c_in; //internal net wire c1, c2, c3; fulladd fa0(sum[0], c1, a[0], b[0], c_in); fulladd fa1(sum[1], c2, a[1], b[1], c1); fulladd fa2(sum[2], c3, a[2], b[2], c2); fulladd fa3(sum[3], c_out, a[3], b[3], c3); endmodule JITS Page 53
Department Of ECE define the stimulus module module stimulus; //declare variables to be connected reg [3:0] A, B; reg C_IN; wire [3:0] SUM; wire C_OUT; fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN); verilog code for dff module dff(clk, d, q); input clk, d; output reg q; always @(posedge clk) q <= d; endmodule module DFFAsyncClr(D, clk, resetn, Q, presetn); input D, clk, resetn, presetn; output Q; reg Q; always@(posedge clk or negedge resetn or negedge presetn) if(!resetn) Q <= 0; else if(!presetn) Q <= 1; else Q <= D; endmodule module Reg32(Q, D, clk, reset_); JITS Page 54
Department Of ECE //********************************************************* output [31:0] Q; input [31:0] D; input clk, reset_; reg [31:0] Q; always @(posedge clk or negedge reset) if (!reset_) Q <= 32'b0; else Q <= D; Endmodule module Test_Reg1; //********************************************************* wire [31:0] OutReg; reg [31:0] Din; reg clk, reset_; // Instantiate Reg32 (named DUT {device under test}) Reg32 DUT(OutReg, Din, clk, reset_); initial begin $timeformat(-9, 1, " ns", 6); clk = 1’b0; reset_ = 1’b1; // deassert reset t=0 #3 reset_ = 1’b0; // assert reset t=3 #4 reset_ = 1’b1; // deassert reset t=7 @(negedge clk) //will wait for next negative edge of the clock (t=20) Din = 32'hAAAA5555; @(negedge clk) //will wait for next negative edge of the clock (t=40) Din = 32'h5F5F0A0A; JITS Page 55
Department Of ECE @(negedge clk) //will wait for next negative edge of the clock (t=60) Din = 32'hFEDCBA98; @(negedge clk) //will wait for next negative edge of the clock (t=80) reset_ = 1’b0; @(negedge clk) //will wait for next negative edge of the clock (t=100) reset_ = 1’b1; @(negedge clk) //will wait for next negative edge of the clock (t=120) Din = 32'h76543210; @(negedge clk) //will wait for next negative edge of the clock (t=140) $finish; // to kill the simulation end // This block generates a clock pulse with a 20 ns period. // Rising edges at 10, 30, 50, 70 .... Falling edges at 20, 40, 60, 80 .... always #10 clk = ~ clk; // this block is sensitive to changes on clk or reset and will // then display both the inputs and corresponding output always @(posedge clk or reset_) #1 $display("At t=%t / Din=%h OutReg=%h" , $time, Din, OutReg); Endmodule Verilog program for seven segment module SevSegCase(aIn, sOut); input [3:0]aIn; output [6:0]sOut; reg [6:0]sOut; always @(aIn) begin JITS Page 56
Department Of ECE case (aIn) // abcdefg 4'b0000:sOut = 7'b0000001; //0 4'b0001:sOut = 7'b1001111; //1 4'b0010:sOut = 7'b0010010; //2 4'b0011:sOut = 7'b0000110; //3 4'b0100:sOut = 7'b1001100; //4 4'b0101:sOut = 7'b0100100; //5 4'b0110:sOut = 7'b0100000; //6 4'b0111:sOut = 7'b0001111; //7 4'b1000:sOut = 7'b0000000; //8 4'b1001:sOut = 7'b0001100; //9 4'b1010:sOut = 7'b0001000; //A 4'b1011:sOut = 7'b1000010; //B 4'b1100:sOut = 7'b0000111; //C 4'b1101:sOut = 7'b0000001; //D 4'b1110:sOut = 7'b0110000; //E 4'b1111:sOut = 7'b0000110; //F endcase end endmodule jk ff:
module jkff(J, K, clk, Q); JITS Page 57
Department Of ECE input J, K, clk; output Q; reg Q; reg Qm; always @(posedge clk) if(J == 1 && K == 0) Qm <= 1; else if(J == 0 && K == 1) Qm <= 0; else if(J == 1 && K == 1) Qm <= ~Qm; // always @(negedge clk) Q <= Qm; endmodule
//n-bit parallel in/parallel out // with tri-state out. module RegnBit(dIn, dOut, clk, enable); JITS Page 58
Department Of ECE parameter n = 8; input [n-1:0]dIn; input clk, enable; output [n-1:0] dOut; reg [n-1:0] dOut; reg [n-1:0] state; always @(enable) begin if(enable) dOut = state; //data to out else dOut = n'bz; //tri-state out end always @(posedge clk) state <= dIn; endmodule //n-bit parallel in/parallel out // with tri-state out. module RegnBit(dIn, dOut, clk, enable); parameter n = 8; input [n-1:0]dIn; input clk, enable; output [n-1:0] dOut; reg [n-1:0] dOut; reg [n-1:0] state; always @(enable) begin if(enable) JITS Page 59
Department Of ECE dOut = state; //data to out else dOut = n'bz; //tri-state out end always @(posedge clk) state <= dIn; endmodule //n-bit parallel in/parallel out // with tri-state out. module RegnBit(dIn, dOut, clk, enable); parameter n = 8; input [n-1:0]dIn; input clk, enable; output [n-1:0] dOut; reg [n-1:0] dOut; reg [n-1:0] state; always @(enable) begin if(enable) dOut = state; //data to out else dOut = n'bz; //tri-state out end always @(posedge clk) state <= dIn; endmodule //n-bit parallel in/parallel out // with tri-state out. JITS Page 60
Department Of ECE module RegnBit(dIn, dOut, clk, enable); parameter n = 8; input [n-1:0]dIn; input clk, enable; output [n-1:0] dOut; reg [n-1:0] dOut; reg [n-1:0] state; always @(enable) begin if(enable) dOut = state; //data to out else dOut = n'bz; //tri-state out end always @(posedge clk) state <= dIn; endmodule //CntSeq.v //Sequence counter module CntSeq(clk, reset, state); parameter n = 4; input clk, reset; output [n-1:0]state; reg [n-1:0]state; // always @(posedge clk) if(reset) state = 0; else JITS Page 61
Department Of ECE begin case (state) 4'b0000:state = 4'b0001; //0 -> 1 4'b0001:state = 4'b0010; //1 -> 2 4'b0010:state = 4'b0100; //2 -> 4 4'b0100:state = 4'b1001; //4 -> 9 4'b1001:state = 4'b1010; //9 -> 10 4'b1010:state = 4'b0101; //10-> 5 4'b0101:state = 4'b0110; //5 -> 6 4'b0110:state = 4'b1000; //6 -> 8 4'b1000:state = 4'b0111; //8 -> 7 default:state = 4'b0000; endcase end endmodule Figure 14 A case statement is used to implement a sequence counter //ShiftMultiple //This file uses multiple modules for dual shift s // of differing lengths module ShiftMultiple(sIn, sOut, clk); input [2:0] sIn; input clk; output [2:0]sOut; Shiftn Shift4 (clk, sIn[0], sOut[0]); //defaults to n = 4 Shiftn Shift6(clk, sIn[1], sOut[1]); defparam Shift6.n = 6; //resets n to 6 Shiftn Shift12(clk, sIn[2], sOut[2]); JITS Page 62
Department Of ECE defparam Shift12.n = 12; //resets n to 12 endmodule // //Shiftn //n-bit shift serial in serial out module Shiftn(clk, sIn, sOut); parameter n = 4; //number of stages input sIn, clk; output sOut; reg sOut; reg [n-1:0]state; always @(posedge clk) // sIn -> [0|1|...|n-1] -> sOut begin sOut <= state[n-1]; state <= {state[n-2:0], sIn}; end endmodule module fundecode(aIn, yOut, enable); input [1:0] aIn; input enable; output [3:0]yOut; reg [3:0] yOut; // function [3:0]FindOutput; input [1:0]xIn; if(~xIn[1] && ~xIn[0]) FindOutput = 4'b0111; if(~xIn[1] && xIn[0]) FindOutput = 4'b1011; if(xIn[1] && ~xIn[0]) FindOutput = 4'b1101; JITS Page 63
Department Of ECE if(xIn[1] && xIn[0]) FindOutput = 4'b1110; endfunction // always@(aIn or enable) begin if(enable == 1) begin yOut = FindOutput(aIn); end else yOut = 4'b1111; end endmodule module taskdecode(aIn, yOut, enable); input [1:0] aIn; input enable; output [3:0]yOut; reg [3:0] yOut; // task FindOutput; input [1:0]xIn; output [3:0] tOut if(~xIn[1] && ~xIn[0]) tOut = 4'b0111; if(~xIn[1] && xIn[0]) tOut = 4'b1011; if(xIn[1] && ~xIn[0]) tOut = 4'b1101; if(xIn[1] && xIn[0]) tOut = 4'b1110; endtask // JITS Page 64
Department Of ECE always@(aIn or enable) begin if(enable == 1) begin FindOutput(aIn, yOut); end else yOut = 4'b1111; end endmodule module flif_flop (clk,reset, q, d); 2 input clk, reset, d; 3 output q; 4 reg q; 5 6 always @ (posedge clk ) 7 begin 8 if (reset == 1) begin 9 q <= 0; 10 end else begin 11 q <= d; 12 end 13 end 15 endmodule VHDL CODE FOR FULL AADDER DATAA FLOW: Full Adder A B C Ci S Co 00000 JITS Page 65
Department Of ECE EXXPRESSIONS: 00 110 01 010 B Ci S= =A 01 101 B)Ci + AB CO O = (A 10 010 10 101 11 001 11 111 Libraary IEEE; use IEEE.STD_LOOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; JITS Page 66
Department Of ECE entity fa1 is Port ( a,b,ci : in STD_LOGIC; s,,co : out STD_LOGIC); end fa1; architecture Behavioral of fa1 is begin s<=a xor b xor ci; co<=(a and b)or (b and ci)or (ci and a); end Behavioral; VHDL CODE FOR FULL ADDER BEHAVIORAL: : libraary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fa1 is Port ( a,b,ci : in STD_LOGIC; s,,co : out STDD_LOGIC); end fa1; archhitecture Behavioral of fa1 is begin process(a,b,ci) begin s<=a xor b xor ci; co<=(a and b)or (b and ci)or (ci and a); end process; JITS Page 67
Department Of ECE end Behavioral; VHDL CODE FOR FULL ADDER STRUCTURAL: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fa1 is Port ( a,b,cin : in STD_LOGIC; s,cout : out STD_LOGIC); end fa1; architecture struct of fa1 is component and21 port(a,b:in std_logic; ---components, entity and architecture c:out std_logic); --- must be declared separately end component; component xor21 port(a,b:in std_logic; ---components, entity and architecture --- must be declared separately c:out std_logic); end component; component or31 port(a,b:in std_logic; ---components, entity and architecture d:out std_logic); --- must be declared separately end component; signal s1,s2,s3:std_logic; begin u1:xor21 port map(a,b,s1); u2:xor21 port map(s1,cin,s); JITS Page 68
Department Of ECE u3:and21 port map(a,b,s2); u4:and21 port map(s1,cin,s3); u6:or31 port map(s2,s3,cout); end struct; VHDL CODE FOR MULTIPLEXER (8:1): INPUTS SELECTLINES O/P d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) s(2) s(1) s(0) f XX X X X X X 0 0 0 0 0 XXXXXXX10001 XXXXXX0X0010 XXXXXX1X0011 XXXXX0XX0100 XXXXX1XX0101 XXXX0XXX0110 XXXX1XXX0111 XXX0XXXX1000 XXX1XXXX1001 XX0XXXXX1010 XX1XXXXX1011 X0XXXXXX1100 X1XXXXXX1101 0XXXXXXX1110 1XXXXXXX1111 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux1 is JITS Page 69
Department Of ECE Port ( d : in STD_LOGIC_VECTOR (7 downto 0); s : in STD_LOGIC_VECTOR (2 downto 0); f : out STD_LOGIC); end mux1; architecture Behavioral of mux1 is begin f<= d(0) when s="000" else d(1) when s="001" else d(2) when s="010" else d(3) when s="011" else d(4) when s="100" else d(5) when s="101" else d(6) when s="110" else d(7) when s="111"; end Behavioral; VHDL CODE FOR Demultiplexer (1:8): SELECT LINES I/P OUTPUT s(2) s(1) s(0) f d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) 0000XXXXXXX0 0001XXXXXXX1 0010XXXXXX0X 0011XXXXXX1X 0100XXXXX0XX 0101XXXXX1XX 0110XXXX0XXX 0111XXXX1XXX 1000XXX0XXXX 1001XXX1XXXX JITS Page 70
Department Of ECE 1010XX0XXXXX 1011XX1XXXXX 1100X0XXXXXX 1101X1XXXXXX 11100XXXXXXX 11111XXXXXXX
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dmux is port(f:in std_logic; s:in std_logic_vector(2 downto 0); y:out std_logic_vector(7 downto 0)); end demux; architectural behavioral of dmux is begin y(0)<=f when s="000"else'0'; y(1)<=f when s="001"else'0'; y(2)<=f when s="010"else'0'; y(3)<=f when s="011"else'0'; y(4)<=f when s="100"else'0'; y(5)<=f when s="101"else'0'; y(6)<=f when s="110"else'0'; y(7)<=f when s="111"else'0'; end behavioral; JITS Page 71
Department Of ECE VHDL CODE FOR ENCODER WITHOUT PRIORITY (8:3): SELECT LINES OUTPUT s(2) s(1) s(0) y(7) y(6) y(5) y(4) y(3) Y(2) y(1) y(0) 00000000001 00100000010 01000000100 01100001000 10000010000 10100100000 11001000000 111XXXXXXXX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity enco is Port ( i : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0)); end enco; architecture Behavioral of enco is begin with i select y<="000" when "00000001", "001" when "00000010", "010" when "00000100", "011" when "00001000", "100" when "00010000", "101" when "00100000", JITS Page 72
Department Of ECE "110" when "01000000", "111" when others; end Behavioral; VHDL CODE FOR ENCODER WITH PRIORITY (8:3): SELECT LINES OUTPUT s(2) s(1) s(0) y(7) y(6) y(5) y(4) y(3) y(2) y(1) y(0) 00000000111 00100000110 01000000101 01100000001 10000000110 1 0 1 0- 0 0 0 0 0 1 0 11000000100 111XXXXXXXX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity enco1 is Port ( i : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0)); end enco1; architecture Behavioral of enco1 is begin with i select y<="000" when "00000111", "001" when "00000110", "010" when "00000101", JITS Page 73
Department Of ECE "011" when "00000100", "100" when "00000011", "101" when "00000010", "110" when "00000001", "111" when others; end Behavioral; 7.VHDL CODE FOR 3:8 DECODER: SELECT LINES OUTPUT s(2) s(1) s(0) y(7) y(6) y(5) y(4) y(3) y(2) y(1) y(0) 00000000001 00100000010 01000000100 01100001000 10000010000 10100100000 11001000000 11110000000 XXX00000000 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec1 is Port ( s : in STD_LOGIC_VECTOR (2 downto 0); y : out STD_LOGIC_VECTOR (7 downto 0)); end dec1; architecture Behavioral of dec1 is JITS Page 74
Department Of ECE begin with sel select y<="00000001" when "000", "00000010" when "001", "00000100" when "010", "00001000" when "011", "00010000" when "100", "00100000" when "101", "01000000" when "110", "10000000" when "111", "00000000" when others; end Behavioral;
8.VHDL CODE FOR 2-bit comparator: A1 A0 B1 B0 Y1 (A > B) Y2 (A = B) Y3 (A < B) 0000010 0001001 0010001 0011001 0100100 0101010 JITS Page 75
Department Of ECE 0110001 0111001 1000100 1001100 1010010 1011001 1100100 1101100 1110100 1111010 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp is Port ( a,b : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0)); end comp; architecture Behavioral of comp is begin y<= "100" when a>b else "001" when a
Department Of ECE G(1)=B(1) B(2) G(2)=B(2) B(3) G(3)=B(3) Inputs Outputs B (3) B (2) B (1) B (0) G (3) G (2) G (1) G (0) 00000000 00010001 00100011 00110010 01000110 01010111 01100101 01110100 10001100 10011101 10101111 10111110 11001010 11011011 11101001 11111000
library IEEE; use IEEE.STD_LOGIC_1164.ALL; JITS Page 77
Department Of ECE use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Binary_Gray is port( b: in std_logic_vector(3 downto 0); --Binary Input g: out std_logic_vector(3 downto 0)); --Gray Output end binary_gray; architecture behavioral of Binary_gray is begin b(3)<= g(3); b(2)<= g(3) xor g(2); b(1)<= g(2) xor g(1); b(0)<= g(1) xor g(0); end behavioral; VHDL CODE FOR GRAY TO BINARY: CIRCUIT DIAGRAM:
EXPRESSIONS:
B(0)=G(0) G(1) G(2) G(3) B(1)=G(1) G(2) G(3) B(2)=G(2) G(3) B(1)=G(3) INPUT OUTPUT G(3) G(2) G(1) G(0) B (3) B (2) B (1) B (0) JITS Page 78
Department Of ECE 00000000 00010001 00110010 00100011 01100100 01110101 01010110 01000111 11001000 11011001 11111010 11101011 10101100 10111101 10011110 10001111 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gb1 is Port ( g : in STD_LOGIC_VECTOR (3 downto 0); b : out STD_LOGIC_VECTOR (3 downto 0)); end gb1; architecture Behavioral of gb1 is begin b(3)<= g(3); b(2)<= g(3) xor g(2); JITS Page 79
Department Of ECE b(1)<= g(3) xor g(2) xor g(1); b(0)<= g(3) xor g(2) xor g(1) xor g(0); end behavioral; VHDL CODE FOR JK FLIP FLOP WITH ASYNCHRONOUS RESET: (Master Slave JK Flip-Flop) Reset J K Clock Qn+1 Status Qn + 1 1 X X X 0 1 Reset 0 0 0 Qn No Change Qn 0 0 1 0 1 Reset 0 1 0 1 0 Set 011 Qn Toggle Qn library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff1 is Port ( j,k,clk,reset : in STD_LOGIC; Q : inout STD_LOGIC); end jkff1; JITS Page 80
Department Of ECE architecture Behavioral of jkff1 is signal div:std_logic_vector(22 downto 0); signal clkd:std_logic; begin process(clk) begin if rising_edge(clk)then div<= div+1; end if; end process; clkd<=div(22); process(clkd,reset) begin if(reset='1')then Q<= '0'; elsif(clkd'event and clkd='1')then if(j='0' and k ='0')then Q<= Q; elsif(j='0' and k='1')then Q<= '0'; elsif(j='1' and k='0')then Q<= '1'; elsif(j='1' and k='1')then Q<= not Q; end if; end if; end process; end Behavioral; JITS Page 81
Department Of ECE VHDL CODE FOR T FLIP FLOP: + Qn 1 Clear T Clock Qn+1 Qn 1000 Qn 01 Qn library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t,clk,rst : in STD_LOGIC; q : inout STD_LOGIC); end tff; architecture Behavioral of tff is signal div:std_logic_vector(22 downto 0); signal clkd:std_logic; begin process(clk) begin if rising_edge(clk)then div<= div+1; end if; JITS Page 82
Department Of ECE end process; clkd<=div(20); process(clkd,rst) begin if(rst='1')then q<='0'; elsif (clkd'event and clkd='1' and t='1') then q<= not q; else q<=q; end if; end process; end Behavioral; VHDL CODE FOR D FLIP FLOP: + Qn 1 Clear D Clock Qn+1 10001 0110 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is Port ( d,res,clk : in STD_LOGIC; q : out STD_LOGIC); end dff; JITS Page 83
Department Of ECE architecture Behavioral of dff is begin process(clk) begin if (res ='1')then q<='0'; elsif clk'event and clk='1' then q<=d; end if; end process; end Behavioral; ASYNCHRON NOUS BINARRY UP COUNTER: 3-bit t Asynchrono ous up countter Cloock QC QB Q QA 0 00 00 0 1 10 01 1 2 20 10 0 JITS Page 84
Department Of ECE 3 30 11 1 4 41 00 0 5 51 01 1 6 61 10 0 7 71 11 1 8 80 00 0 9 90 01 1 JITS Page 85
Department Of ECE libraary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity asybin1 is Port ( rs,clk : in STD_LOGIC; q : inout STD__LOGIC_VECTOR (3 downto 0)); end asybin1; architecture Behavioral of asybin1 is signal div:std_logic_vector(22 downto 0); signal temp:STD_LOGIC_VECTOR (3 downto 0); signal clkd:std_logic; begin process(clk) begin if rising_edge(clk)then div<= div+1; end if; end process; clkd<=div(22); proccess(clkd,rs) begin if(rs='1'))then temp<=(others=>'00'); --for down counnter temp=>"1111"; elsif(clkdd='1' and clkd'event) then JITS Page 86
Department Of ECE temp<=t temp+1; --for down counter temp<= temp-1; q<= temp; end if; end process; end Behavioral; SYNCHRONOOUS BINARYY UP COUNTER: 3-bit t Asynchronous up counter Clock QC QB QAA 0 00 00 0 1 10 01 1 2 20 10 0 3 30 11 1 JITS Page 87
Department Of ECE 4 41 00 0 5 51 01 1 6 61 10 0 7 71 11 1 8 80 00 0 9 90 01 1 libraary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; JITS Page 88
Department Of ECE use IEEE.STD_LOGIC_UNSIGNED.ALL; entity synbicount is Port ( rs,clk : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 down to 0)); end synbicount; architecture Behavioral of synbicount is signal div:std_logic_vector(22 downto 0); signal temp:STD_LOGIC_VECTOR (3 downto 0); signal clkd:std_logic; begiin process(clk) begin if rising edge(clk)then div<= div+1; end if; end process; clkd<=div(22); process(clkd) begin if(clkd='1' and clkd'event) then if(rs='1'))then temp<=(others=>'00'); ---for down counter temp<="11111" ---for do own counter else temp<=temp+1; temp<= temp-1; end if; q<= temp; JITS Page 89
Department Of ECE end if; end process; end Behavioral; BCD UP COUNTER: Clock QD QC QB QA 00000 10001 20010 30011 40100 50101 60110 70111 81000 91001 10 0 0 0 0 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcdupcount is Port ( clk,rst : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end bcdupcount; architecture Behavioral of bcdupcount is signal div:std_logic_vector(22 downto 0); signal clkd:std_logic; JITS Page 90
Department Of ECE begin process(clkd) begin if rising_edge(clk)then div<= div+1; end if; end process; clkd<=div(22); process(clkd,rst) begin if rst='0' or q="1010" then q<="0000"; elsif clkd'event and clkd='1' then q<=q+1; end if; end process; q<=q; end Behavioral; BCD DOWN COUNTER: Clock QD QC QB QA 01001 11000 20111 30110 40101 50100 60011 70010 JITS Page 91
Department Of ECE 80001 90000 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcddowncounter1 is Port ( clk,rst : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end bcddowncounter1; architecture Behavioral of bcddowncounter1 is signal div:std_logic_vector(22 downto 0); signal clkd:std_logic; begin process(clkd) begin if rising_edge(clk)then div<= div+1; end if; end process; clkd<=div(22); process(clkd,rst) begin if rst='0' or q="1111" then q<="1001"; elsif clkd'event and clkd='1' then q<=q-1; JITS Page 92
Department Of ECE end if; end process; q<=q; end Behavioral; VHDL CODE FOR SEVEN SEGMENT DISPLAY INTERFACE Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Use ieee.std_logic_arith.all; Entity mux_disp is Port (clk:in std_logic ---4mhz
JITS Page 93
Department Of ECE rst: in std_logic; seg: out std_logic_vector(6 downto 0) base: out std_logic_vector(3 downto 0)); end mux_disp; architecture mux_disp_arch of mux_disp is signal count : std_logic_vector(25 downto 0); signal base_cnt: std_logic_vector(1 downto 0); signal seg_cnt: std_logic_vector(3 downto 0); begin process(clk,rst) begin if rst = '1' then count<=(others=>'0'); elsif clk='1' and clk'event then count<= + '1'; end if; end process; base_cnt<=count(12 downto11); seg_cnt<=count(25 downto 22); Base<= "1110" when base_cnt="00" else "1101" when base_cnt="01" else "1011" when base_cnt="10" else "0111" when base_cnt="11" else "1111"; Seg<= "0111111" when seg_cnt="0000" else ---0 "0000110" when seg_cnt="0001" else ---1 "1011011" when seg_cnt="0010" else ---2 JITS Page 94
Department Of ECE "1001111" when seg_cnt="0011" else ---3 "1100110" when seg_cnt="0100" else ---4 "1101101" when seg_cnt="0101" else ---5
JITS Page 95
Department Of ECE "1111101" when seg_cnt="0110" else ---6 "0000111" when seg_cnt="0111" else ---7 "1111111" when seg_cnt="1000" else ---8 "1100111" when seg_cnt="1001" else ---9 "1110111" when seg_cnt="1010" else ---A "1111100" when seg_cnt="1011" else ---B "0111001" when seg_cnt="1100" else ---C "1011110" when seg_cnt="1101" else ---D "1111001" when seg_cnt="1110" else ---E "1110001" when seg_cnt="0000" else ---F "0000000"; End mux_disp_arch; VHDL CODE FOR MULTIPLEXER (4:1)(STRUCTURAL): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( i0,i1,i2,i3,s0,s1 : in STD_LOGIC; y : out STD_LOGIC); end mux; architecture struct of mux is component and1 ----components, entity and architecture port (l,m,u:in std_logic;n:out std_logic); --- must be declared separately end component; component or1 ----components, entity and architecture port (o,p,x,y:in std_logic;q:out std_logic); --- must be declared separately JITS Page 96
Department Of ECE end component; component not1 ----components, entity and architecture port (r:in std_logic;s:out std_logic); --- must be declared separately end component; signal s2,s3,s4,s5,s6,s7:std_logic; begin u1:and1 port map(i0,s2,s3,s4); u2:and1 port map(i1,s2,s1,s5); u3:and1 port map(i2,s0,s3,s6); u4:and1 port map(i3,s0,s1,s7); u5:not1 port map(s0,s2); u6:not1 port map(s1,s3); u7:or1 port map(s4,s5,s6,s7,y); end struct; VHDL CODE FOR BINARY TO GRAY (Structural): library IEEE; use IEEE E.STD_LOGIC _1164.ALL; use IEEE E.STD_LOGIC _ARITH.ALL; use IEEE E.STD_LOGIC _UNSIGNED .ALL; entity bg is Port ( b : in STD_LOGIC__VECTOR (3 downto 0); g : out STD__LOGIC_VECT TOR (3 downto 0)); end bg; architecture struct of bg is component xor1 port(a, b:in std_logic; ----components, entity and architecture c:out std_logic); JITS Page 97
Department Of ECE --- must be declared separately end compon nent; component and1 port(d,e:in std_logic; ----components, entity and architecture --- must f:out std_logic); must be declared separately end component; begin u1:and1 porrt map(b(3),bb(3),g(3)); u2:xor1 portt map(b(3),bb(2),g(2)); u3:xor1 portt map(b(2),b b(1),g(1)); u4:xor1 portt map(b(1),bb(0),g(0)); end struuct; VHDL CODE : FOR GRAY TO BINARY (Structural): library IEEE; use IEEE.STD D_LOGIC_11 64.ALL; use IEEE.STD _LOGIC_AR ITH.ALL; use IEEE.STD _LOGIC_UN SIGNED.ALL; entity gb is Port( g : in STD_ _LOGIC_VEC CTOR (3 downto 0); b : out STD_LOGIC_VECTOR R (3 downto 0)); end gb; architecture struct of gb is ----component xor1 port(a,b:in std_logic; JITS Page 98
Department Of ECE architecture c:ouut std_logic); --- must be declared separately end component ; component and 1 port(d,e:in std_logic; components, entity and architecture --- must be d f:out std_logic); declared separately end component; component xor1 12 port(g,h,i: :in std_logic; ; ---components, entity and architecture --- must be d k:out std_logic); declared separately end component; component xor13 port(l,m,n,o:in std_logic; ----components, entity and architecture:out std_logic); --- must be declared separately end component ; begin u1:and1 port map(g(3),g(3),b(3)); u2:xor1 port map(g(3),g(2),b(2)); u3:xor12 port map(g(3), g(2),g(1),b(1)); u4:xor13 port map(g(3), g(2),g(1),g(0),b(0)); end struct; JITS Page 99
Department Of ECE VHDL CODE FOR DECODER (Structural): Y (0 ) Y (1 ) Y (2 ) Y (3 ) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec is Port ( a,b : in STD_LOGIC; y: out STD_LOGIC_VECTOR (3 downto 0)); end dec; architecture Behavioral of dec is component and1 is ----components, entity and architecture port(p,q:in std_logic;r:out std_logic); --- must be declared separately end component; component not1 is ----components, entity and architecture port (d:in std_logic;e:out std_logic); --- must be declared separately end component; signal s1,s2:std_logic; begin u1:and1 port map(s1,s2,y(0)); u2:and1 port map(s1,b,y(1)); u3:and1 port map(a,s2,y(2)); u4:and1 port map (a,b,y(3)); JITS Page 100
Department Of ECE u5:not1 port map(a,s1); u6:not1 port map(b,s2); end Behavioral 26. VHDL CODE FOR D FLIP FLOP (Structural): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff1 is Port ( d,clk,pr,clr : in STD_LOGIC; q,qn : inout STD_LOGIC); end dff1; architecture struct of dff1 is component clkdiv is ----components, entity and architecture port(clk:in std_logic;clk_d:out std_logic); --- must be declared separately end component; component nand1 is port(a,b,c:in std_logic; ----components, entity and architecture d:out std_logic); --- must be declared separately end component; component nand12 is port(x,y:in std_logic; ----components, entity and architecture z:out std_logic); --- must be declared separately end component; component nand13 is port(e:in std_logic; ----components, entity and architecture f:out std_logic); --- must be declared separately JITS Page 101
Department Of ECE end component; signal s1,s2,s3,s4,s5,s6,s7,s8,s9:std_logic; begin u10:clkdiv port map(clk,s7); u1:nand1 port map(d,s7,qn,s1); u2:nand1 port map(s9,s7,q,s2); u3:nand1 port map(pr,s1,s4,s3); u4:nand1 port map(s2,clr,s3,s4); u5:nand12 port map(s3,s8,s5); u6:nand12 port map(s8,s4,s6); u7:nand12 port map(s5,qn,q); u8:nand12 port map(s6,q,qn); u9:nand13 port map(s7,s8); u11:nand13 port map(d,s9); end struct;
27. VHDL CODE FOR JK FLIP FLOP (Structural): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff is Port ( j,k,clk,pr,clr : in STD_LOGIC; q,qn : inout STD_LOGIC); end jkff; architecture struct of jkff is JITS Page 102
Department Of ECE component clkdiv is ----components, entity and architecture port(clk:in std_logic;clk_d:out std_logic); --- must be declared separately end component; component nand1 is ----components, entity and architecture port(a,b,c:in std_logic; --- must be declared separately d:out std_logic); end component; component nand12 is ----components, entity and architecture port(x,y:in std_logic; --- must be declared separately z:out std_logic); end component; component nand13 is port(e:in std_logic; ----components, entity and architecture f:out std_logic); --- must be declared separately end component; signal s1,s2,s3,s4,s5,s6,s7,s8:std_logic; begin u10:clkdiv port map(clk,s7); u1:nand1 port map(j,qn,s7,s1); u2:nand1 port map(k,s7,q,s2); u3:nand1 port map(pr,s1,s4,s3); u4:nand1 port map(s2,clr,s3,s4); u5:nand12 port map(s3,s8,s5); u6:nand12 port map(s8,s4,s6); u7:nand12 port map(s5,qn,q); u8:nand12 port map(s6,q,qn); u9:nand13 port map(s7,s8); end struct; JITS Page 103
Department Of ECE VHDL CODE FOR T FLIP FLOP (Structural): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff1 is Port ( t,clk,pr,clr : in STD_LOGIC; q,qn : inout STD_LOGIC); end tff1; architecture struct of tff1 is component clkdiv is ----components, entity and architecture port(clk:in std_logic;clk_d:out std_logic); --- must be declared separately end component; component nand1 is port(a,b,c:in std_logic; ----components, entity and architecture d:out std_logic); --- must be declared separately end component; component nand12 is port(x,y:in std_logic; ----components, entity and architecture z:out std_logic); --- must be declared separately end component;
JITS Page 104
Department Of ECE component nand13 is port(e:in std_logic; ----components, entity and architecture f:out std_logic); --- must be declared separately end component; signal s1,s2,s3,s4,s5,s6,s7,s8:std_logic; begin u10:clkdiv port map(clk,s7); u1:nand1 port map(t,qn,s7,s1); u2:nand1 port map(t,s7,q,s2); u3:nand1 port map(pr,s1,s4,s3); u4:nand1 port map(s2,clr,s3,s4); u5:nand12 port map(s3,s8,s5); u6:nand12 port map(s8,s4,s6); u7:nand12 port map(s5,qn,q); u8:nand12 port map(s6,q,qn); u9:nand13 port map(s7,s8); end struct; 1 BIT COMPARATOR (structural): Y2 Y3 A B Y1 (A>B) (A = B) (A < B) 00010 01001 10100 11010 JITS Page 105
Department Of ECE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp is Port ( a,b : in STD_LOGIC; y : out STD_LOGIC_VECTOR (2 downto 0)); end comp; architecture struct of comp is component and1 port(l,m:in std_logic; ----components, entity and architecture n:out std_logic); --- must be declared separately end component; component xnor1 is port(p,q:in std_logic; ----components, entity and architecture r:out std_logic); --- must be declared separately end component; component notgate1 is port(s:in std_logic; ----components, entity and architecture t:out std_logic); --- must be declared separately end component; signal s1,s2:std_logic; begin u1:and1 port map(a,s2,y(0)); u2:and1 port map(s1,b,y(1)); u3:xnor1 port map(a,b,y(2)); u4:notgate1 port map(a,s1); JITS Page 106
Department Of ECE u5:notgate1 port map(b,s2); end struct;
JITS Page 107
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