Esquema Placa Mae 810 Celeron 2q6643

8

7

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5

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1

INTEL(R) CELERON(TM) PROCESSOR (PPGA)/INTEL(R) 810 CHIPSET UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS REVISION 1.3 D

C

B

A

D

TITLE

PAGE

Cover Sheet Block Diagram 370-Pin Socket GTL Termination Clock Synthesizer GMCH Frame Buffer DIMM Sockets ICH0 FWH Super I/O PCI Connectors ATA33 IDE Connectors USB Connectors Parallel Port Serial/Game Ports Keyboard/Mouse/Floppy Disk Digital Video Out (TBD) Graphics Connectors AC’97 Riser Connector LAN System Voltage Regulators Processor Voltage Regulator System Pullup Resistors and Unused Gates Decoupling

1 2 3,4 5 6 7,8,9 10 11,12 13,14 15 16 17,18 19 20 21 22 23 24 25 26 27,28 29 30 31,32 33 34,35

** PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE

TH ESE SC HEM AT IC S ARE PRO VIDED “AS IS” W ITH N O W ARRANT IES W HATSO EVER, INCLUDIN G ANY W AR RANT Y O F M ERCH ANT ABILIT Y, FIT NESS FO R ANY PART ICULAR PUR PO SE, O R ANY W ARR ANT Y O THERW ISE ARISING O UT O F PR O PO SAL, SPECIFIC AT IO N O R SAM PLES. Inform ation in this docum ent is provided in connection with Intel products. No license, express or im plied, by estoppel or otherwise, to any intellectual property rights is granted by this docum ent. Except as provided in Intel's T erm s and Conditions of Sale for such products, Intel assum es no liability whatsoever, and Intel disclaim s any express or im plied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, m erchantability, or infringem ent of any patent, copyright or other intellectual property right. Intel products are not intended for use in m edical, life saving, or life sustaining applications. Intel m ay m ake changes to specifications and product descriptions at any tim e, without notice. The Intel Celeron TM processor and Intel 810 chipset m ay contain design defects or errors known as errata which m ay cause the product to deviate from published specifications. Current characterized errata are available on request.

*Third-party brands and nam es are the property of their respective owners.

A

REV:

1.3

COVER SHEET DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

7

6

B

Copyright © Intel Corporation 1998.

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

8

C

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

5-26-1999_17:09 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

1

OF

40

8

7

6

5

4

3

2

1

Block Diagram D

Device Table

D

VRM

370-Pin Socket Processor

Clock

DATA

CTRL

ADDR

DATA

CTRL

ADDR

Term

Display Cache Memory

2 DIMM Modules

GMCH Digital Video Out Device

C

IDE Primary

UltrA/33

PCI ADDR/DATA

USB

USB Port 2

LPC Bus

AMC’97 Audio/Modem

AC’97 Link

PCI CONN 3

ICH0 USB Port 1

PCI CONN 2

PCI CONN 1

PCI CNTRL IDE Secondary

PCI CNTRL PCI ADDR/DATA

LAN

B

SIO

REFERENCE DESIGNATOR U12 U16,U17 U15 U3 U1 U2 U14 U7 U13 U8,U9 U10 U6 U18 U4 U5 U11 VR2,VR3 VR4 VR1 VR5

DEVICE TYPE 74lvc14a gd75232 lpc47b27_a 74lvc06a ck-whitney 82810-DC100 82801AB sii-dfp 82559 1x16sdram 74lvc08a qst3384 93c46 74ls132 74lvc07a 74lvc07a lt1587ad lt1117_3 ltc1753 lt1585ad

SHEET NUMBER 32 22 16 29,32 6 7,8,9 13,14 24 27 10 32 25 27 29,32 29,31 19,31 29 29 30 29

GATES USED A,B,C,D

A,B,C,D

A,B

A,B A,B,C A,B,C

C

B

FirmWare Hub

Keyboard

Floppy

Parallel

Game Conn

Mouse Serial 1

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

BLOCK DIAGRAM DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:43 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

2

OF

40

8

7

6

2

1

HD#31

C5

HD#32

F6

HD#33

C1

HD#34

C7

HD#35

B2

HD#36

C9

HD#37

A9

HD#38

D8

HD#39

D10

HD#40

C15

HD#41

D14

HD#42

D12

HD#43

A7

HD#44

A11

HD#45

C11

HD#46

A21

HD#47

A15

HD#48

A17

HD#49

C13

HD#50

C25

HD#51

A13

HD#52

D16

HD#53

A23

HD#54

C21

HD#55

C19

HD#56

C27

HD#57

A19

HD#58

C23

HD#59

C17

HD#60

A25

HD#61

A27

HD#62

E25

HD#63

F16

V32

Z32

AH32

AM32

B30

F30

AK34

D28

AJ29

AM28

F26

D24

AJ25

AM24

F22

D20

AJ21

AM20

B18

E17

AJ17

AM16

B14

E13

AJ13

AM12

B10

E9

AJ9

AM8

B6

D6

AJ5

F2

J5

N5

S5

W5

AA5

AE5

AM4

E5

F4

K2

P2

T2

AB2

AF2

AK2

C3

B26

R32 VCC52

VCC51

VCC50

VCC49

VCC48

VCC47

VCC46

VCC45

VCC44

VCC43

VCC42

VCC41

VCC40

VCC39

VCC38

VCC37

VCC36

VCC35

VCC34

VCC33

VCC32

VCC31

VCC30

VCC29

VCC28

VCC27

VCC26

VCC25

VCC24

VCC23

VCC22

VCC21

VCC20

VCC19

VCC18

VCC17

VCC16

VCC15

VCC14

VCC13

VCC12

VCC11

VCC10

VCC9

VCC8

VCC7

VCC6

VCC5

VCC4

VCC3

HA#30

HD#29

HA#31

HD#30 HD#31

VID0

HD#32

VID1

HD#33

VID2

HD#34

VID3

HD#35 RS#0

HD#36

RS#1

HD#37

RS#2

HD#38 HD#39

REQ#0

HD#40

REQ#1

HD#41

REQ#2

HD#42

REQ#3

HD#43

REQ#4

HD#44 RSRVD1

HD#45

RSRVD2

HD#46

RSRVD3

HD#47

RSRVD4

HD#48

RSRVD5

HD#49

RSRVD6

HD#50

RSRVD7

HD#51

RSRVD8

HD#52

RSRVD9

HD#53

RSRVD10

HD#54

RSRVD11

HD#55

RSRVD12

HD#56

RSRVD13

HD#57

RSRVD14

HD#58

RSRVD15

HD#59

RSRVD16

HD#60

RSRVD17

HD#61 HD#62 HD#63

GND50

HD#30

J3

HA#29

HD#28

GND49

A3

HD#27

GND48

HD#29

HA#28

GND47

A5

HA#27

GND46

HD#28

HD#26

GND45

HD#27

HA#26

Part 1

HD#25

GND44

E1 F12

GND43

E3

HD#26

HA#25

HD#24

GND42

K6

GND41

HD#24

HA#24

HD#23

GND40

G3

HA#23

GND39

HD#23

370-Pin Socket

HD#22

GND38

F8

HA#22

GND37

HD#22

HD#21

GND36

G1

HA#21

HD#20

GND35

HD#21

HD#19

GND34

L3

HA#20

GND33

HD#20

HA#19

HD#18

GND32

HD#19

H6

GND31

P4

HA#18

HD#17

GND30

HD#18

HD#16

GND29

R4

HA#17

GND28

HD#17

HA#16

HD#15

GND27

HD#16

H4

GND26

U3

HA#15

HD#14

GND25

HD#15

HA#14

HD#13

GND24

N3

HD#12

GND23

HD#14

HA#13

GND22

L1

HA#12

HD#11

GND21

HD#13

HA#11

HD#10

GND20

Q1

HA#10

HD#9

GND19

M4

HD#12

HD#8

GND18

Q3

HD#11

HA#9

GND17

HD#10

HD#7

GND16

P6

HA#8

GND15

HD#9

HA#7

HD#6

GND14

HD#8

S1

HD#5

GND13

J1

HA#6

GND12

T6

HD#7

HA#5

HD#4

GND11

HD#6

HA#4

GND10

HD#5

S3

HA#[31:3]

HA#3

GND9

A

3

HD#3

GND8

U1

HD#25

B

4

HD#2

GND7

HD#4

HD#1

GND6

M6

GND5

N1

HD#3

GND4

HD#2

VCC2

T4

VCC1

HD#1

HD#0

GND3

C

W1

GND2

D

X2 HD#0

GND1

HD#[63:0]

RSRVD18

AK8

5,7

HA#3

AH12

HA#4

AH8

HA#5

AN9

HA#6

AL15

HA#7

AH10

D

HA#8

AL9

HA#9

AH6

HA#10

AK10

HA#11

AN5

HA#12

AL7

HA#13

AK14

HA#14

AL5

HA#15

AN7

HA#16

AE1

HA#17

Z6

HA#18

AG3

HA#19

AC3

HA#20

AJ1

HA#21

AE3

HA#22

AB6

HA#23

AB4

HA#24

AF6

HA#25

Y3

HA#26

AA1

HA#27

AK6

HA#28

Z4

HA#29

AA3

HA#30

AD4

HA#31

AL35

VID0

AM36

VID1

AL37

VID2

C

VID[3:0]

AJ37

VID3

AH26

RS#0

AH22

RS#1

RS#[2:0]

AK28

RS#2

AK18

HREQ#0

AH16

HREQ#1

AH18

HREQ#2

AL19

HREQ#3

AL17

HREQ#4

30

7

HREQ#[4:0]

7

B

AH20 AH4 A29 A31 A33 AA33 AA35 AC1 AC37 AF4 AK16 AK24 AK30 AL11 AL13 AL21

A

AN11 AN13

REV:

D30

AM30

B28

F28

D26

AJ27

AM26

B24

F24

D22

AJ23

B20

AM22

F20

E19

AJ19

AM18

B16

E15

AJ15

AM14

B12

E11

AJ11

AM10

B8

E7

AJ7

AM6

B4

D4

G5

L5

Q5

U5

Y5

AC5

AG5

AL3

AK4

D2

H2

D18

M2

V2

Z2

AD2

AH2

AM2

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

AM34

5,7

5

VCCVID

370PGA Socket Part 1

DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

1.3

370-PIN SOCKET, PART 1

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

PROJECT: INTEL(R) 810 CHIPSET SHEET:

11-23-1998_13:44 3 1

OF

40

8

7

6

5

370PGA Socket Part 2

4

3

2

1

VTT1_5 4,33 VCMOS

4

R9

VCCVID

GTLREF

6

8

VCMOS

7

4,33

ITP Test Port Option

VCC2_5

5

VTT1_5

VCMOS

4,33

VCC2_5

220

RP2

D

R7

6 VCCVID

32 4,5,7 R76

VCMOS Decoupling

J35

APICD1

L35

APICCLK_U

J33

UHCLK

W37

PWRGOOD

AK26 X4

URST#

AG1

EDGCTRL

51

C6

R5

0.1UF

A

Do Not Stuff C114 C114 Place Site w/in 0.5" of clock pin (W37).18PF

AA37

K32

F14

AH24

AD32

D32

D36

H36

R36

V36

B22

AH36

B34

F34

K34

P34

T34

X34

AB34

AF34

H32

M32

AK22

AK12

Y35 VCC75

VCC74

VCC73

VCC72

VCC71

VCC70

VCC69

VCC68

VCC67

VCC66

VCC65

VCC64

VCC63

VCC62

VCC61

VCC60

VCC59

VCC58

VCC57

VCC56

VCC55

VCC54

VCC53

VREF7

VREF6

V6

R6

K4

F18

E33

AD6

VREF5

VREF4

VREF3

VREF2

VREF1

Z36

RSRVD41 RSRVD42

PICD0

RSRVD43

PICD1

RSRVD44

PICCLK

RSRVD45 BCLK

RSRVD46 RSRVD47

PWRGOOD

RSRVD48

RESET#

RSRVD49

EDGCTRL

RSRVD50 RSRVD51

UPRES# GND51

4,33

C37

Place 0603 Package Near VCMOS Processor Pin.

RSRVD39

AF32

VCMOS

RSRVD40

GND80

6

APICD0

BPRI# HTRDY#

AN19

DEFER#

AK20

HLOCK#

AN27

DRDY#

AL23

HITM#

AL25

HIT#

AL27

DBSY#

AN31

HADS#

RSRVD52

5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7

AE37 AJ33

FREQSEL

AN29

BR0#

6,9

C

5

AL31 AL29 AH28 AE33

A20M#

AG35

STPCLK#

AH30

USLP#

AJ35

SMI#

M36

INTR

L37

NMI

AG33

INIT#

AC35

FERR#

AG37

IGNNE#

13,33 13,33 13,33 13,33 13,33 13,33 13,15,33 13,33 13,33

AE35

VCCVID W33

PLL1

U33

PLL2

L22

S37

C123

+ 1

4.7UH

33UF 20%

U35

B

VCC3_3

U37 V4 W3

R171 220

W35 X6 Y1 E21

VCOREDET

E27

SLEWCTRL

R2 S35

RTTCTRL

X2

33

680

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

370-PIN SOCKET, PART 2 DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

9

33

Y33

13,33

RSRVD38

GND79

13,33

BNR#

AN17 AN25

2

RSRVD37

GND78

0.1UF

PLL2

AH14

RSRVD36

AJ31

0.1UF

PLL1

RSRVD35

Y37

0.1UF

S33

C207

IERR#

RSRVD34

GND77

0.1UF

C204

RSRVD33

AN3

1%

C209

IGNNE#

GND76

C206

FERR#

RSRVD32

AL1

R104 150

RSRVD31

GND75

Q37

INIT#

AJ3

Q35

4

RSRVD30

GND74

Q33 GTLREF

B

LINT1/NMI

AC33

N37

LINT0/INTR

RSRVD29

GND73

N35

RSRVD28

A37

Use 0603 Packages and distribute within 500 mils of Mendocino GTLREF Inputs (1 cap for every 2 inputs).

1%

SMI#

GND72

N33

R102 75

RSRVD27

F36

L33

SLP#

GND71

G37

RSRVD26

GND70

GTLREF Generation Circuit

STPCLK#

K36

G35

RSRVD25

A20M#

P36

F10

Part 2

RSRVD24

GND69

VTT1_5

THRMDN THERMTRIP#

RSRVD23

T36

E31

THRMDP

RSRVD22

GND68

E29

RSRVD21

GND67

E23

BR0#

370-Pin Socket

RSRVD20

X36

C33

BSEL#

RSRVD19

AF36

C31

BPM1#

GND66

B36 C29

FLUSH#

AK36

AN23

BPM0#

GND65

AN21

ADS#

D34

E35 AN15

DBSY#

BP3#

GND64

C35

BP2#

H34

30

E37

GND63

29

G33

4,5

M34

28

ITPRDY#

240

HIT#

GND62

27

R21

PRDY#

GND61

26

HITM#

R34

24

25

DRDY# PREQ#

GND60

23

ITPRDY#

4,5

LOCK#

V34

22

TMS

GND59

21

J37 A35

DEFER#

GND58

20

TMS AK32

TRDY#

TCK

Z34

19

R_ITPRDY#

R4 47

TRST#

AH34

18

R_TMS

4

AL33

AD34

17

ITPREQ#

TCK

GND57

16

R3 47

B32

15

R_TCK

4

GND56

14

BPRI#

GND55

13

TDO

F32

AN33

GND54

AN37

TRST#

P32

TDO

12

BNR#

T32

10

11

JP1 is a Test Option Only.

TDI

GND53

AN35

X32

TDI

V2_5

8

VREF0

6

7

ITPCLK

6

4

5

0K

ITP_PON9

C

3

4

R_TMS

4

X2

R_DBRST# 3

GND52

R_TCK

4

R2

2

AB32

DBRESET# 240

32

ITP_RST 1

V1_5

330

J2 1

4,5,7

R1

AD36

1K URST#

AB36

JP1

150

V_CMOS

R8

2

D

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

5-26-1999_17:09 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

4

OF

40

8

7

6

5

4

3

2

1

GTL Termination VTT1_5

VTT1_5

VTT1_5

VTT1_5

D

D

RP6

RP19 1

8

HA#17

2

7

HA#22

3

6

HA#31

4

5

HA#19

HA#[31:3]

3,7

BPRI#

4,7

1

8

HD#15

1

8

HD#54

7

HREQ#4

3,7

2

7

HD#1

2

7

HD#55

3

6

HLOCK#

4,7

3

6

HD#0

3

6

HD#52

4

5

RS#1

3,7

4

5

HD#6

4

5

HD#40

56 8

HA#18

2

7

HA#21

3

6

4

5

HA#25 HA#10

8

HTRDY#

2

7

RS#0

3

6

DRDY#

4

5

DBSY#

8

HD#8

1

8

HD#56

2

7

HD#5

2

7

HD#61

4,7

3

6

HD#9

3

6

HD#62

4,7

4

5

HD#4

4

5

HD#46

3,7

56

8

HA#15

2

7

HA#12

3

6

HA#3

4

5

HA#6

1

8

HITM#

2

7

HIT#

3

6

RS#2

5

HADS#

4

56

1

8

HD#16

1

8

HD#60

4,7

2

7

HD#23

2

7

HD#50

3

6

HD#21

3

6

HD#53

5

HD#24

4

5

HD#58

3,7

4

4,7

8

HA#30

2

7

HA#24

3

6

HA#20

4

5

HA#23

8

HREQ#0

2

7

DEFER#

3

6

HREQ#3

4

5

HREQ#2

1

8

HD#3

1

8

HD#57

4,7

2

7

HD#12

2

7

HD#63

3,7

3

6

HD#10

3

6

HD#59

3,7

4

5

HD#17

4

5

HD#48

3,7

56 8

HA#28

2

7

HA#13

3

6

HA#16

4

5

HA#5

ITPRDY#

1

8

1

8

HD#30

1

8

HD#47

2

7

2

7

HD#7

2

7

HD#27

3

6

3

6

HD#11

3

6

HD#44

4

5

4

5

HD#20

4

5

HD#45

BR0#

4

4

56

56

56 56 B

RP39

RP26

RP3

RP12

56

56

56

1

RP36

RP24

1

RP37

RP25

RP7 1

8

HA#9

2

7

HA#11

3

6

HA#7

4

5

HREQ#1

1

8

HD#13

1

8

HD#49

2

7

HD#18

2

7

HD#51

3

6

HD#14

3

6

HD#41

4

5

HD#2

4

5

HD#42

3,7

56

RP43 8

HA#8

2

7

HA#4

3

6

4

5

BNR#

4,7

B

56

56

RP11 1

C

56

56

RP10

RP20

RP32

4,7

56

1

56

RP35

RP5

RP8 1

RP33

1

4,7

56

56 C

RP23

1

3,7

56

56

RP9

RP18

HD#[63:0]

8

2

56

1

RP38

RP22

1

RP40

1

8

HD#31

1

8

HD#36

2

7

HD#32

2

7

HD#22

3

6

HD#25

3

6

HD#43

4

5

HD#26

4

5

HD#34

HA#14

56 56

56

RP41

RP21 URST#

1

8

2

7

HA#26

3

6

HA#29

4

5

HA#27

4,7

A

RP42

1

8

HD#29

1

8

HD#39

2

7

HD#19

2

7

HD#37

3

6

HD#35

3

6

HD#38

4

5

HD#33

4

5

HD#28

56

56

56

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

GTL TERMINATION DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

5

OF

38

8

7

6

5

4

3

2

1

VCC3_3

Clock Synthesizer

L17 USBV3

2

1

1

22UF

VCC3_3

0.1UF

2

VCC3_3

C50

+

C55

L13 1

D

L16 2

1

D

2

C38

C40

C39

C388

C385

.001UF

.001UF

C386

C63

C60

C387

C64

C61

C48

2

C37

+

C158

2

+

1

MEMV3

1

PCIV3

22UF

0.1UF

.001UF

0.1UF

.001UF

0.1UF

.001UF

0.1UF

0.1UF

.001UF

0.1UF

22UF

Notes: - Place all decoupling caps as close to VCC/GND pins as possible R41

- PCI_0/ICH pin has to go to the ICH. (This clock cannot be turned off through SMBus)

16 14

SIO_CLK14

C49

R184 10

ICH_CLK14

4

8 13 16 17 17 18 27 15

R42 22

ICH_3V66 GMCH_3V66 R49 22

PCLK_2 PCLK_3 PCLK_4 PCLK_5 PCLK_6

R50 33 R52 33 R51 33

3V66_0

7

3V66_1

8

PCI_0

11

PCI_1

12

R44 33

PCI_2

13

PCI_3

15

R45 33

PCI_4

16

PCI_5

18

R46 33

PCI_6

19

R53 33

USB_0

25

USB_1

26

R43 33

PCLK_0/ICH PCLK_1

APIC

20

APIC_0 APIC_1

REF XTAL_OUT

U_0 U_1 U_2/ITP

REF0

3V66_0

SDRAM_0

3V66

3V66_1

SDRAM_1

ICS9250-10 PCI_0/ICH

CK-Whitney

PCI_1

SDRAM_2 SDRAM_3

Memory

SDRAM_4 SDRAM_5

PCI_2 PCI_3

SDRAM_6

PCI

SDRAM_7

PCI_4

PCI_6

DCLK

DOTCLK

R47 22

USB_0

SCLK

USB

USB_1

SDATA SEL1

1

B

USBCLK

APIC_0

54

APIC_1

R34 33

52

U_0_1

R32

APICCLK_U R25 33 33

50 49

U_2

46

DRAM_0

45

DRAM_1

43

DRAM_2

42

DRAM_3

40

DRAM_4

39

DRAM_5

37

DRAM_6

36

DRAM_7

34

DCLK

SEL0

13

R35 33

R26 33

R27 22 R28 22 R29 22 R30 22

GMCHHCLK

7

ITPCLK

R36 22

MEMCLK0

R37 22

MEMCLK2

R38 22

MEMCLK4

R39 22

MEMCLK6

R40 22

DCLK_WR

C

4 4

MEMCLK[7:0]

11,12

MEMCLK1 MEMCLK3 MEMCLK5 MEMCLK7

CK_PWRDN#

32 31

CK_SMBCLK

30

CK_SMBDATA

VCC2_5

8 32 25

L15

25

B

29 28

FREQSEL

4,9 1

L_CKVDDA

4

APICCLK_ICH UHCLK

PCI_7 PWRDWN#

9

55

PCI_5

L18

14

SEL1_PU

38

33

27

21

10

44 VDD3_3[7]

VDD3_3[6]

VDD3_3[5]

VDD3_3[4]

VDD3_3[3]

XTAL_IN

U 1

REFCLK

14

2

XTAL_OUT

12PF

R48 10

VCC3_3

3

14.318MHZ

2

1

C

VDD3_3[2]

VDD3_3[0] XTAL_IN

XTAL

Y1

2

12PF

VDD3_3[1]

2

C51

9

8.2K

U1

- U_ITP pin has to go to the ITP. It is the only U CLK that can be shut off through the SMBUS interface.

L_VCC2_5

VDD_A VDD2_5[0]

53

VSS3_3[7]

VSS3_3[6]

VSS3_3[5]

VSS3_3[4]

VSS3_3[3]

VSS3_3[2]

VSS_A VSS3_3[1]

23

1

VDD2_5[1]

.001UF

VSS3_3[0]

0.1UF

51

VSS2_5[1] VSS2_5[0]

56

C46

C47

+

22

C53

C56

48 2

C52

.001UF

0.1UF

4.7UF

47

41

35

24

6

17

CLK14 trace to JP6.

14

5

Minimize Stub Length from

APIC Clk Strap 16MHz 33MHz

A

JP6 in out*

JP1

JP6

A R23 10K REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

CLOCK SYNTHESIZER DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

12-8-1998_13:05 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

6

OF

40

5

4

W13

R81 150

C166

F8

F10

F14

GTLREFB

6 0.1UF

.001UF

HD0# HD1# HD2# HD3# HD4# HD5#

C167

1%

13,17,18,24,27 4,5 4,5 4,5 4,5 4,5 4,5 4,5 4,5 4,5 4,5 4,5

GMCHHCLK

V6

PCIRST#

M2

URST#

AB4

HLOCK#

P5

DEFER#

R3

HADS#

N3

BNR#

T3

M4 N1

HITM#

R1

HTRDY#

N4

HA#4

U1

HA#5

V4

HA#6

V1

HA#8

U2

HA#9

U3

HA#10

W1

HA#11

U4

HA#12

W3

B

HD12# HD13#

INTEL 82810-DC100

DBSY#

HD14# HD15# HD16#

PART1

HIT#

HD17# HD18# HD19#

HOST INTERFACE

HA3#

HD20# HD21#

HA4#

HD22#

HA5#

HD23#

HA6#

HD24#

HA7#

HD25#

HA8#

HD26#

HA9#

HD27#

HA10#

HD28#

HA11#

HD29#

HA12#

HA#13

W4

HA#14

T5

HA#15

W2

HA#16

V2

HA#17

AC2

HD30#

HA13#

HD31#

HA14#

HD32#

HA15#

HA#18

AA2

HA#19

Y3

HA#20

HD11#

HTRDY#

U5

T4

HD10#

HITM#

HA#3

HA#7

HD9#

HLOCK#

DRDY#

P1

C

URST#

BPRI#

HIT#

3,5

HD8#

BNR#

DBSY#

HA#[31:3]

HD7#

RESETB

ADS#

T1

DRDY#

HD6#

HTCLK

DEFER#

BPRI#

AB3

HA#21

AA1

HA#22

AB2

HA#23

AC3

HA#24

AA3

HA#25

Y2

HA#26

AB5

HA#27

AC4

HA#28

Y1

HA#29

AC5

HA#30

Y4

HA#31

AB1

HD33#

HA16#

HD34#

HA17#

HD35#

HA18#

HD36#

HA19#

HD37#

HA20#

HD38#

HA21#

HD39#

HA22#

HD40#

HA23#

HD41#

HA24#

HD42#

HA25#

HD43#

HA26#

HD44#

HA27#

HD45#

HA28#

HD46#

HA29#

HD47#

HA30#

HD48#

HA31#

HD49#

HREQ#[4:0] 3

RS#[2:0] 3

HREQ#0

R4

HREQ#1

T2

HD50# HREQ0#

P4

HREQ#3

R2

HREQ#4

R5

RS#0

HD51#

HREQ1#

HREQ#2

HD52#

HREQ2#

HD53#

HREQ3#

HD54#

HREQ4#

N5

HD55# HD56#

RS0#

RS#1

P2

RS#2

N2

HD57#

RS1#

HD58#

RS2#

HD59#

A VSS[23]

VSS[22]

VSS[21]

HD61# HD62# HD63#

N13

N14

M10

VSS[19]

VSS[18]

VSS[20] M11

M12

M13

VSS[16]

VSS[15]

VSS[17] M14

L10

L11

VSS[13]

VSS[14] L12

L13

VSS[11]

VSS[10]

VSS[9]

VSS[8]

VSS[7]

VSS[12] L14

K10

K11

K12

K13

K14

VSS[5]

VSS[4]

VSS[3]

VSS[2]

VSS[1]

VSS[6] E22

C19

Y19

J22

N22

Y22

V18

VSS[0]

HD60#

Do Not Stuff C161 C161 Place Site w/in 0.5" of clock ball (V6). 18PF

2

1

F7 VCC_CORE[13]

VCC_CORE[12]

VCC_CORE[11]

F17

V7

V8

V9

V10

V14

V15

F16 VCC_CORE[9]

VCC_CORE[10]

VCC_CORE[8]

VCC_CORE[7]

VCC_CORE[6]

VCC_CORE[5]

VCC_CORE[4]

VCC_CORE[3]

V16

V17

GTLREFA

VCC_CORE[2]

M5

GMCHGTLREF

D

VCC_CORE[1]

VCC1_8[0]

1%

VCC_CORE[0]

U2 R80 75

P6

B20

82810-DC100, PART 1: HOST INTERFACE

3

VCC1_8

U18

6

VCC1_8[2]

7 VTT1_5

VCC1_8[1]

8

HD#[63:0]

Y5

HD#0

W5

HD#1

W8

HD#2

AA6

HD#3

AB6

HD#4

Y6

HD#5

AA5

HD#6

AA9

HD#7

V5

HD#8

AC7

HD#9

AB7

HD#10

AC8

HD#11

AA7

HD#12

Y8

HD#13

W7

HD#14

AC6

HD#15

W9

HD#16

AC9

HD#17

Y7

HD#18

AA10

HD#19

AB8

HD#20

AC10

HD#21

AB13

HD#22

AB10

HD#23

AB9

HD#24

AB11

HD#25

Y10

HD#26

AB16

HD#27

AB12

HD#28

Y11

HD#29

Y9

HD#30

AC12

HD#31

W11

HD#32

AC11

HD#33

W12

HD#34

AA11

HD#35

AA13

HD#36

Y13

HD#37

Y12

HD#38

AC14

HD#39

AA15

HD#40

AC15

HD#41

Y14

HD#42

AC13

HD#43

AA14

HD#44

AB14

HD#45

Y17

HD#46

Y15

HD#47

AC17

HD#48

AC16

HD#49

AA18

HD#50

AB15

HD#51

W15

HD#52

AB18

HD#53

W17

HD#54

AA17

HD#55

W18

HD#56

W16

HD#57

AC19

HD#58

Y16

HD#59

AB19

HD#60

Y18

HD#61

AC18

HD#62

AB17

3,5

D

C

B

A

HD#63 REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

82810-DC100 : HOST INTERFACE DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

7

OF

40

8

7

6

5 VCC1_8

82810-DC100 PART 2: SYSTEM MEMORY AND HUB INTERFACE

4

VCC3SBY

3

2

1

VCC3_3

A9

SM_MAA3

D7

SM_MAA4

8

1

R_MAA4

B8

SM_MAA5

7

2

R_MAA5

A8

SM_MAA6

6

3

R_MAA6

B7

SM_MAA7

5

4

R_MAA7

A7

SM_MAA8 RP70 and RP71 should be placed within 0.5" of the GMCH balls.

SM_MAB[7:4]# Place HUBREF Generation Circuit in middle of VCC1_8 GMCH and ICH.

12

RP70

C6

SM_MAA10

D5

SM_MAA11

A5

SM_MAB4#

8

1

R_MAB#4

B6

SM_MAB5#

7

2

R_MAB#5

A6

SM_MAB6#

6

3

R_MAB#6

B4

SM_MAB7#

5 RP71

SM_DQM[7:0]

HUBREF

8,13

SM_BS[1:0]

R131 301 1%

R176 56

C10 A10

SM_DQM2

B1

SM_DQM3

D1

SM_DQM4

B10

SM_DQM5

D9

SM_DQM6

C1

SM_DQM7

D2

C5

SM_BS1

E5

J18

F18

R18 VCC3_3[15]

VCC3_3[14]

VCC3_3[13]

L21

G21 VCC3_3[12]

VCC3_3[11]

B2

K6

F9

F15

G3

L3

C15

C7

C11

F6 VCC3_3[9]

VCC3_3[10]

VCC3_3[8]

VCC3_3[7]

SMD1 SMD2 SMD3 SMD4

SMAA3

SMD5

SMAA4

SMD6

SMAA5

SMD7

SMAA6

SMD8

SMAA7

SMD9

SMAA8

SMD10

SMAA9 SMAA10

SMD11

INTEL 82810-DC100

SMAA11

SMD12 SMD13 SMD14

SMAB4#

PART 2

SMAB5#

SMD15 SMD16

SMAB6#

SMD17

SMAB7#

SYSTEM MEMORY

SMD18 SMD19

SDQM0 SDQM1

SMD20

AND

SDQM2

SMD21 SMD22

SDQM3

HUB INTERFACE

SDQM4

SMD23 SMD24

SDQM5

SMD25

SDQM6

SMD26

SDQM7

SMD27 SMD28

SBS0

SMD29

SBS1

SMD30

SM_CS#[3:0]

SM_CS#0

11,12 470PF

11,12 11,12 11,12

C3

SM_CS#2

B3

SM_CS#3

C2

SM_CAS#

A11

SM_WE#

B11

0K

DCLK_WR

SM_CS#1

D8

11,12

B

C4

SM_RAS#

SM_CKE[1:0]

SM_CKE0

A3

SM_CKE1

A2

SCLK

E6

SMD31

SCS0#

SMD32

SCS1#

SMD33

SCS2#

SMD34

SCS3#

SMD35 SMD36

SRAS#

SMD37

SCAS#

SMD38

SWE#

SMD39 SMD40

SCKE0

SMD41

SCKE1

SMD42

SCLK

SMD43

R31

HUBREF HLSTB#

A20 GHCOMP D18

SMD59

HCOMP

SMD60

0.1UF

SMD61 SMD62 SMD63

E17

SM_MD0

C16

SM_MD1

D15

SM_MD2

D17

SM_MD3

C17

SM_MD4

A17

SM_MD5

A16

SM_MD6

B16

SM_MD7

A15

SM_MD8

C14

SM_MD9

B14

SM_MD10

A14

SM_MD11

D13

SM_MD12

C13

SM_MD13

A13

SM_MD14

A12

SM_MD15

E1

SM_MD16

F2

SM_MD17

G4

SM_MD18

G1

SM_MD19

D3

SM_MD20

H2

SM_MD21

H1

SM_MD22

J4

SM_MD23

J1

SM_MD24

K2

SM_MD25

K1

SM_MD26

K3

SM_MD27

L1

SM_MD28

L2

SM_MD29

M3

SM_MD30

K4

SM_MD31

D16

SM_MD32

E15

SM_MD33

D14

SM_MD34

E14

SM_MD35

E13

SM_MD36

E12

SM_MD37

D12

SM_MD38

B15

SM_MD39

B12

SM_MD40

C12

SM_MD41

D11

SM_MD42

D10

SM_MD43

E10

SM_MD44

E9

SM_MD45

E8

SM_MD46

C8

SM_MD47

F3

SM_MD48

F1

SM_MD49

G2

SM_MD50

H3

SM_MD51

E4

SM_MD52

E3

SM_MD53

F4

SM_MD54

J3

SM_MD55

F5

SM_MD56

G5

SM_MD57

H5

SM_MD58

H4

SM_MD59

H6

SM_MD60

J5

SM_MD61

K5

SM_MD62

L5

SM_MD63

SM_MD[63:0] 11,12

D

C

B

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

J2

L4

P3

M1

R6

V3

W14

W10

W6

AA16

AA8

AA12

AA4

18PF

P10

C236 AC1

Place C241 as close as possible to GMCH

SMD58

HLSTB#

VSS[24]

C241

HLSTB

P11

8,13

A21

SMD57

P12

A

HLSTB

SMD56

HUBREF

P13

8,13

D20

SMD55

HL10

VSS[45]

A19

VSS[44]

HL10

HL9

VSS[43]

C20

SMD54

VSS[42]

HL9

SMD53

HL8

VSS[41]

A22

VSS[40]

HL8

SMD52

HL7

VSS[39]

A18

VSS[38]

HL7

SMD51

HUB I/F

HL6

VSS[37]

C18

VSS[36]

HL6

SMD50

HL5

VSS[35]

B18

VSS[34]

HL5

SMD49

HL4

VSS[33]

B19

VSS[32]

HL4

SMD48

HL3

VSS[31]

A23

VSS[30]

HL3

SMD47

HL2

VSS[29]

B22

HL1

VSS[28]

HL2

SMD46

VSS[27]

B23

SMD45

HL0

VSS[26]

HL1

SMD44 HLCLK

P14

22PF

C21

VSS[25]

D19

HL0

N10

GMCH_3V66 HL[10:0]

6,8 13

N11

C168

N12

6

A4

SMD0

SMAA2

10 OHMS

SM_BS0

11,12

C299 HUBREF_CG

R_MAB#7

SM_DQM1 R130 301 1%

R177 56

4

SM_DQM0

11,12 470PF

C

D6

SM_MAA9

C300 HUBREF_CV

10 OHMS

SMAA1

VCC3_3[6]

E7

SM_MAA2

VCC3_3[5]

SM_MAA1

D

SMAA0

VCC3_3[4]

C9

VCC3_3[3]

SM_MAA0

VCC3_3[2]

11,12

U2

VCC3_3[0]

SM_MAA[11:0]

VCC3_3[1]

R82 40 1%

as possible to GMCH

D4

Place Resistor as Close

1.3

82810-DC100: SYSTEM MEMORY AND HUB DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

5-26-1999_17:13 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

8

OF

40

7

6

5

4

3

82810-DC100, PART 3: DISPLAY CACHE AND VIDEO INTERFACE

L24

10

GMCH RESET STRAPS 10 10

VCOREDET

4

10 FREQSEL

4,6

10

DC_DQM1

R23

DC_DQM2

C23

DC_DQM3

F20

DC_RAS#

K19

DC_CAS#

K20

DC_WE#

J19

DC_MA[11:0]

VCC3_3

DC_MA0

M19

DC_MA1

P19

DC_MA2

P20

6

7

RP48

4

3

2 GRS_PU30

1

10K

GRS_PU31

4 GRS_PU26

3

2

1

10K

GRS_PU28

C

5

8

6

5

7

8

DC_MA3

RP46

10

JP16 JP15

DC_MD31 DC_MD30 DC_MD29

JP14

DC_MD28 DC_MD27

JP13

Function XOR

DC_MD26

System Bus Frequency IOQD VCORE Detect RESVD

9,10 9,10 9,10 9,10 9,10 9,10

JP15 N/A

READS System Bus Frequency

JP16

B

Tri-State

DC_MD[31:0]

Function IN=XOR TREE OUT=NORMAL* IN=TriState Mode OUT=NORMAL*

Jumper

IN=IO Queue Depth 1 OUT=IO Queue Depth 4* Detects Type of Processor N/A I/O Buffers JP13 TBD

JP14

10

P21

J21

DC_MA5

H19

DC_MA6

H20

DC_MA7

H18

DC_MA8

G19

DC_MA9

F19

DC_MA10

M20

DC_MA11

L19

DC_MD0

M22

DC_MD1

M21

DC_MD2

L23

DC_MD3

L22

DC_MD4

K21

DC_MD5

K23

DC_MD6

R19

DC_MD7

R20

DC_MD8

R22

DC_MD9

R21

DC_MD10

P23

DC_MD11

P22

DC_MD12

N23

DC_MD13

N21

DC_MD14

N20

DC_MD15

M23

DC_MD16

F23

DC_MD17

E20

DC_MD18

E21

DC_MD19

E23

DC_MD20

D22

DC_MD21

D23

DC_MD22

D21

DC_MD23

C22

DC_MD24

H21

DC_MD25

H22

DC_MD26

H23

DC_MD27

G20

DC_MD28

G22

DC_MD29

G23

DC_MD30

F21

DC_MD31

F22

R127

DC_CLK

N19

DC_MA4

R_LTCLK

K22

RCLK

J20

OCLK

J23

AB21

AB23

VCCDA

VCCDACA2

E19 VCCBA

U6 VCCHA

LCS#

VCCDACA1

DC_DQM0

LTVDATA0

LDQM0

LTVDATA1

LDQM1

LTVDATA2

LDQM2

LTVDATA3

LDQM3

LTVDATA4

VIDEO DIGITAL OUT

LRAS#

LTVDATA5 LTVDATA6

LCAS#

INTERFACE

LWE#

LTVDATA7 LTVDATA8

LMA0

LTVDATA9

LMA1

LTVDATA10

LMA2

LTVDATA11

LMA3

BLANK#

LMA4

TVCLKIN/SL_STALL

INTEL 82810-DC100

LMA5

CLKOUT0

LMA6

CLKOUT1

LMA7

PART3

LMA8

TVVSYNC TVHSYNC

OCLK_FB

0K

R129

LMA10

LTVCL

DISPLAY CACHE

LMA11 LMD0

LTVDA

FTD0

Y20

FTD1

W23

FTD2

W22

FTD3

W21

FTD4

V23

FTD5

U23

FTD6

U22

FTD7

U21

FTD8

T23

FTD9

T22

FTD10

T21

FTD11

D

FTD[11:0]

FTBLNK#

V19 U20

SL_STALL

V21

FTCLK0

V22

FTCLK1

V20

FTVSYNC

U19

FTHSYNC

T19

3VFTSCL

T20

3VFTSDA

24

24 24 24 24 24 24

C

24,25 24,25

AND

LMD1 LMD2 LMD3

VIDEO INTERFACE

LMD4 LMD5 LMD6 LMD7 LMD8 LMD9 LMD10 LMD11 LMD12 LMD13 LMD14 LMD15 LMD16

B

LMD17 LMD18

DISPLAY CACHE INTERFACE

LMD19 LMD20

DDCDA DDCCL

LMD21

DCLKREF

LMD22

IWASTE

LMD23

IREF

W19

3VDDCDA

W20

3VDDCCL

AA21

DOTCLK

25 25 6

Y23 AA23

IREFPD

LMD24 LMD25 VSYNC

GRAPHICS INTERFACE

LMD26

HSYNC

LMD27

RED

LMD28

GREEN

LMD29

BLUE

LMD30

AA20

CRT_VSYNC

AB20

CRT_HSYNC

AC21

VID_RED

AC22

VID_GREEN

AC23

VID_BLUE

25 25 25 25 25

LMD31

R125 Place as close as 174 Possible to GMCH 1% and via straight to VSS plane.

LTCLK

LRCLK

C379

Do Not Stuff C379 Place Site w/in 0.5" of clock ball (AA21).

18PF

A

LOCLK

VSSDA

VSS[61]

VSS[60]

VSS[59]

VSS[58]

VSS[57]

VSS[56]

VSS[55]

VSS[54]

VSS[53]

VSS[52]

VSS[51]

VSS[50]

VSS[49]

VSS[48]

VSS[47]

VSS[46]

VSSBA

VSSHA

33 Place R129 within 0.5" of the GMCH Ball. C238

Y21

VSSDACA

R128

C222 0.1UF

68NH-0.3A

LMA9

22

A

C216 0.01UF

2

L20

DC_DQM[3:0]

C217

+

DC_CS#

AC20

1

10

1

VCCDACA

U2

D

2 VCC1_8

VCC1_8

33UF 20%

8

REV:

AB22

AA22

AA19

T18

P18

K18

B21

B17

G18

E16

B13

E11

B9

B5

A1

E2

G6

J6

E18

22PF

T6

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

Do Not Populate C238

DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

1.3

82810-DC100: DISPLAY CACHE AND VIDEO

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

5-26-1999_17:09

1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

9

OF

40

8

7

6

5

4

3

2

1

4MB Display Cache

D

D

DC_MA11

19

DC_CLK

35

DC_CKE

34

A7

DQ7

A8

DQ8

A9 A10 A11

CLK CKE

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

15

33 37

29

11

DC_MD6

9

DC_MA6

12

DC_MD7

30

DC_MD8

9 9

DC_MA7

39

DC_MA8

31

DC_MD9

DC_MA9

32

40

9

42

DC_MD10

9

DC_MA10

20

43

DC_MD11

9

45

DC_MD12

46

DC_MD13

9

48

DC_MD14

10

49

DC_MD15

UDQM

CAS#

LDQM

19

DC_CLK

35

DC_CKE

34

DC_CS#

18

DC_RAS#

17

DC_CAS#

16

DC_WE#

15

36

DC_DQM1

9

14

DC_DQM0

9 9

33 NC_1

37

NC_2

44

38

A3

DQ3

A4

DQ4

A5

DQ5

A6

DQ6

A7

DQ7

A8

DQ8

A9 A10 A11

CLK CKE

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14

3

DC_MD17

5

DC_MD18

6

DC_MD19

8

DC_MD20

9

DC_MD21

11

DC_MD22

12

DC_MD23

39

DC_MD24

40

DC_MD25

42

DC_MD26

43

DC_MD27

45

DC_MD28

46

DC_MD29

48

DC_MD30

49

DC_MD31

36

DC_DQM3

14

DC_DQM2

DC_DQM[3:0] 9

C

CS# RAS#

UDQM

CAS#

LDQM

WE#

NC_1 NC_2

50

26

47

41

10

4

13

7

DQ2

4

B

DQ1

A2

DQ15

9

WE#

DC_MA11

VDDQ_4

28

VDDQ_3

27

DC_MA5

VDDQ_2

DC_MA4

9

VDDQ_1

9

DC_MD5

A1

VSS_1

DC_WE#

9

RAS#

VSS_2

16

VSSQ_1

17

VSSQ_2

DC_RAS# DC_CAS#

9

DC_MD4

9

CS#

VSSQ_3

9 9

18

VSSQ_4

DC_CS#

9

DC_MD3

8

25

1 DQ6

6

24

VDD_1

38

13

44 VDDQ_4

VDDQ_3

7

A6

23

DC_MA3

DC_MD16

VSS_1

20

DQ5

22

DC_MA2

2

B

50

DC_MA10

A5

DC_MA1

9

VSS_2

32

DQ4

9

DC_MD2

9 DQ0

26

DC_MA9

DQ3

A4

DC_MD1

5

VSSQ_1

31

A3

3

47

30

DC_MA8

DQ2

DC_MD[31:0]

SDRAM 50-PIN TSOP

DC_MA7

DQ1

A2

VSSQ_2

29

DQ0

A1

VSSQ_3

DC_MA6

VDDQ_2

28

VDDQ_1

1 27

DC_MA5

VDD_2

24

DC_MA4

VDD_1

DC_MA3

A0

A0

41

9

23

9

21

10

R114 4.7K

22

DC_MA2

2

DC_MD0

DC_MA0

VSSQ_4

C

DC_MA1

SDRAM 50-PIN TSOP

VCC3_3

21

25

U9

U8 DC_MA[11:0] 9 DC_MA0

VCC3_3

VDD_2

VCC3_3

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

DISPLAY CACHE DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

10 OF

40

8 7

A

6

MEMCLK[7:0]

8

8

8

12,14,25,28,33

12,14,25,28,33 8

SM_BS[1:0]

5 SM_DQM7

SM_CS#1

SM_CS#0

SM_MAA[11:0]

SM_CKE1

SM_CKE0

8 SM_DQM6

4 SAO_PU

3 R

164

146

145

135

134

109

108

80

62

61

51

50

NC17

NC16

NC15

NC14

NC13

NC12

NC11

NC10

NC9

NC8

NC7

NC6

NC5

NC4

NC3

NC2

NC1

WP

SA2

SA1

SA0

REGE

SMBCLK

SMBDATA

SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD20 SM_MD21 SM_MD22 SM_MD23 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD32 SM_MD33 SM_MD34 SM_MD35 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD46 SM_MD47 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_MD52 SM_MD53 SM_MD54 SM_MD55 SM_MD56 SM_MD57 SM_MD58 SM_MD59 SM_MD60 SM_MD61 SM_MD62 SM_MD63

7 8 9 10 11 13 14 15 16 17 19 20 55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161

VCC17 VSS18

VCC16 VSS17

VCC15 VSS16

DIMM0

SLAVE ADDRESS = 1010000B 137

136

106

105

53

52

22

21

SM_MD3

5

3

ECC7

ECC6

ECC5

ECC4

ECC3

ECC2

ECC1

ECC0

DQ63

DQ62

DQ61

DQ60

DQ59

DQ58

DQ57

DQ56

DQ55

DQ54

DQ53

DQ52

DQ51

DQ50

DQ49

DQ48

DQ47

DQ46

DQ45

DQ44

DQ43

DQ42

DQ41

DQ40

DQ39

DQ38

DQ37

DQ36

DQ35

DQ34

DQ33

DQ32

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ13

DQ12

SM_MD2

4

4

48

44

31

25

24

81

167

166

165

147

83

CKE1

CKE0

RAS#

CAS#

WE#

S3#

S2#

S1#

S0#

DQMB7

DQMB6

DQMB5

DQMB4

DQMB3

DQMB2

DQMB1

DQMB0

BA1

BA0

A13

A12

A11

A10

A9

A8

A7

A6

A5

DQ11

SM_MD1

3

5

82

63

128

115

111

27

129

45

114

30

131

130

113

112

47

46

29

28

39

122

132

126

123

38

121

37

120

36

A4

SM_MD0

2

6

SM_DQM5

SM_DQM4

SM_DQM3

SM_DQM2

SM_DQM1

SM_DQM0

6 SM_BS1

SM_BS0

SM_MAA11

SM_MAA10

35 119

DQ10

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

7

SM_MAA9

SM_MAA8

SM_MAA7

SM_MAA6

SM_MAA5

SM_MAA4

A3

6

A2

18

118

26

SM_MAA3

40

A1

41

34

90

117

102

SM_MAA2

49

SM_MAA1

110

A0

124 VCC12

33

59 VCC13

SM_MAA0

73

CLK3

84

163

C VCC14

MEMCLK3

133

CLK2

143

CLK1

157

79

168

125

CLK0

VCC3SBY

MEMCLK2

42

D

MEMCLK1

MEMCLK0

8 2

VSS15

VSS14

VSS13

VCC11 VSS12

VCC10 VSS11

VCC9 VSS10

VCC8 VSS9

VCC7 VSS8

VCC6 VSS7

VCC5 VSS6

VCC4 VSS5

VCC3 VSS4

VCC2 VSS3

VCC1 VSS2

VSS1

PCD PLATFORM DESIGN

1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 2

1

SYSTEM MEMORY

8,12 SM_MD[63:0]

D

162

152

148

138

127

116

107

C

96

85

78

68

64

54

43

32

23

12

1

J11

B B

12

8

8 SM_DQM[7:0]

8 SM_CS#[3:0]

SM_WE#

SM_CAS#

SM_RAS#

SM_CKE[1:0]

A

SMBDATA

SMBCLK TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

SYSTEM MEMORY: DIMM0

REV:

DRAWN BY:

INTEL CORPORATION

PLATFORM COMPONENTS DIVISION LAST REVISED:

12-8-1998_13:14 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

1.3

11 OF

40

8 7

A

6 8

8

8

8

11,14,25,28,33

11,14,25,28,33

5

SM_MAA[11:0] SM_DQM7

SM_DQM6

SM_CS#3

SM_CS#2

8 SM_DQM5

SM_DQM4

SM_DQM3

SM_DQM2

SM_DQM1

SM_DQM0

35

121 38 123

SM_MAA9 SM_MAA10 SM_MAA11

SM_BS1

SM_MAB[7:4]#

8 SM_BS[1:0]

4 3 R

PCD PLATFORM DESIGN

1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 2

164

146

145

135

NC17

NC16

NC15

NC14

NC13

NC12

NC11

NC10

NC9

NC8

NC7

NC6

NC5

NC4

NC3

NC2

NC1

VCC17

DIMM1

VCC14 VSS15

VCC13 VSS14

SLAVE ADDRESS = 1010001B

ECC7

ECC6

ECC5

ECC4

ECC3

ECC2

ECC1

ECC0

DQ63

DQ62

DQ61

DQ60

DQ59

DQ58

DQ57

DQ56

DQ55

DQ54

DQ53

DQ52

DQ51

DQ50

DQ49

DQ48

DQ47

DQ46

DQ45

DQ44

DQ43

DQ42

DQ41

DQ40

DQ39

SM_MD3 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD20 SM_MD21 SM_MD22 SM_MD23 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD32 SM_MD33 SM_MD34 SM_MD35 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD46 SM_MD47 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_MD52 SM_MD53 SM_MD54 SM_MD55 SM_MD56 SM_MD57 SM_MD58 SM_MD59 SM_MD60 SM_MD61 SM_MD62 SM_MD63

5 7 8 9 10 11 13 14 15 16 17 19 20 55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161

137

136

106

105

53

52

22

21

SM_MD2 4

3

134

109

108

80

62

61

51

50

48

44

31

25

24

WP

SA2

SA1

SA0

REGE

SMBCLK

SMBDATA

CKE1

CKE0

RAS#

CAS#

DQ38

DQ37

DQ36

DQ35

DQ34

DQ33

DQ32

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

SM_MD1 3

4

81

167

166

165

147

83

82

63

128

115

WE#

S3#

S2#

S1#

S0#

DQMB7

DQMB6

DQMB5

DQMB4

DQMB3

DQMB2

DQMB1

DQMB0

BA1

BA0

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

SM_MD0 2

5

111

27

129

45

114

30

131

130

113

112

47

46

29

28

39

122

132

126

37

120

36

119

SM_MAA8

SM_BS0

SM_MAB7#

SM_MAB6#

SM_MAB5#

34

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

6

SM_CKE1

MEMCLK[7:0]

SM_CKE0

6 DQ1

DQ0

7

SM_MAB4#

B 118

6

SM_MAA3

18

SM_MAA2

26 VCC12

A1

40 VCC15

A0

41

117

90

SM_MAA1

102

33

110

SM_MAA0

49 VCC16

CLK3

124

CLK2

C

163

59

MEMCLK7

73

CLK1

84

79

133

125

143

MEMCLK6

157

MEMCLK5

CLK0

168

42

VCC3SBY

MEMCLK4

8 2 1

SYSTEM MEMORY

8,11 SM_MD[63:0]

D D

VSS18

VSS17

VSS16

VSS13

VCC11 VSS12

VCC10 VSS11

VCC9 VSS10

VCC8 VSS9

VCC7 VSS8

VCC6 VSS7

VCC5 VSS6

VCC4 VSS5

VCC3 VSS4

VCC2 VSS3

VCC1 VSS2

VSS1

162

152

148

138

127

116

107

96

85

78

C

68

64

54

43

32

23

12

1

J13

VCC3SBY

SAO_PU

R60

B

2.2K

8

8 SM_DQM[7:0]

8 SM_CS#[3:0]

SM_WE#

SM_CAS#

SM_CKE[1:0] SM_RAS#

SMBDATA

SMBCLK

A

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

SYSTEM MEMORY: DIMM1

REV:

DRAWN BY:

INTEL CORPORATION

PLATFORM COMPONENTS DIVISION LAST REVISED:

12-8-1998_13:14 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

1.3

12 OF

40

6

5

3

C1

AD13

B1

AD14

D4

AD15

C3

AD16

C

C_BE#[3:0]

17,18,27

B

A4

AD17

B4

AD18

C5

AD19

C6

AD20

B5

AD21

E7

AD22

A6

AD23

B6

AD24

D7

AD25

B8

AD26

A7

AD27

A8

AD28

B7

AD29

C9

AD30

D8

AD31

C7

C_BE#0

D2

C_BE#1

B2

C_BE#2

A3

C_BE#3

D6

PCLK_0/ICH

6 17,18,27,33 17,18,27,33 17,18,27,33 17,18,27,33 17,18,27,33 7,15,16,17,18,19,24,27 17,18,33

C14

FRAME#

B3

DEVSEL#

D9

IRDY#

A2

TRDY#

C4

STOP#

D5

PCIRST#

J5

PLOCK#

B9

PAR

17,18,27 17,18,27,33 17,18,27 18,33 18 33 33

A9 A1 K1

PCI_REQ#A

N6

PCI_GNT#A

P5

REQ#B/GPIO1

P4

GNT#B/GPIO17

R5

H16

L15

G15

K14

H14

G13

J16 VCC1_8_7

VCC1_8_6

VCC1_8_5

VCC1_8_4

VCC1_8_3

VCC1_8_2

VCC1_8_1

N13

N5

D16

E5

E6

A5

C8

C11

M14

T16

R13

U10

T7

E13 VCC3_3_17

VCC3_3_16

VCC3_3_15

VCC3_3_14

VCC3_3_13

VCC3_3_12

VCC3_3_11

VCC3_3_10

VCC3_3_9

VCC3_3_8

VCC3_3_7

VCC3_3_6

VCC3_3_5

P6

G5

AD7

SMI#

F14

SMI#

AD8

STPCLK#

A17

STPCLK#

RCIN#

A15

RCIN#

A20GATE

B15

A20GATE

AD9 AD10

AD12

INTEL 82801AB PART 1

AD13 AD14 AD15 AD16 AD17

4,33 4,33 4,15,33 4,33 4,33 4,33 4,33 16,33 16,33

D17

HL1

E17

HL1

HL2

F17

HL2

HL3

G16

HL3

HL4

J15

HL4

HL5

K16

HL5 HL6

VCC1_8

HL7

L17

HL7

AD20

HL8

H15

HL8

AD21

HL9

J17

HL9

AD22

HL10

J14

HL10

HUB I/F

C

R182 40, 1%

HL6

AD19

PCI

8

HL0

HL0

K17

AD18

4,33 4,33

HL[10:0]

AD11

Place R182 as close as possible to ICH0. HLSTB

AD23

HLSTB

G17

AD24

HLSTB#

H17

AD25

HCOMP

M17

AD26

HUBREF

J13

PIRQ#A

D10

AD29

PIRQ#B

A10

PIRQ#B

AD30

PIRQ#C

B10

PIRQ#C

PIRQ#D

C10

PIRQ#D

IRQ14

P11

IRQ15

N14

IRQ15

C_BE#2

APICCLK

C16

APICCLK_ICH

C_BE#3

APICD1

C17

APICD1

APICD0

E16

APICD0

SERIRQ

R4

SERIRQ

8

HLSTB#

8

IHCOMP_PU

HUBREF

8

AD27 AD28

AD31

IRQ

C_BE#0 C_BE#1

PCICLK

PIRQ#A

17,18,27,33 17,18,33

0.1UF

17,18,33

Place C302 as close as possible to ICH0.

17,18,33

IRQ14

C302

19,33 19,33 6

B

4,33 4,33 16,18,33

FRAME# DEVSEL#

REQ#0

A14

PREQ#0

IRDY#

REQ#1

B13

PREQ#1

TRDY#

REQ#2

B12

PREQ#2

REQ#3

D12

PREQ#3

GNT#0

A13

PGNT#0

GNT#1

C13

PGNT#1

GNT#2

A12

PGNT#2

GNT#3

C12

PGNT#3

GNT4#

A11

RESV0PU

REQ4#

B11

RESV1PU

HL11

F16

STOP#

PCI

PCIRST# PLOCK# PAR SERR# PME#

REQ#A/GPIO0 GNT#A/GPIO16

PC/PCI

REQ#B/GPIO1/REQ5#

RESV2PD

17,33 17,33 18,33 27,33 17,33 17,33

VCC3_3

18,33 27,33

R174 R175

R181

8.2K

8.2K

0K

GNT#B/GPIO17/GNT5#

Don’t Stuff R181 For Test/Debug

R2

VSS1

SERR# PCI_PME#

NMI

VSS11

AD12

B16

VSS12

C2

NMI

U

AD6

G14

AD11

INTR

K10

E4

E14

VSS9

AD10

INTR

AD5

VSS10

D3

INIT#

J10

D1

AD9

IGNNE#

E15

VSS8

E2

AD8

B17

INIT#

K9

AD7

IGNNE#

AD4

H10

E1

FERR#

AD3

VSS7

AD6

AD2

FERR#

VSS6

F5

A20M# USLP#

F15

J9

AD5

F13 E12

VSS5

F4

A20M# USLP#

K8

F3

AD4

D

AD1

H9

AD3

1

AD0

VSS4

F2

VSS3

G4

AD2

J8

G2

AD1

VSS2

AD0

H8

17,18,27

G3

AD[31:0]

VCC3_3_4

D

2

VCC1_8

VCC3_3_3

E3 VCC3_3_1

U14

VCC3_3_2

ICH0, Part 1

A

4

VCC3_3

A

VSS13

7

K15

8

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

ICH0, PART 1 DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

2-22-1999_10:37 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

13

OF

40

8

7

6

5

4

3

ICH0

JP20 Config 1-2 Normal 2-3 Clear CMOS

1.0UF

31 22

JP20

JP24_PD

3

2.2UF

11,12,25,28,33 11,12,25,28,33 33

1

R216 R202

1K

1K

VBAT

D14

SLP_S3#

K3

SLP_S3/GPIO24

THRM#

K2

SLP_S5

PWROK

J3

PWROK

PWRBTN#

M2

PWRBTN#

ICH_RI#

L3

RSMRST#

F1

RSMRST#

SUS_STAT#

L4

SUSSTAT#/GPIO25

33

R_VBIAS

6

C347

6 6

2200PF

SMBDATA SMBCLK SMBALERT#

SMBDATA

J2

SMBCLK

M1

1

+

10M

Socketed CR2032

14,26

Y3 1

26,33

2

26,33 3

C346

32.768KHZ

12PF

14,31 12PF

16,33 18,33 33 33 18,33 33 31

B

31 28 28

JP17 S TRA P (S PK R) IN No Reboot on 2nd watc hdog tim eout OUT Reboot on 2nd watc hdog tim eout

15,16 15,16 15,16

(A C_S DOUT) Forc e U freq strap to safe m ode (1111) Use U freq s trap in ICH regis ter

15,16 15,16 16 33

ICH_SPKR

JP17

20 20 20

JP13_PD

10K R187 JP14_PU

A

R209 10K

20

C15

BAT17

SDCS#1 PDCS#3

SDCS#3

L16

SDCS#3

PDA0

R12

PDA0

PDA1

T12

PDA1

PDA2

P12

PDA2

SDA0

M16

SDA0

SDA1

M15

SDA1

SDA2

L13

SDA2

PDDREQ

U11

CLK48

SDDREQ

P17

SDREQ

PDDACK#

U12

PDDACK#

SDDACK#

M13

SDDACK#

PDIOR#

R11

PDIOR#

SDIOR#

N16

SDIOR#

PDIOW#

T11

PDIOW#

SDIOW#

N15

SDIOW#

PIORDY

N11

PIORDY

SIORDY

N17

SIORDY

H2

VBIAS

RTCX1

H3

RTCX2

H4

RTCX2

H1

RTCRST#

T1

AC_RST#

RTCX1

AC_RST# AC_SYNC

T3

AC_BITCLK

R3

AC_BITCLK

AC_SDOUT

T2

AC_SDOUT

AC_SDIN0

U1

AC_SDIN0

AC_SDIN1

P3

AC_SDIN1/GPIO9

ICH_SPKR

U3

SPKR

AC_SYNC

AC97

INTEL 82801AB PART 2 IDE

LPC_SMI# LPC_PME# GPIO7 GPIO12

D11

GPIO5

E11

GPIO6

E9

GPIO7/PERR#

N4

GPIO12

GPIO13

L2

GPIO13

GPIO21

B14

GPIO21

D13

GPIO22

GPIO22

GPIO

GPIO23_FPLED

D15

GPIO26_FPLED

K4

GPIO26/SUSCLK

GPIO27

M5

GPIO27

GPIO28

L5

GPIO28

LAD0/FWH0

R6

LAD1/FWH1

U5

LAD2/FWH2

GPIO23

LAD0/FWH0 LAD1/FWH1

T5

LAD2/FWH2

LAD3/FWH3

T4

LAD3/FWH3

LFRAME#/FWH4

U4

LFRAME#/FWH4

T6

LDRQ#0

LDRQ#0 LDRQ#1

N3

LPC

LDRQ#1/GPIO8

USBP1P

R1

USBP1P

USBP1N

P2

USBP1N

P1

USBP0P

N2

USBP0N

M4

OC#1

USBP0P USBP0N OC#0

M3

USB

OC#0

Minimize Stub Length to Jumpers

19

19

CLK14

CLK66

19

SDA[2:0]

U2 A16

19

19

USBCLK ICH_3V66

19

PDA[2:0]

INTRUDER#/GPIO10

VCC3_3 20

PDCS#1

L14 U13

J4

C366

16,33

JP18 IN OUT

N1

SYSTEM

SMBALERT#/GPIO11

10M

26

N12

SDCS#1 PDCS#3

PDCS#1

U6

R197

26

1K

ICH_CLK14

C

R220

R173 C

0.1UF

INTRUDER#

VBIAS

26

A

D

RI#

J1

C294

5VREF

THERM#

1.0UF

2 RTCRST#

+

A

28

C364

2

BAT17

8.2K

CR14

28,32

1

VBATC_DLY

R203

SLP_S5#

28,32

VBATC

R219

R85

VCCSUS1

33 29,32

U14

VCCSUS2

C349

10K

G1

C

A

1K

10K

VCCRTC

R85 and R203 for Test/Debug

L1

C290

BAT17

D

2

CR11

ICH5VREF

R206

14,31

VCC5

VRTC

VCC3SBY

CR13

X3

1 VCC3_3

VCC3SBY

PART 2

C

2

VCC3SBY

PDREQ

PDD0

R10

PDD0

PDD1

N9

PDD1

PDD2

R9

PDD2

PDD3

U9

PDD3

PDD4

R8

PDD4

PDD5

U8

PDD5

PDD6

R7

PDD6

PDD7

U7

PDD7

PDD8

P7

PDD8

PDD9

N7

PDD9

PDD10

T8

PDD10

PDD11

P8

PDD11

PDD12

T9

PDD12

PDD13

P9

PDD13

PDD14

T10

PDD14

PDD15

P10

PDD15

SDD0

P15

SDD0

SDD1

R16

SDD1

SDD2

T17

SDD2

SDD3

U16

SDD3

SDD4

U15

SDD4

SDD5

R14

SDD5

SDD6

P13

SDD6

SDD7

T13

SDD7

SDD8

U14

SDD8

SDD9

T14

SDD9

SDD10

P14

SDD10

SDD11

T15

SDD11

SDD12

U17

SDD12

SDD13

R15

SDD13

SDD14

R17

SDD14

SDD15

P16

SDD15

19 19 19 19 19

C

19 19 19 19 19

PDD[15:0] 19

B

SDD[15:0] 19

A

JP18 C293 18PF

1.3 DRAWN BY:

14,26

R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

ICH0, PART 2

AC_SDOUT

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

5-26-1999_17:09

1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

14

OF

40

8

7

6

5

4

3

2

1

FirmWare Hub (FWH) Socket NOTE: This is a Socketed Implementation

D

D

VCC3_3

VCC3_3

C211

C355

0.1UF

0.1UF

C361

C259

0.1UF

0.1UF

VCC3_3 Distribute close to each power pin. X4 1 2

C353

C

3

C36

4

0.1UF

0.1UF

5 6 7 8

6

PCLK_6

9 10

R218

0K

R_VPP

13,17,18,24,27

PCIRST#

11 12 13 14

VCC3_3

VCC3_3

15 16

19 19

P66DETECT

18 19

JP21

WPROT

40PIN_TSOP_SKT 40

GNDA

IC

VCCA

NC3

FWH4

NC4

INIT#

NC5

RFU36

NC6

RFU35

FGPI4

RFU34

NC8

RFU33

CLK

RFU32

VCC10

VCC31

VPP

GND30

RST#

GND29

NC13

FWH3

NC14

FWH2

FGPI3

FWH1

FGPI2

FWH0

FGPI1

ID0

FGPI0

ID1

WP#

ID2

TBL#

ID3

39 38

LFRAME#/FWH4

37

INIT#

14 4,13,33

C

36 35 34 33 32 31 30 29 28

LAD3/FWH3

27

LAD2/FWH2

26

LAD1/FWH1

25

LAD0/FWH0

24

FWH_ID0

23

FWH_ID1

22

FWH_ID2

21

FWH_ID3

14,16 14,16 14,16 14,16

FGPI2_PD

R222

FGPI3_PD

20

FGPI4_PD

B

17

IC_PD

JP21 CONFIG IN Unlocked OUT Locked Default

S66DETECT

NC1

B

4.7K 1

2

3

4

1

2

3

4

TBLK_LCK 8.2K

0K

RP63

RP64 RP64 for Test/Debug 8

7

6

5

8

7

6

5

R223 4.7K

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

FIRMWARE HUB (FWH) DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

2-22-1999_10:37 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

15

OF

40

8

7

6

5

4

3

VCC5

VCC3_3

2

1

VCC3_3

Decoupling

VCC3_3

VCC5

14

D

14,15 14,15

2

+

1

Place near VREF pin C99 2.2UF

C287 0.1UF

C246 0.1UF

C297 0.1UF

C229 0.1UF

14,15 14,15

C323

14 0.1UF

LFRAME#/FWH4

24

LAD3/FWH3

23

LAD2/FWH2

22

LAD1/FWH1

21

LAD0/FWH0

20

LDRQ#0

25

PCIRST#

13,17,18,24,27

26 27

SUSSTAT_PU

14,33 Place 1 0.1UF cap near each power pin

13,18,33 6

23 23 23 23 13,33 13,33

C 31 31

LPC_PME#

17

SERIRQ

30

PCLK_1

29

KDAT

56

KCLK

57

MDAT

58

MCLK

59

RCIN#

63

A20GATE

64

IRRX

61

IRTX

62

C356 470PF

C371

22 22

470PF

22 22 22 22 22 22

84

TXD0

85

DSR#0

86

RTS#0

87

CTS#0

88

DTR#0

89

RI#0

90

DCD#0

91

RXD#1

22 22 22

95

TXD1

96

DSR#1

97

RTS#1

22 22 22

B

RXD#0

22 22

98

CTS#1

99

DTR#1

100

RI#1

92

DCD#1

94

65

53

93 VCC3

VCC2

VCC1

VTR

VREF

U15

44

R183 4.7K

18

Super I/O

LAD3

INIT#

LAD2

SLCTIN#

LAD1

PD7

LAD0 LDRQ#

PD6

LPC I/F

PD5 PD4

LRESET#

PARALLEL PORT I/F

LPD# PME#

PD3 PD2

SERIRQ

PD1

SIO

PCI_CLK

PD0 SLCT#

LPC47B27X

KDAT

PE

KCLK

BUSY

MDAT

ACK#

MCLK

KYBD/MSE I/F

ERROR#

KBDRST

ALF# STROBE#

A20GATE

IRRX2/GP34 IRTX2/GP35

FAN2/GP32

INFRARED I/F

FAN1/GP33

RXD1

FDC_PP/DDRC/GP43

23 23 23 23 23 23 23 23 23 23 23 23

DRVDEN#1

2

DRVDEN#0

1

MTR#0

3

DS#0

5

DIR#

8

STEP#

9

WDATA#

10

WGATE#

11

HDSEL#

12

INDEX#

13

TRK#0

14

WRTPRT#

15

RDATA#

16

DSKCHG#

23

4

66

PAR_INIT#

67

SLCTIN# PDR[7:0]

75

PDR7

74

PDR6

73

PDR5

72

PDR4

71

PDR3

70

PDR2

69

PDR1

68

PDR0

21 21 21

SLCT#

77 78

PE

79

BUSY

80

ACK#

81

ERROR#

82

ALF#

83

STROBE#

54

PWM2

55

PWM1

21 21 21 21 21 21 21

C

31 31

SIO_GP43

28

TXD1 DSR1# RTS1# CTS1#

Test/Debug Header Unused GPIOs

SERIAL PORT 1

J23

DTR1# RI1# DCD1#

1

2

3

4

5

6

RXD2_IRRX TXD2_IRTX DSR2# RTS2#

SERIAL PORT 2

CTS2#

GP60/LED1

DTR2#

GP61/LED2

RI2#

GP27/IO_SMI# GP30/FAN_TACH2

DCD2#

GP31/FAN_TACH1

23

D

LFRAME#

DRVDEN1

GP25/MIDI_IN

DRVDEN0

GP26/MIDI_OUT

48

SIO_GP60

49

SIO_GP61

50

LPC_SMI#

51

TACH2 TACH1

52 46

MIDI_IN

47

MIDI_OUT

32

J1BUTTON1

33

J1BUTTON2

34

J2BUTTON1

35

J2BUTTON2

36

JOY1X

37

JOY1Y

38

JOY2X

39

JOY2Y

41

KEYLOCK#

B 14,33 31 31 23 23

MTR0# DS0#

GP10/J1B1

DIR#

GP11/J1B2

STEP#

GP12/J2B1

WDATA# WGATE#

GP13/J2B2

FDC I/F

GP14/J1X

HDSEL#

GP15/J1Y

INDEX#

GP16/J2X

TRK0#

GP17/J2Y

WRTPRT#

GP20/P17

RDATA#

GP21/P16

DSKCHG#

GP22/P12

42

SIO_GP21

43

SIO_GP22

23 23 23 23 23 23 23 23 31

A CLKI32

CLOCKS

GP24/SYSOPT

45

A

SYSOPT Pulldown on SYSOPT for IO address of 0x02E

AVSS

GND4

GND3

CLOCKI GND1

19

GND2

6

SIO_CLK14

6

R180

40

76

7

60

31

4.7K REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

SUPER I/O DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

16

OF

40

8

7

6

PCI Connector 0 (DEV Ah)

5

4

PCI Connector 1 (DEV Bh)

VCC3SBY VCC3_3

VCC12M

VCC5

VCC5

13,17,18,33 13,17,18,33 18 18

6 13,33

PTCK

17,18

13,17,18,33 17,18,27 13,17,18,27,33

PTMS

B4

A4

PTDI

B5

A5

PIRQ#A

PIRQ#D

B8

A8

PRSNT#11

B9

A9

B10

A10

B11

A11

B12

A12

B13

A13

B14

A14

B15

A15

B16

A16

13,17,18,27

B

A3

PIRQ#C

C_BE#[3:0]

13,17,18,27,33

A2

B3

A7

13,17,18,27

13,17,18,27,33

A1

B2

A6

AD[31:0]

C

PTRST#

B1

B7

PCIRST# PGNT#0

A17 A18 A19

AD31

B20

A20

AD29

B21

A21

B22

A22

AD28

AD27

B23

A23

AD26

AD25

B24

A24

B25

A25

PCI_PME# AD[31:0]

AD30

13,17,18,27,33 13,17,18,33

13,17,18,33 13,17,18,27,33 18

B26

A26

AD23

B27

A27

B28

A28

AD22

AD21

B29

A29

AD20

AD19

B30

A30

B31

A31

AD18

AD17

B32

A32

AD16

C_BE#2

B33

A33

R_AD16

R168

A4

PTDI

B5

A5

B6

A6

PIRQ#B

A7

PIRQ#D

A8

PRSNT#21

B9

A9

B10

A10

PRSNT#22

B11

A11

7,13,15,16,17,18,19,24,27 13,33

13,33

PCLK_3 PREQ#1 AD[31:0]

13,17,18,27

13,17,18,27

AD16

13,17,18,27

FRAME#

A34 A35 A36

B37

A37

B38

A38

PLOCK#

B39

A39

PERR#

B40

A40

SDONEP1

B41

A41

SBOP1

B42

A42

TRDY# STOP#

PAR

B43

A43

C_BE#1

B44

A44

AD14

B45

A45

B46

A46

AD13

AD12

B47

A47

AD11

AD10

B48

A48

B49

A49

A13

B14

A14

B15

A15

B16

A16

B17

A17

13,17,18,27,33 13,17,18,27,33 13,17,18,27,33 33

13,17,18,27,33 13,17,18,33 17,18,27 13,17,18,27,33

PCIRST# PGNT#1

A18

B19

A19

AD31

B20

A20

AD29

B21

A21

B22

A22

AD28

AD27

B23

A23

AD26

AD25

B24

A24

B25

A25

AD24

C_BE#3

B26

A26

R_AD17

AD23

B27

A27

B28

A28

AD22

AD21

B29

A29

AD20

AD19

B30

A30

B31

A31

AD18

B32

A32

AD16

B33

A33

DEVSEL#

R191

FRAME#

A34

B35

A35

B36

A36

B37

A37

B38

A38

AD17

TRDY# STOP#

B39

A39

PERR#

B40

A40

SDONEP2

B41

A41

SBOP2

SERR#

B42

A42

B43

A43

B44

A44

C_BE#1 AD14

13,17,18,27

AD15

AD12 AD10

13,17,18,33 13,17,18,33

7,13,15,16,17,18,19,24,27 13,33 13,17,18,27 13,17,18,27

C

PLOCK#

33

D

17,18,33

13,17,18,27

100

AD17

IRDY#

PCI_PME# AD[31:0]

AD30

C_BE#2

B34

13,17,18,27,33

17,18 17,18,33

A12

B13

B18

13,17,18,27

PAR

13,17,18,27,33 13,17,18,27,33 13,17,18,27,33 33 33

B

13,17,18,27

AD15

B45

A45

B46

A46

AD13

B47

A47

AD11

B48

A48

B49

A49

AD9

key

AD9

key

33

B4

B8

100

B36

AD8

B52

A52

AD7

B53

A53

B54

A54

AD6

AD5

B55

A55

AD4

AD3

B56

A56

B57

A57

AD2

B58

A58

AD0

B59

A59

B60

A60

B61

A61

B62

A62

PU1_ACK64#

PTMS

B7

C_BE#[3:0]

B35

AD1

A3

PIRQ#A

13,17,18,27

B34

A

A2

B3

PIRQ#C

AD24

C_BE#3

SERR#

17,18,33

6

B19

DEVSEL#

17,18

PTRST#

A1

B2

B12

B18

IRDY#

PTCK

17,18,33

18

B17

PREQ#0

VCC5 VCC12

J16 PCI3_CON

B6

PCLK_2

VCC12M VCC5 VCC3_3

B1

PIRQ#B

PRSNT#12

1 VCC3SBY

J17 PCI3_CON

17,18

2 VCC3_3

VCC12

VCC3_3

D

3

C_BE#0

13,17,18,27

B52

A52

AD7

B53

A53

B54

A54

AD6

B55

A55

AD4

AD5 AD3 AD1

33

PU1_REQ64#

C_BE#0

AD8

PU2_ACK64#

B56

A56

B57

A57

AD2

B58

A58

AD0

B59

A59

B60

A60

B61

A61

B62

A62

PU2_REQ64#

13,17,18,27

33

A

33

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

PCI CONNECTORS 1 AND 2 DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

17

OF

40

8

7

6

PCI Connector 2 (DEV 6h)

5

4

3

2

VCC3_3

VCC12M

VCC5

VCC5

VCC12

VCC3_3

J22 PCI3_CON

17,18

D

PTCK

13,17,33 18 14,33 18

A1 A2

B3

A3

PTMS

B4

A4

PTDI

A6

PIRQ#C

B7

A7

PIRQ#A

PIRQ#B

B8

A8

PRSNT#31

B9

A9

B10

A10

B11

A11 R_GNT#A

R185

B12

A12

0K

GPIO21 PRSNT#32

R194 0K

R_GPO21

For Debug Only

B13

A13

R_SERIRQ

B14

A14

For Debug Only

B15

A15

6 13,33

B16

A16

B17

A17

B18

A18

B19

A19

AD31

B20

A20

AD29

B21

A21

SERIRQ 0K PCLK_4 PREQ#2 AD[31:0]

13,17,18,27

C

13,17,27,33 13,17,27,33 13,17,33 17,18,27

B

13,17,27,33

5.6K

AD28 AD26

AD25

B24

A24

PCI_PME# AD[31:0]

A25

AD24

A26

R_AD22

AD23

B27

A27

B28

A28

AD22

AD21

B29

A29

AD20

AD19

B30

A30

B31

A31

AD18

AD17

B32

A32

AD16

C_BE#2

B33

A33

B34

A34

B35

A35

B36

A36

DEVSEL#

B37

A37

B38

A38

PLOCK#

B39

A39

PERR#

B40

A40

SDONEP3

B41

A41

SBOP3

B42

A42 A43 A44 A45

PRSNT#22 PRSNT#21 PRSNT#12

17

7,13,15,16,17,19,24,27

PRSNT#11

0K R192

13,33 13,17,27

0K Do Not Stuff R192

PCI_REQ#A

13,33

C336

C337

C267

C284

C335

C342

For Debug Only 0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

13,17,18,27

C

B26

B45

PRSNT#31

17

17

B25

B44

13

R193

AD30

A23

B43

PRSNT#32

18 17

PGNT#2

A22

AD14

13,17,27,33

For Debug Only

PCIRST#

B23

C_BE#1

13,17,33

VAUX3

B22

SERR#

D

R190

17,33

18

AD27

IRDY#

5.6K PTCK

17,18

17,33

VCC3SBY PCI_GNT#A

C_BE#3

C_BE#[3:0] 13,17,27

R189

PTRST#

17,18

17,18

A5

B6

PIRQ#D

R195 13,16,33

PTRST#

B1 B2

B5

13,17,33

1

Layout Note: Should be in Slot 0 Position (Outside Edge of Board Furthest from U)

R167

AD22

13,17,18,27

100

FRAME# TRDY# STOP#

PAR

13,17,27,33 13,17,27,33 13,17,27,33

JP19

33

17,18,27

33

B46

A46

AD13

B47

A47

AD11

AD10

B48

A48

B49

A49

1

PERR#_PU

3

GPIO7

33

B

2

14,33

13,17,27

AD15

AD12

PERR#

JP19 - ICH/ICH0 Compatibility 1-2 ICH0 Default 2-3 ICH

AD9

key

B52

A52

AD7

B53

A53

B54

A54

AD6

AD5

B55

A55

AD4

AD3

B56

A56

AD1

A 33

PU3_ACK64#

C_BE#0

AD8

B57

A57

AD2

B58

A58

AD0

B59

A59

B60

A60

B61

A61

B62

A62

13,17,27

A PU3_REQ64#

33

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

PCI CONNECTOR 3 DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

18

OF

40

8

7

6

5

4

3

2

1

ULTRAATA/33 IDE CONNECTORS VCC5

PRIMARY IDE CONN.

VCC5

D PDD[15:0]

14 R133 PCIRST_BUF#

R100

J15

1K

R140 33

R_RSTP#

1

2

PDD7

3

4

PDD8

PDD6

5

6

PDD5

7

8

9

PDD4

14 14 14 14

C

14 13,33

14 31

D

SDD[15:0]

14

19

SECONDARY IDE CONN.

J12

1K

R139

PCIRST_BUF#

R_RSTS#

1

2

SDD7

3

4

SDD8

PDD9

SDD6

5

6

SDD9

PDD10

SDD5

7

8

SDD10

9

19

33

10

PDD11

SDD4

10

SDD11

PDD3

11

12

PDD12

SDD3

11

12

SDD12

PDD2

13

14

PDD13

SDD2

13

14

SDD13

PDD1

15

16

PDD14

SDD1

15

16

SDD14

PDD0

17

18

PDD15

SDD0

17

18

SDD15

19

20

19

20

PDREQ

21

22

SDREQ

21

22

PDIOW#

23

24

PDIOR#

25

26

PIORDY

27

28

PDDACK#

29

30

IRQ14

31

32

PDCS#1 IDEACTP# PDA[2:0]

PDA1

33

34

PDA0

35

36

37

38

39

40

14 For Host-Side 80-Conductor Cable Detection: Populate R96 and R221, DePopulate C187 For Drive-Side 80-Conductor Cable Detection: Populate C187, DePopulate R96 and R221

PRI_PD1

14 14 14 14 13,33

R96

P66DETECT

R_P66DET

23

24

25

26

SIORDY

27

28

SDDACK#

29

30

IRQ15

31

32

15

0K PDCS#3

14

14

31

PDA2

14

SDIOW# SDIOR#

14

R135

R138

R101

5.6K

10K

470

SDCS#1 IDEACTS# SDA[2:0]

33

34

SDA0

35

36

37

38

39

40

For Host-Side 80-Conductor Cable Detection: Populate R94 and R95, DePopulate C186 For Drive-Side 80-Conductor Cable Detection: Populate C186, DePopulate R94 and R95 R95

S66DETECT

R_S66DET

C

15

0K SDCS#3

14

SDA2

C187 R221 0.047UF

SDA1

PRI_SD1

R134

R137

R132

5.6K

10K

470

C186 R94

0.047UF

15K

15K

VCC3_3

B

B VCC3_3

R141 U11

8.2K

13,17,18,24,27

14

VCC

PCIRST#

5

PCIRST_BUF#

6

19

7 GND SN74LVC07A

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

ULTRAATA/33 CONNECTORS DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

2-22-1999_10:37 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

19

OF

40

8

7

USB Connectors

6

5

4

1

Do Not Stuff AC97_USB- R149 0K

2

26 POLYSWITCH RUSB250

F3

AC97_USB+

26

2.5A

R148 0K

D 1

D

2

VCC5

VCC3_3

R147 330K

3

L23 USBV5

1

2

1

C202

+

AC97_OC#

26

C12

68UF

0.1UF

2

R146 0K

R72 470K

Do Not Stuff

USBV0

14

C124 .001UF

R13

R_USBP0N

15

0K R205

USBP0P

14

USBD0N R15

R_USBP0P

15

R201 560K

USBD0P

0K USBG0 R14

15K

15K

47PF

47PF

C

R11 C359

C348

2

OC#0

14

R204

USBP0N

C15 L11

USB-CON2 1 1

Place R204, R205, C348, and C359 within 1" of ICH0

2 3 4 5

L9 1

C

J3

470PF

6 2

7 8

VCC1 DATA1DATA1+ GND1 VCC2 DATA2DATA2+ GND2

1

C9

+

C201 68UF

2 - USB Stacked

0.1UF

2

USBV1 R214

USBP1N

14

USBD1N

15

B

R211 15

USBP1P

14

USBD1P

B

USBG1

C358

C357

47PF

R12

R63

C13

15K

15K

47PF

C8 C16

47PF

C98

2

47PF

47PF

C14

47PF

Place CAPs as close as possible to connector.

L10

470PF 1

Place R214, R211, C357, and C358 within 1" of ICH0

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

USB CONNECTORS DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

20

OF

40

8

7

6

5

4

3

2

1

Parallel Port Header

D

D

VCC5

CR1 A

C

PARV5

8

7

6

5

3

4

RP13 2.2K

2

6

5

7

8

6

7

RP17 2.2K

1

RP28 2.2K

R224

5

8

6

7

5

8

1N4148

RP14 2.2K

16

4

3

2

1

4

3

2

1

4

3

1

C

2

2.2K

C

ERROR# RP16

16 16 16 16

16

SLCTIN#

1

8

R_SLCTIN#

PAR_INIT#

2

7

R_PARINIT#

ALF#

3

6

R_ALF#

STROBE#

4

5

R_STROBE#

PDR[7:0]

33 RP15

J5

PDR0

1

8

R_PDR0

PDR1

2

7

R_PDR1

PDR2

3

PDR3

6

4

2

3

4

5

6

7

8

R_PDR3

9

10

R_PDR2

5

33 RP27

B

1

PDR4

1

8

R_PDR4

11

12

PDR5

2

7

R_PDR5

13

14

PDR6

3

6

R_PDR6

15

16

PDR7

4

5

R_PDR7

17

18

19

20

21

22

23

24

25

26

33

BUSY

180PF

180PF

C91

C97

C94

C90

C89

C95 180PF

180PF

180PF

C93

180PF

C190

C88

180PF

C193

C92

180PF

180PF

C196

C96

C189

180PF

C192

180PF

C194

180PF

SLCT#

180PF

PE

180PF

16

180PF

C197 16

180PF

16

ACK#

180PF

16

B

J5 Pinned Out for IDC (Flow Through) Ribbon Cable Connector

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

PARALLEL PORT DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

2-22-1999_11:02 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

21 OF

40

8

7

6

5

4

3

2

1

Serial Port/COM Headers VCC12VCC5

VCC12 J19 and J21 pinned out for IDC (Flow Through) Ribbon Cable Connector U17

D

D 16 16 16 16 16 16 16 16

DCD#0

19

RXD#0

18

DSR#0

17

DTR#0

16

TXD0

15

CTS#0

14

RTS#0

13

RI#0

12 11

VCC

VCC12

RY0

RA0

RY1 RY2 DA0 DA1

GD75232

20

RA1 RA2 DY0 DY1

RY3

RA3

DA2

DY2

RY4

RA4

GND

VCC-12

1 2

DCD#0_C

3

RXD#0_C

4

DSR#0_C

1

2

5

DTR#0_C

3

4

6

TXD#0_C

5

6

7

CTS#0_C

7

8

8

RTS#0_C

9

10

9

RI#0_C

J21

10

C325

C327

C329

C368

100PF

100PF

100PF

100PF

COM1 and COM2 are 2x5 pin Headers for a cabled port. VCC3SBY C326

C328

C330

C369

100PF

100PF

100PF

100PF

Place Close to Header

C

C R230

10K RI#_CR_C

3

2

ICH_RI#

D

R227

Q10 3

2N7002LT1

1

47K

G ICHRI#_C

2

VCC5 R229

If not populated at all, remove CR14 and short RI#0_C to RI#CR

VCC12

C374

47K

U16

1.0UF 20

16 NOTE: If Wake from S3 on Serial Modem is not ed do not stuff CR15 and Q10.

B

2nd COM Header Option

VCC12-

S

16 16 16 16 16 16 16

DCD#1

19

RXD#1

18

DSR#1

17

DTR#1

16

TXD1

15

CTS#1

14

RTS#1

13

RI#1

12 11

VCC

VCC12

RY0

RA0

RY1 RY2 DA0 DA1

GD75232

14

CR15 BAT54C 1

RA1 RA2 DY0 DY1

RY3

RA3

DA2

DY2

RY4

RA4

GND

VCC-12

1 2

DCD#1_C

3

RXD#1_C

4

DSR#1_C

1

2

5

DTR#1_C

3

4

B

J19

6

TXD#1_C

5

7

CTS#1_C

7

8

8

RTS#1_C

9

10

6

RI#1_C

9 10

C316

C314

100PF

C315

100PF

C311

100PF

100PF

C312

C313

C309

C310

100PF

100PF

100PF

100PF

Place Close to Header

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

SERIAL AND GAME PORTS DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

2-22-1999_11:02

1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

22

OF

40

8

7

6

5

4

3

KEYBOARD/MOUSE PORTS

VCC5

L3

F2 2 1 PS2V5_F

1

FLOPPY DISK HEADER

VCC5

1

2

PS2V5

2

1.25A

D

D 6

7

5

8

RP31

RP1 4.7K 4

KCLK

1

4 5

L_KCLK

2

R143 1K

16

6 L7 MDAT

1

16

7

L_MDAT

2

17

9 L6 1

10 2

11

L_MCLK

PS/2 Mse

8

MCLK

5

J1 1

L_KDAT

2

L4

16

6

1K

PS/2 Kybd

3

2

1

1

3

C

7

STACKED PS2 CONNECTOR

2

16

2

4

L5

16

8

3

KDAT

16

1

16

PS2GND

16

16 15

16

14

12

13 16

C4

C5

C2

C1

470PF

470PF

470PF

470PF

0.1UF

16 L1

2

C3

16 16 16

PS2_PD 2

1

16

L2

16 16

J14 1

4

3

DRVDEN#1

6

5

INDEX#

8

7

10

9

MTR#0

12

11

14

13

16

15

DIR#

18

17

STEP#

20

19

WDATA#

22

21

WGATE#

24

23

TRK#0

26

25

WRTPRT#

28

27

RDATA#

30

29

HDSEL#

32

31

DSKCHG#

34

33

DS#0

C

1

16

2

DRVDEN#0

GAME PORT HEADER J7 Pinned Out for IDC (Flow Through) Ribbon Cable Connector RP29 VCC5

B

R_JOY1X

1

8

JOY1X

R_JOY1Y

2

7

JOY1Y

R_JOY2Y

3

6

JOY2Y

R_JOY2X

4

5

JOY2X

16

B

16 16 16

2.2K

1

3

5

7

9

11

13

15

2

4

6

8

10

12

14

16

VCC5 VCC5

C199

C198

C191

C195

0.01UF

0.01UF

0.01UF

0.01UF

7

6

5 4

4.7K

3

4.7K

2

R178

8

R89

1

J7

RP30 1K

J1BUTTON1 J1BUTTON2 J2BUTTON2 J2BUTTON1

A 16

R88

MIDI_OUT MIDI_IN

16 16 16

A

R_MIDIOUT

47 16

16

R179

C179

C178

C79

C182

47PF

47PF

47PF

47PF

R_MIDIIN

47 C177

C176

470PF

470PF

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

KEYBOARD/MOUSE/FLOPPYGAME PORTS DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

2-22-1999_11:02 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

23

OF

40

8

7

Digital Video Out

6

5

4

3

2

1

VCC3_3 L26 2

1 FPP1V3

+

VCC3_3

2

10UF

100PF

100PF

D

1

C281

C275 C280 VCC3_3

D

L25 FPDV3 24

2

1

+ 2

C230 10UF

100PF

C271 C272 100PF

100PF

C231

100PF

C276 C277 100PF

+

C282 2

VCC1_8

1

FPAV3 1

1 L27

10UF

2

VCC1_8

R116

1K

FTVREF

38 39 40 41 42 43 44 45 46

FTD[11:0]

47

9 FTD11

50

FTD10

51

FTD9

52

FTD8

53

FTD7

54

FTD6

55

FTD5

58

FTD4

59

FTD3

60

FTD2

61

FTD1

62

FTD0

63

FTCLK0

56

FTCLK1

57

1

12

D22

TXC-

D21

TXC+

FLAT TRANSMITTER SII154

D18

D16/PFEN D15

TX0TX0+

D14

TX1-

D13

TX1+

D10

TX2-

D9

TX2+

EXT_RS

D7

TX0+

27

TX1-

28

TX1+

30

TX2-

31

TX2+

25 25

25 25

25 25

19 EXTRS_PU

D5

DKEN/RST

D4

TEST

D3

BSEL/SCL

D2

DSEL/SDA

D1

ISEL

D0

MSEN

EDGE/CHG

IDCLKIDCLK+

CTL1/A1/DK1 DE CTL2/A2/DK2 HS CTL3/A3/DK3

PCIRST#

35 34

B 13,17,18,24,27

TEST_PD

15

3VFTSCL

14

3VFTSDA

9,24,25 9,24,25

13

SL_STALL

11

9,24

10

3VHTPLG

9 8

A1_PD

7

A2_PD

6

A3_PD

25

GND0

R121

R118

R113

16

GND1 48

64

32

GND2

VS PGND

5

TX0-

25

25

D6

17

4

FTVSYNC

24

25

D8

AGND0

FTHSYNC

TXC+

D11

AGND2

9,24

2

22

D12

AGND1

9,24

FTBLNK#

TXC-

D19

D17

20

9,24

21

D20

26

9,24

Do Not Stuff R126

C

PD

9,24

4.7K

400

1%

VCC0

VCC1

18

49

23

33 VCC2

PVCC0

PVCC1

29

D23

AVCC0

3

AVCC1

100PF

36 37

B

R126 R165

VREF

C228

1K

0.01UF

C

R122

24

Place C226 near U28, pin 3 U7 C226

1K

1K

1K

Do Not Stuff

A

A

R124 R124 is for Test Only TEST pin may be tied direct to GND

4.7K FPDV3 24

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

DIGITAL VIDEO OUT DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

5-26-1999_17:13

1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

24

OF

40

8

7

6

5

4

3

2

1

Video Connectors VGA Connector

20 Pin Flat Connector

D

VCC5

VCC5

D

2

BLM11B750S is rated at 75Ohms at 100MHz

L21 VCC5

1

1

11

TX2+

TX1-

2

12

TX2-

3

13

4

14

5

15

24

16

7

17

8

18

3.3PF

1K

CR7

1 BAT54S

+

R74 1K

L12

J6

3

CR10

6

24

L_RED R75

Place R66,R67,&R69 Close to VGA Connector

5VHTPLG 25

2.2K

C203

VID_GREEN

9

C200

L_GREEN

2

2

75 1%

C105

C106

3.3PF

3.3PF

0K

5VFTSCL 0K

1 BAT54S

24,25

L_HSYNC

3

CR9

24,25

25 25

2

8

L_BLUE FUSE_5

5VFTSDA

C

3 13 9

MON2PU

4

L_VSYNC

14 10

5VDDCDA

5

R71

5VHSYNC

11

12

BLM11B750S

R67

Populate if DFP Device is also populated.

R103

6 1

11 7

1

VCC1_8

2

R105

1

MONOPU

L20

De-Bounce Circuit +

C

A

CON_HTPLG

CON_FTSCL

19 20

2

3.3PF

2.5A

-

1

9 10

TX0-

Protection Circuit for 20V Tolerance

C111

1

6

24

0.01UF

TXC-

24

TX0+

CON_FTSDA

TXC+

1N5821

C

24

R69 75 1%

24

C109

2

24

TX1+

R65

BLM11B750S

10UF

24

F1

2

VCC1_8

J8

1 CRT5V_F

VID_RED

9

10 5

15

15

0K

VCC5 VCC5

C122

C119

3.3PF

3.3PF

2

CR4 C

25

4.7K

R115

0.1UF

2.2K

C227

6

7

RP34

A 1N4148

5

8

QS4_3V

5V to 3.3V Translation/Isolation

1 BAT54S

25

Do Not Stuff C119 and C122

CR5

5VDDCCL

R64

5VVSYNC VCC5

QST3384 24

VCC

9 9 9 9 24 9,24 9,24 6 6

3VDDCDA

3

3VDDCCL

4

CRT_HSYNC CRT_VSYNC

7 8

3VHTPLG

11

3VFTSDA

14

3VFTSCL

17

CK_SMBDATA

18

CK_SMBCLK

21 22 1 13

1A1

1B1

1A2

1B2

1A3

1B3

1A4

1B4

1A5

1B5

2A1

2B1

2A2

2B2

2A3

2B3

2A4

5VDDCDA

5

5VDDCCL 5VHSYNC 5VVSYNC

9

5VHTPLG

10

R119

19 QSSDA 20 QSSCLR120

2B5

BEA#

GND

3.3PF

B

0K

C112

1 BAT54S

25

3

L19

25

9

25

VID_BLUE

1

R66 75 1%

24,25 11,12,14,28,33

SMBCLK

2

C101

10PF

C104

C103

10PF

3.3PF

3.3PF

2

11,12,14,28,33

0K

10PF C116

BLM11B750S

VCC1_8

24,25

SMBDATA

C208

10PF Do Not Stuff C100 and C102

CR6

25

5VFTSCL

16

2A5

25

5VFTSDA

15

23

C100

3.3PF 2

2

6

2B4

0K C102

4

3

2

1

B U6

3

1 BAT54S

3

12

CR8

BEB#

A

A

2.2K

R59 2.2K REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

R58 Do Not Populate

1.3

VIDEO CONNECTORS DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

25

OF

40

8

7

6

5

4

3

2

1

AUDIO/MODEM RISER

D

D

VCC12 VCC5

VCC12-

VCC3_3

VCC5 VCC3SBY

J18

B1 B2

31

AC97SPKR

B3 B4 B5 B6

C

B7 B8 B9 B10 B11

AUDIO_MUTE# GND[0]

AUDIO_PWRDWN MONO_PHONE

(ISOLATED)

MONO_OUT/PC_BEEP

RESV[5]

RESV[1]

RESV[6]

RESV[2]

RESV[7]

PRIMARY_DN#

GND[7]

-12V

+5VDUAL/5VSBY USB_OC

GND[1]

GND[8]

+12V GND[2]

USB+

+5VD

USB-

AC’97_RISER

KEY

B13 B14 B15 B16

14 14

AC_SDOUT

B17

AC_RST#

B18 B19 B20 B21 B22 B23

A2 A3 A4 A5 A6

C

A7

AC97_OC#

A8

20

A9 A10

AC97_USB+

A11

AC97_USB-

20 20

KEY

AMR_CONNECTOR

KEY B12

A1

KEY

GND[3]

GND[9]

RESV[3]

S/P_DIF_IN

RESV[4]

GND[10]

+3.3VD

+3VDUAL/3VSBY

GND[4]

GND[11]

AC97_SDATA_OUT

AC97_SYNC GND[12]

AC97_RESET# AC97_SDATA_IN3

AC97_SDATA_IN1

GND[5]

GND[13]

AC97_SDATA_IN2

AC97_SDATA_IN0 GND[14]

GND[6] AC97_MSTRCLK

AC97_BITCLK

A12 A13 A14 A15 A16

AC_SYNC

A17

14

A18

AC_SDIN1

A19

14,33

A20

AC_SDIN0

A21

14,33

A22

AC_BITCLK

A23

B

14

B

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

AUDIO/MODEM RISER DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

26

OF

40

8

7

6 VCC5

LAN

LAN Decoupling Distribute aroung Power Pins Close to 82559. VCC3SBY

C261

C184

C165

0.1UF

0.1UF

0.1UF

VCC3SBY

C180 0.1UF

C257 0.1UF

VCC3SBY

1

C255 +

2

2

+

1

C

4.7UF

Place C68/C255 Close to Ball A10

3

2

1

VCC3SBY

C_BE#[3:0]

13,17,18,33 13,17,18,33 13,17,18,33 13,17,18,33 13,17,18,33 13,17,18,33 17,18 13,17,18,27 13,33 13,33 7,13,15,16,17,18,19,24 6

L9

L5

L4

K11

K10

K9

K8

K7

K6

K5

K4

J11

J10

J9

J8

J7

J6

J5

H8

H7

H6

H5

G6

G5

E12

L10 VCC[25]

VCC[24]

VCC[23]

VCC[22]

VCC[21]

VCC[20]

VCC[19]

VCC[18]

VCC[17]

VCC[16]

VCC[15]

VCC[14]

VCC[13]

VCC[12]

VCC[11]

VCC[10]

VCC[9]

VCC[8]

VCC[7]

VCC[6]

VCC[5]

VCC[4]

VCC[3]

VCC[2]

VCC[1]

VCC[0]

N6

K3

E1

A7

A3

P2 VCP[5]

VCP[4]

VCP[3]

VCP[2]

VCP[0]

VCP[1]

A11 VCT

N8

P12 VCL[3]

K13

AD1

P6

AD2

LILED

A12

LILED

AD3

P5

AD3

ACTLED

C11

ACTLED

AD4

N5

AD4

SPEEDLED

B11

SPEEDLED

AD5

M5

AD5

TDP

C13

TDP

AD6

P4

AD6

TDN

C14

TDN

AD7

N4

AD7

RDP

E13

RDP

P3

AD8

RDN

E14

RDN

AD9

N3

AD9

SMBALRT#

B10

AD10

N2

AD10

CSTSCHG

C5

AD11

M1

AD11

PME#

A6

AD12

M2

AD12

FLA0/PCIMODE#

J13

AD13

M3

AD13

FLA1/AUXPWR

J12

28

28

PCI_PME#

13,17,18

R164

LANAPWR

3K

AD14

FLA2

K14

L2

AD15

FLA3

L14

AD16

FLA4

L13

AD17

E3

AD17

FLA5

L12

AD18

D1

AD18

FLA6

M14

AD19

D2

AD19

AD20

D3

AD20

AD21

C1

AD21

AD22

B1

AD22

AD23

B2

AD23

AD24

B4

AD24

AD25

A5

AD25

FLA13/EEDI

P10

EEDI

3

FLA7

M13 N14

FLA9/MRST

P13

FLA10/MRING#

N13

FLA11/MINT

M12

FLA12/MCNTSM#

M11

82559

VCC3SBY

U18

B5

AD26

FLA14/EEDO

N10

EEDO

4

B6

AD27

FLA15/EESK

M10

EESK

2

AD28

C6

AD28

FLA16

P9

AD29

C7

AD29

FLD0

F14

AD30

A8

AD30

FLD1

F13

AD31

B8

AD31

FLD2

F12

FLD3

G12

C_BE#0

M4

C/BE0#

FLD4

H14

C_BE#1

L3

C/BE1#

FLD5

H13 FLD5_PD

C_BE#2

F3

C/BE2#

FLD6

H12 FLD6_PD

C_BE#3

C4

C/BE3#

FLD7

J14

EECS

P7

F2

FRAME#

FLCS#

N9

IRDY#

F1

IRDY#

FLOE#

M8

FLWE#

M9

TRDY#

G3

TRDY#

DEVSEL#

H3

DEVSEL#

STOP#

H1

STOP#

J1

CLKRUN# TEST

PAR

TCK

D14

INTA#

PERR#

J2

PERR#

TI

SERR#

A2

SERR#

TO

AD20

R153

PREQ#3

100

IDSEL

RBIAS10

C3

REQ#

RBIAS100

B13 RBIAS100

PGNT#3

J3

GNT#

VREF

PCIRST#

C2

RST#

NC11

PCLK_5

G1

CLK

NC10

LAN_ISOLATE#

B9

ISOLATE#

NC8

LAN_RST#

A9

ALTRST#

NC7 NC6

C9

SMBCLK

NC5

SMBD

NC4 NC3

VIO

G2

VIO

N11

X1

P11

X2

NC2

A

25MHZ

22PF

22PF

R163 619 EECS

R154 62K

B

R152 4.7K

R156 549

R155 619

C12 D10 G4 A14 J4 L7 P1 D9 L8 P14 H4 A1

A

VSS[31]

VSS[30]

VSS[29]

VSS[28]

VSS[27]

VSS[26]

VSS[25]

VSS[24]

VSS[23]

VSS[22]

VSS[21]

VSS[20]

VSS[19]

VSS[18]

VSS[17]

VSS[16]

VSS[15]

VSS[14]

VSS[13]

VSS[12]

VSS[11]

VSS[10]

VSS[9]

VSS[8]

VSS[7]

VSS[6]

VSS[5]

VSS[4]

VSS[3]

VSS[2]

VSS[1]

VSS[0]

VSSPP[5]

VSSPP[4]

VSSPP[3]

VSSPP[2]

VSSPP[1]

VSSPP[0]

VSSPT

VSSPL[3]

VSSPL[2]

VSSPL[1]

619

L6

L11

H11

H10

H9

G11

G10

G9

G8

G7

F11

F10

F9

F8

F7

F6

F5

F4

E11

E10

E9

E8

E7

E6

E5

E4

D11

D8

D7

D6

D5

D4

N1

M6

K2

E2

B7

B3

C10

N12

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

LAN

0.1UF R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

7

6

Do Not Stuff R162

DRAWN BY:

8

7

C265 P8

C269

G14

C331

K12

LAN_XTAL2

VSSPL[0]

NC1 LAN_XTAL1

NC1

EECS

D12

B14 RBIAS10

A10

NC2

EESK

B12

A4

R_LANIDS

EEDO

5

A13 LAN_TEST D13

VCC EEDI

GND

C8 LANCLKRUN

TEXEC

H2

1

C

8

93C46

AD27

FRAME#

Y2

28

L1

L_SMBD

28

28

K1

FLA8/IOCHRDY

D

28

AD16

L_SMBCLK

28

28

AD15

NC9

28

28

28

AD8

PIRQ#A

13,17,18,33

VCL[2]

G13

AD0

M7

PAR

13,17,18

VCL[0]

N7

AD2

AD26

4.7UF

13,17,18

B

4

VCC3SBY

AD1

AD14

0.1UF

C68

5%

AD0

VCL[1]

U13

4.7K AD[31:0]

13,17,18

C334

VCC3SBY

VCC3SBY R159

D

5

VCC3SBY

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

27

OF

40

8

7

6

5

4

3

2

1

VCC3SBY

LAN

VCC3SBY

R111 330

D

27

TDN

12

27

RDP

9

27

RDN

7

5

14

SPEEDLED

JP7

JP11

JP12

27,28

27,28 27,28

RJ-8

TDC

SPEEDLED

8

11 TDC

27,28

LILED ACTLED

C

TXC_PD

RXC_PD

C

RDC

27,28

RDC

TXC 1

C268 0.1UF

RJ78_PD

C266 0.1UF

330

27,28

RJ-7

4

RJ45_PD

Do Not Stuff

RD_PD

LILED

330

13

RJ-5

3 TD_PD

ACTLED

330

RJ-4

6

SHLD2

R161 50

RJ-45

RD-

SHLD1

R160 50

330

RXC

R158 50

R112

LI_CR

16

RD+

18

R157 50

15

TD-

2

Place Termination near 82559

RJMAG

R145

JP23_PU

TD+

17

27

10

R144

JP18_PU

J9 TDP

R108

JP7_PU

ACT_CR

D

R107

R110

R106

R109

75

75

75

75

C213

C212

0.1UF

0.1UF

Do Not Stuff RJMAG_CONN

VCC3SBY C210 Default Config: Do Not Stuff For EST Testing

470PF-1500V

Note: Chassis Ground, use plane for this signal R215 4.7K

Note: Chassis Ground, use plane for this signal

11,12,14,25,33

JP8

SMBCLK

1

GPIO27

3

2

14

JP8_SMBC

R151

L_SMBCLK

0K

27

B

B

VCC3SBY

Select JP8/JP9 ICH0 1-2 Default ICH 2-3 14

SUS_STAT#

R210

R186 4.7K

0K

14,29,32

PWROK

JP9

LAN_ISOLATE#

27

R198

11,12,14,25,33

1

GPIO28

3

2

0K

14

Do Not Stuff R198

RSMRST#

JP9_SMBD

R150

L_SMBD

0K

27

LAN DISABLE - JP10 Normal 1-2 Default Disable 2-3

JP10 14,32

SMBDATA

1

LAN_RST#

2

A

27

A

3

Note: This circuit is for debug purpose only.

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

LAN DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

28

OF

40

8

7

6

5

Voltage Regulators

4

VCC3_3

3

V3SB

2

1

VCC3SBY

1N5822 C

A NDS356AP

D

G

S

S

D

47UF D

2

47UF

CR2

C75

+

2

This generates 3.3V Standby Power which is on in S0,S1,S3,S4,&S5. It es 3.3V from the ATX supply in S0/S1, and 3.3VSB (generated by VR2 below) in S3/S4/S5.

1

1

C174

+

VCC 3.3V Standby VOLTAGE SWITCH D

G

Q5 Do Not Populate C375

1

1

C173 +

1200UF

1200UF

G

2

2

D

S

S

D

VCC12

R61

Q6 G

VCC5SBY

+

NDS356AP

4.7K SN74LVC07A has 5V input and output tolerance.

VCC5SBY

Q9

VCC3SBY

SI4410DY

R87 PLANE_CTL1

10K

14,32

2

PCTL_IN

VCC

1

2

PLANE_CTL0

7

R83

3 B

V_GQ6

0K

7

28,32

3

PWROK

Q7

U5

VCC

14

C

14

1 2

GND

GND

5

3

6

2

7

1

8

C MMBT3904LT1

U4 74LS132 1

SLP_S3#

4

SN74LVC07A

VTT 1.5V VOLTAGE REGULATOR VCC3_3

C

VTT1_5

VR5

E

Q8

LT1587-1_5

SI4410DY 4

5

3

3

VOUT

2

ADJ

1

VIN

6

C225

2

2

100UF-TANT

C270

+

C43 1.0UF

+

100UF-TANT

8

1

7

1

1

2

B

B

VCC 3.3VSB Regulator

VCC 1.8 VOLTAGE REGULATOR

VCC5SBY

V3SB

VCC 2.5 VOLTAGE REGULATOR VCC1_8

VCC3_3

VCC5

VCC2_5

VR2

VR3

LT1587ADJ

LT1587ADJ VOUT

IN

OUT

3

2

301

VOUT 3

VR1_ADJ

100UF-TANT

100UF-TANT

1%

130

ADJ

1

VR5_ADJ

C65

2

1.0UF

240

R57

C74

1%

0.1UF

Place C159 at the Regulator

240

2

R54

R56 1%

+

C57

2

VIN

+

C59 2

2

2

Place C76 at the Regulator

1

+

+

C76

+

1

C159

1

1

1

1

1 22UF-TANT

1%

VIN ADJ

GND

C71

R55

100UF-TANT

3

2

22UF-TANT

VR4 LT1117-3_3

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

VOLTAGE REGULATORS DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44

1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

29

OF

40

8

7

6

5

4

3

Processor Voltage Regulator

VCC3_3

2

1

VCC5

VCC12 VCC5 R33

R18

220

5.6K

R22

L8

1.0UH-6.8A

D

VRM_PWRGD

5.1

D 32

C21 5VIN

1.0UF 1

1200UF

2

1200UF

C7 +

1

C29 +

+

2

1200UF

C26

1

1

C30

2

10UF

2

2

0.1UF

10K

+

C22

+

C27

1

R17

1200UF

R20

PV12 5

2 PVCC

8

D2

D1

S3

S2

S1

4

3

2

1

6

7

G1

1

D3

2

D4

S1

6

D1

5

8

SENSE

C

0.8UH-20A

3

GND

1.0UF

20

4

SGND

VFB_PD

S2

3

1

VCC

2

G2

11

S3

SS

S1

Q1 SI4410DY

S2

1.0UF

VCCVID

L14

G1

4

D1

Close to FETs C25

L_VCCVID

D2

COMP

D2

1

R19

D3

9

8

3

R_VCCVID

D4

VFB

G1

8

7

10

7

4

G2

FAULT#_PU

20

6

Q3 SI4410DY

Q4 SI4410DY

R16

JP5 C18 150PF

R_VRCOMP

JP4

S3

VID4

12

SS_PD

JP3

G1

IFB

VRCOMP_PD

JP2

D3

G1

VID3

LTC1753

D4

FAULT#

VID2

5

The LTC1753 incorporates internal pull-ups on VID[4:0]. If your VR IC does not incorporate these, they must go on the motherboard.

6

14

5

8

0K

Place CAPs C24

13

PWRGD

VID1

1

15

S1

16

R_VID3

Q2 SI4410DY

17

R_VID2

D1

1

R_VID1

8

7

2

6

2

IMAX

3

3

VID0

4

VID3

OUTEN

S2

VID2

5

18

IMAX

S3

VID1

4

R_VID0

7

G1

C

19

D2

VID0

OUTEN

D3

RP4

D4

VID[3:0]

3

7

0.01UF

VR1

6

2.7K

5

C20

8.2K C17

C19 C35

0.01UF 0.1UF 220PF

B

B

VID Override Jumpers

1 + 2

+ 2

C54 2700UF

1

C128 2700UF

2

+

1

C28 2700UF

1 2

2700UF

+ 2

0.1UF

2700UF

Do Not Stuff C147

C58 +

C31

1

C147

Refer to VR Supplier for Layout Guidelines

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

VRM 8.4 DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

2-22-1999_11:02 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

30

OF

40

8

7

6

5

4

3

2

1

VCC5

VCC3_3

1M

R225

16V

1

PWRBTN#

14

+

C292 2

C279

R226

D

10UF

No stuff. For test only

ICH has internal pullup and debounce on PWRBTN#

100K

R217

VCC3SBY

SYSTEM

D

0.1UF 0K

No stuff. For test only

VCC5

VCC5

16

C370

16

1.0UF

1

R212

IRTX

SW2

VCC3_3

VCC3_3

VCC3_3

2

3

4

2 R_IRTX 3

82

R213

1

J20

IRRX

INFRARED

4

4.7K

5

KEY

6

PBSWITCH

7 PBTN_IN 8

POWER SW.

9

R228

10

R93 10K

470

R231

IDEACTP#

19

11 12

U11

10K

VCC 14

R136 10K

3

13

IDE_ACTIVE

4

KEY

H.D. LED

14 7 GND

VCC

C

IDEACTS#

19

14

SN74LVC07A 1

15

VCC5

FP_PD

U11

2

16

7

R232

SN74LVC07A

18

C POWER LED

KEY

PWRLED 19

220 16

KEY

17 GND

20

KEYLOCK#

KEY

21

KEYLOCK

22 23 24

AC97SPKR SPKR_IN

JP22 VCC3_3

Q11

1

14

ICH_SPKR

SPEAKER

R_SPKRIN

VCC5

26

C

FNT_PNL_CONN

R234

2 3

R235

SPKR

3 SPKR_Q1G B

8

7

6

5

RP62

2.2K

SP1

68

1 2 E

4.7K

KEY

25

R233 68

2N3904

26

C373

C378

1

C258 SPKR_NEG

0.1UF

470PF

+

2

POS NEG

470PF

Speaker Circuit

FAN Headers 1

2

3

4

B

B

VCC3SBY

VCC12

VCC12

VCC3SBY

TACH1

TACH2

16

14

R98

330

VCC

3

U5

VCC 4

1

6

2

GP23LED

GP26LED

GND

GPIO26_FPLED 14

5 7

On-Board LED indicates the Standby Well is on to prevent Hot-Swapping Memory.

GND

SN74LVC07A

SN74LVC07A

CR3

VCC12 1

VCC12

330

GPIO23_FPLED

4.7K

3

14

R172

3

U5 R188 2 V3SBLED

2

14

1

2

7

16

VCC3SBY

0.1UF

J24

0.1UF 1

CR12

J26

330

VCC3SBY C363

R97

VCC3SBY C23

A

A C362 J27

C365 J25

0.1UF

0.1UF

1

1

2

2

3

3

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

SYSTEM, PART 1 DRAWN BY:

16

PWM1

8

PWM2

16

R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:44 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

31

OF

40

8

7

6

5

4

3

2

1

SYSTEM ITP RESET CIRCUIT - FOR DEBUG ONLY

Power Connector and Reset Control

VCC3SBY

VCC3SBY

R99

D

D

240

Power Good Circuit

DBRESET#

4

U10

14

1

3

VCC5SBY

VCC5

APOK_ST

VCC5SBY

VCC_5-

VCC2_5

DBRST

7 SN74LVC08A

VCC12

VCC12-

2

U12

14

1

VCC3_3

U12

2

14

3

ST23

7

74LVC14A

VCC3SBY

4 7

74LVC14A

R10

R90

SN74LVC06A has 5V input tolerance

330

0K VCC5SBY VCC3SBY

11 12

U3

SLP_S3#

14

13 VCC

5

6

14

5VPSON

15

7 GND SN74LVC06A

16

SN74LVC06A is 5V output tolerance

C

VCC

1

PWRGOOD

2

4

7 GND

4.7K

14,32

14

74LVC14A is 5V input tolerant

J4

R62

U3

17 18 19 20

3_3V1

3_3V11

3_3V2

-12V

GND3

GND13 PS_0N

5V4

ATX

GND5

GND15 GND16

5V6

GND17

GND7 PW_OK

-5V 5V19

5VSB

5V20

12V

1

DBRPOK

SN74LVC06A

32

2 3

R91

4

0K

6

VCC3SBY

U4

R92

74LS132 4 DBRPOK_DLY

ATX_PWOK 5

14

VCC 6

PWROK#

5

0K

7

VCC3SBY GND

C

7

R200

C183

8

Do Not Stuff C183

9

4.7K 1.0UF

U3

14

10

VCC

3

4

PWROK

14,28,29

7 GND SN74LVC06A

R199

Do Not Stuff For Debug Only

1M

220 Ohm Pull-up to 3.3V is on VRM Sheet

VRM_PWRGD

30

Reset Button SW1 1

2

B

R24

B

3

4

RST_PD

PBSWITCH

22 C185

Resume Reset Circuitry

10UF

Schmitt Trigger Logic using a 22msec delay

1

0.01UF

Place JP23 Near Front Header (J20)

2

+

C45 JP23

VCC3SBY

VCC3SBY

VCC3SBY

CLOCK POWERDOWN CONTROL

22K

U12 V3RSMRST

14,29,32

6 7

74LVC14A

R86 8.2K

SLP_S3#

U12

14

5

R142

ST69

14

9

8

C264

VCC3SBY

R196

14,28

Do Not Stuff For Debug Only

1M

1.0UF

A

RSMRST#

7

74LVC14A

A 32

DBRPOK

14

4

U10 6

5 7 SN74LVC08A

R84

CK_PWRDN#

CK_PWRD

6

0K Do Not Stuff R84 - For Test Only: If R84 is Populated, R86 Must Be De-Populated

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

SYSTEM, PART 2 DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

12-6-1998_12:54

1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

32

OF

40

7

6

5

4

3

PULL-UP RESISTORS AND UNUSED GATES PCI BUS 18

D

13,17,18,27 13,17,18 13,17,18,27 13,17,18,27 13,17,18,27 13,17,18,27 13,17,18,27

U 4,33

VCC5

PERR#_PU

2

SERR#

3

17

PLOCK#

4

17

STOP#

5

DEVSEL#

6

TRDY#

7

IRDY#

8

FRAME#

9

VCC3SBY

RP47

17 2.7K

1

1

ICH0

VCC5

RP59

2

17

SDONEP1

1

8

SDONEP2

2

7

SBOP1

3

6

SBOP2

4

5

D RP61 14 14

5.6K

14 VCC5

14

SMBALERT#

1

8

LDRQ#1

2

7

GPIO12

3

6

GPIO13

4

5

R73

APICD0

4,13

150 R6

APICD1

4,13

4.7K

150

10

RP60

RP58 9 PULLUP/DOWN RESISTOR PAK

18 18

RP45 PIRQ#D

13,17,18

PIRQ#C

13,17,18 13,17,18 13,17,18,27 13,27 13,18 13,17

C

13,17

VCC5

2

17,18 17,18

3 4

PIRQ#A

5

PREQ#3

6

PREQ#2

7

PREQ#1

8

17

PREQ#0

9

17

2.7K

13,27

2

7

3

6

PTMS

4

5

11,12,14,25,28 14

1

8

2

7

SMBCLK

3

6

INTRUDER#

4

4,13

17

8

PGNT#1

2

7

PGNT#2

3

6

4

NMI

1

8

USLP#

2

7

STPCLK#

3

6

SMI#

4

5

150

1

VCC3_3

17

RP56

PU1_ACK64#

1

8

PU1_REQ64#

2

7

PU2_ACK64#

3

6

PU2_REQ64#

4

5

REQ#B/GPIO1

13 13 13,16,18

1

8

2

7

GNT#B/GPIO17

3

6

SERIRQ

4

5

PU3_ACK64#

18

PU3_REQ64#

18

4,13

INTR

1

8

INIT#

2

7

IGNNE#

3

6

A20M#

4

5

8.2K

C

150

RP52

R208 2.7K

RP49 4,13 4,13,15 4,13

2.7K

13,18 14

R207

13,16

2.7K

13,16

5

PCI_REQ#A

1

8

THERM#

2

7

RCIN#

3

6

A20GATE

4

5

R169

FERR#

4,13

150

8.2K RP53 14,16 14,18

LPC_SMI#

1

8

GPIO7

2

7

3

6

4

5

VCC3SBY

UNUSED GATES

14

9

U10

14,16

8

14,18

10

14

11

4

R68

RTTCTRL

110, 1%

RP54

VCC3SBY U12

For Future Compatibility Upgrade

8.2K

VCC3SBY 14

VCC3_3

4,13 4,13 VCC3_3

8.2K

B

RP50

5

4.7K

RP51

PGNT#0

PGNT#3

SBOP3 PTDI

SMBDATA

11,12,14,25,28

1

RP57

13,18

8

4,13

9 PULLUP/DOWN RESISTOR PAK

13,17

1

VCC5

10

13,17

SDONEP3

5.6K

PIRQ#B

VCMOS

8

1

8

GPIO22

2

7

LPC_PME#

3

6

GPIO21

4

R70

SLEWCTRL

110, 1%

B

5

8.2K

7 SN74LVC08A

10

4

VCC5

7

74LVC14A

U5

14

VCC

9

8

VCC 14

U11

9

GND

SN74LVC07A

14

11

10

11 7

7

U3

13

12

74LS132 9 14

7

7 GND SN74LVC07A

5

AC_SDIN1

14,26

VCC

R166 10K

R170 10K

8

VCC

11

14

10

10 7

7 GND

A

4

AC_SDIN0

14,26

VCC 14

14

12

6

IRQ15

8.2K

U4

U5

3

10

SN74LVC07A

VCC

7

IRQ14

VCC5SBY

GND

SN74LVC07A

13

13,19 13,19

VCC3SBY

VCC

GND

U11

7 SN74LVC08A

74LVC14A

U5

VCC

8

2

13

12 7

SN74LVC07A

14

U11

RP55 1

11

14

13

7

7 GND

U12

U10

14

12 8

GND

SN74LVC06A

A

GND SN74LVC07A

U4 U3

14

74LS132 12

VCC

13

12 7 GND

14

11 13 7

SN74LVC06A

VCC

GND

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

PULLUP/PULLDOWN RESISTORS DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

5-26-1999_17:09

1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

33

OF

40

8

7

6

5

4

3

2

1

370-pin Socket Decoupling VCCVID Decoupling D

Place in 370 PGA Socket Cavity

D

VCCVID Bulk Decoupling 1206 Packages

C125

C152

C136

C117

C110

C115

C153

C146

C126

C139

C155

C140

4.7UF

4.7UF

4.7UF

4.7UF

4.7UF

4.7UF

4.7UF

4.7UF

4.7UF

4.7UF

4.7UF

4.7UF

VCCVID High Frequency Decoupling 0805 Package

C

C C121

1.0UF

C142

1.0UF

C118

C113

1.0UF

1.0UF

C120

1.0UF

C149

1.0UF

C145

C107

1.0UF

1.0UF

C154

1.0UF

C156

1.0UF

C148

C135

1.0UF

1.0UF

C132

1.0UF

C137

1.0UF

C138

C151

1.0UF

1.0UF

C108

C141

1.0UF

1.0UF

C143

1.0UF

C134

1.0UF

VTT Decoupling 0603 Package placed within 200mils of VTT Termination R-packs One Capacitor for every 2 R-Packs

B

B

C384

2

+

1

VTT1_5

22UF

C33

0.1UF

C34

C129

0.1UF

0.1UF

C11

0.1UF

C32

0.1UF

C133

C144

0.1UF

0.1UF

C150

0.1UF

C157

0.1UF

C218

C220

0.1UF

0.1UF

C219

0.1UF

C205

0.1UF

C221

C42

0.1UF

0.1UF

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

VRM DECOUPLING DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

12-8-1998_14:04

1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

34

OF

40

8

7

6

5

4

3

2

1

DRAM, CHIPSET, and BULK POWER DECOUPLING GMCH Decoupling

Display Cache Decoupling

ICH0 Decoupling Distribute near the 1.8V power pins of the ICH0.

D VCC3_3

VCC1_8

ICH0 3.3V Plane Decoupling: Place 1 .1uF/.01uF pair in each corner, and 2 on opposite sides close to component if they fit.

VCC3_3 Distribute near the power pins of both SDRAM components.

VCC1_8

VCC3SBY

1 C215

C381

C163 0.1UF

C286

10UF

10UF

C244

0.1UF

C372

1

C273

+

0.1UF

+

0.1UF

0.1UF

C243 0.1UF

C247 0.1UF

C232 0.1UF

C251 0.1UF

C252 0.1UF

C223 0.1UF

C249

C319

0.1UF

0.1UF

C307 0.1UF

C295 0.1UF

C296 0.1UF

C10 0.1UF

C345

C308

C332

0.1UF

0.01UF

0.01UF

C304 0.01UF

C305

C41

0.01UF

0.01UF

C289

C263

0.01UF

0.1UF

C171

C303 0.1UF

C67

+

C382

0.1UF

1

C239

0.1UF

1

+

C44

C130

0.1UF

0.1UF

2

2

2

2

10UF

D

Distribute near the VCCSUS power pins of the ICH0.

2.2UF

GMCH Core Plane Decoupling: Place 1 .1uF/.01uF pair in each corner, and 2 on opposite sides close to component if they fit.

VCC1_8

C

C C131 0.01UF

C164

C242

0.01UF

C237

0.01UF

C214

0.01UF

C380

C233

0.01UF

0.01UF

C383

0.01UF

0.01UF

Bulk Power Decoupling

System Memory Decoupling

VCC5

VCC3_3

VCC12

VCC_5-

VCC12-

+

C162

C234

C341

C343

C350

C278

C260 0.1UF

C288

C245 0.1UF

C248 0.1UF

C254 0.1UF

C181

22UF

C72

C66

C360

C69

C333

C367

0.1UF

0.1UF

C321

22UF

2

C62

0.1UF

0.1UF

0.1UF

0.1UF

C81 0.1UF

+

1 0.1UF

+

22UF

2

C87

2

0.1UF

22UF 1

22UF

C86

1

2

1

22UF

0.1UF

+

C83

0.1UF

C70 +

C82

2

C85 +

1

DIMM0 Decoupling: Distribute near DIMM0 Power Pins.

GMCH 3.3V IO Decoupling: Place near GMCH Display Cache Quadrant

1

VCC3SBY VCC3_3

C80

C324

C317

0.1UF

0.1UF

0.1UF

C84

C175

0.1UF

0.1UF

2

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

3 VOLT Decoupling B VCC3SBY

DIMM1 Decoupling: Distribute near DIMM1 Power Pins.

Distribute as close as possible to GMCH System Memory Quadrant

+

C188

C169

C262

C352

1

22UF C170

C377

C77

0.01UF

0.01UF

0.1UF

C283

C298

C291

C354

C285

C339

C160

C250

C78

C340

C318

C172

C376

C320

C240

C256

C127

C338

C322

C73 0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

2

0.01UF

C253

0.1UF 0.1UF

0.01UF

B

VCC3_3

VCC3SBY

A

A

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

DRAM, ICH, AND GMCH DECOUPLING DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

5-26-1999_17:09

1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

35

OF

40

8

7

6

5

4

3

2

1

Revision History (Changes from Rev 0.7) She e t De s cription A LL Cosmetic changes to all pages (Re-names nets, re-organized symbol arrangement, etc.) 4

Changed FB1 (f errite bead f or PLL analog isolation) to Inductor L2.

11 12

Changed value of R36 to 10 ohms. D

She e t De s cription 10 Ganged the tw o CKEs of f of one 4.7K Pull-Up to 3.3V . Fixed Symbol Pinout

Replaced R21-R23 w ith 1K R-pack (RP50). Replaced R24-26 and R34 w ith RP44.

Fixed Symbol Pinout Removed SMBUS pullups f rom this page. There are pullups on page 32.

Changed R184 value to 220 ohms

Removed Reset Straps f rom MD lines.

Changed Pull-Up/Dow n Resistor V alues on signals to ITP interf ace and grouped into Rpacks/Discretes to make true populate/de-populate Mf g. Option. Floated THERMTRIP# Signal

13

Updated Ballout Changed C172 to 0.1UF Cap (HUBREF decoupling) A dded Resistor Site to Pull F16 to GND f or test/debug.

Generate GTLREF w ith 1% resistors. Move f rom page 5 to page 4. Changed BR0# Pull-Dow n to 56Ohm to use existing GTL Term Rpack Slot on sheet 5

D

14

A dded Jumper Test Option to GND BSEL line. Change R35 f rom 51Ohm, 1% to 51Ohm, 5%

Updated Ballout Routed PME# and SMI# to GPIO[13:12] respectively to w ake events f rom S1. Pull RTCRST# signal f rom input node of f irst RC delay rather than output node (just other side of diode). Moved Clear CMOS to RTCRST# signal and A dded 1K resistor to GND on pin 3 of jumper.

A dded V CMOS Decoupling C

C

6

Changed V DDA (pin22) of CK-Whitney to 3.3V Supply pet 0.5 Spec.

Change RTC Circuit to pow er V bias straight f rom positive terminal of battery (BA T1). Was charged f rom V CCRTC input. Changed A C_SY NC pull-dow n strap (U Saf e Mode Jumper JP14) to A C_SDOUT pullup strap. Change C8 and C9 to 12pF caps.

A dded/Modif ied Decoupling and Pow er Isolation Ganged U and GMCH Clock Lines Isolated USB/DotCLK pow er (pin 27) f rom SDRA M pow er

Tied OC#0 and OC#1 together.

Changed Pow erDow n control signal to NA ND of SLP_S3# and PWR_OK

A dd jumper straps to SPKR and A C_SY NC

Change C146 and C147 f rom 10pF to 12pF

B

Remove Pull-up f rom SLP_S3# signal

7

Updated GMCH BallOut

8

Changed GTLREF divider to 1% resistors and GTLREF Decoupling to a 0.1uF (C2) and 0.001UF (C72) in parallel Updated GMCH BallOut

15

HUBREF Generated f rom tw o 1% resistors w ith 0.1uF (C171) at GMCH HUBREF pin.

Changed JP4 to a 2 pole instead of 3 pole jumper.

Changed C3 to 20pF Cap

Replace discrete resistors w ith R-packs. Replaced R84-87 w ith RP42.

Decoupled System Memory 3.3V balls f rom Local Memory 3.3V balls. System Memory quadrant connects to 3.3V sb plane and Local Memory connects to 3.3V plane. Updated GMCH BallOut

9

Connected V CCDA CA and V CCDA signals to 1.8V through f iltering circuitry. Connected V SSDA CA and V SSDA to Digital GND. A dded Reset Strap jumpers to LMD[31:26].

A

Updated FWH pinout and labelled symbol as a TSOP Socket. Updated FWH (Socket) Symbol to include FGPI[4:0], routed A TA 66 cable detect to GPI[1:0] and pulled rest dow n through 8.2K. Cominbed Decoupling Caps and reduced to appropriate amount.

16

B

Updated Pinout. Connected new V REF pin to 5V . A dded Decoupling to IRRX/IRTX lines. Routed PME# and SMI# to GPIO[13:12] respectively to w ake events f rom S1. Routed Game Port to game port header, 2nd Serial Port to serial header, PWM/Tach signals to f an headers, and unused signals to test header. Routed Unused GPIOs signals to test header.

Added Oscillator to DotCLK for Test/Debug option

Removed JP6 and Grounded CLOCKI.

Connected Digital V ideo Out signals

Connected V TR to V CC3.3 (removed f rom V CC3SB w ell) and added pow er decoupling. Pulled SY SOPT pin dow n to GND through 4.7K resistor. Moved Keylock pull-up sheet 31.

Changed R70 to 33Ohm and C4 to 20pF.

REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

REVISION HISTORY, PART 1 DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

A

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:43 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

36

OF

40

8

7

6

5

4

3

2

1

Revision History (Changes from Rev 0.7)

D

Sheet Description 17 C hanged device num ers (ID SEL w iring) for s lots to AD 16, AD 17, and AD 22. R outed additional s ignals required to AD 22 s lot to s upport ISA bridge tes t card. 18 C hanged device num ers (ID SEL w iring) for s lots to AD 16, AD 17, and AD 22. R outed additional s ignals through 0K res is tors to AD 22 s lot to s upport ISA bridge tes t card. Added Jum per to route PER R # to IC H /IC H 0 if IC H is populated. 19 C onnected pin 34 of each connector to P66D ETEC T and S66D ETEC T(FWH _GPI0 and FWH _GPI1 res pectively). Buffered PC IR ST# s ignal going to pin 1 of ID E connectors to is olate cable loading. R em oved Series Term inations from IR Q lines (pulled into IC H 0). 20

Sheet 27 C hanged 93C 46 Pinout. 28

29

Is olated each VC C input to U SB s tacked connector through dedicated filtering circuitry. Added 47pF EMI caps on U SB data lines . C onnect U SB through Audio/Modem R is er through 0K res is tors . Make OC detect circuitry unique to each port and update polyfus e value.

22

23 B

25

26

R eplaced D B25 connector w ith 2x13 header s o w e can cable out. SMB R em oved Series Term ination R es is tors from Ack# and Bus y# s ignals .

30

C hanged Pull-ups to 2.2K Added 2nd s erial port and connected both through 2x5 headers to cable out (R em oved 1 D B9 C onnector). Added dis crete s olution to level trans late and route R ing Indicate from Serial ports to IC H for Wake from S3 on s erial m odem . Added MID I/Gam e Port circuitry connected through 2x8 header to cable out. Increas ed C ap values on Keybd/Mous e lines from 100pF to 470pF. C hanged the keyboard and m ous e s ym bols to a PS/2 s tacked connector. C hanged R GB PI filter caps from 22pF to 3.3pF. Added Quick Sw itch to level trans late the C R T Sync, C R T D D C , and Flat D D C Signals .

31

32 32 33

Is olated C K-Whitney from SMBU S in Pow er D ow n through Voltage trans lation Quick Sw itch. C hanged VGA C onnector s ym bol. Added EMI C aps on SYN C and D D C Signals . R outed U SB up the AMR C onnector.

A

R an 5V (ins tead of 5VSB) to Audio Modem R is er. Added s tuffing option AC ’97 debug port

R eplaced R J45 connector and dis crete m agnetics w ith integrated R J45/m agnetics part and connected accordingly.

34 35

Moved Pow er C onnector to Sheet 32 R eplaced old VC C 5dual circuit, w ith VC C 3Sby C ircuit w hich generates s upply for devices w hich m us t s tay pow ered in S3. R em oved LT1585-3.3 (U 36 on rev0.7). C hanged U 27 from LT1585-1.5 to LT1587-1.5 and changed dis cretes . Added V3SB regulator (generated V3SB from V5SB from ATX pow er s upply). C hanged 1.8V R egulator des ign from LT1585AD J to LT1587AD J and change d dis cretes . C hanged 2.5V R egulator des ign from LT1585AD J to LT1587AD J and changed dis cretes . Added VR M Override Jum pers to VID bus . C hange VR D es ign to VR M8.4 com pliant des ign. U s e LTC 1753 per Linear App N ote. Moved R es et and Pow er circuitry to s heet 32 Added Infrared, Pow er Sw itch, H ard D rive/Pow er LED s , Keylock, and Speaker C ircuitry to C om m on Sys tem H eader. Added 12V Fan H eaders (2 s upporting TAC H outputs , and 2 s upport PWM inputs ).

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

5

4

3

FOLSOM, CALIFORNIA 95630 2

A

REV:

1.3

DRAWN BY: R

6

B

C om bined like pullups into R -packs w here pos s ible. Added 8.2K pull-ups to SER IR Q and IC H 0 unus ed GPIOs . Added Pull-U p Sites for FLU SH # and 370PGA Socket Pin W35 to VC MOS for future com patibility upgrade. U pdated Proces s or D ecoupling per lates t Guidelines for 370PGA s ocket. Added Sys tem D ecoupling

REVISION HISTORY, PART 2

7

C

Added D ebug LED to m onitor 3.3VSBY Plane Moved Pull-ups to s heet 33. U pdated new PWR OK/PWR GOOD Generation, R ESET, R SMR ST# circtuitry. Pulled-U p SMBU S interface to 3.3VSby ins tead of 3.3V. R em oved R 164 (FLU SH #) and R 168 (TH ER MTR IP#) pull-ups . R em oved pull-up on PWR GOOD (pulled up on s heet 32). Grouped rem aining pull-ups to 1 1K R pack. C hanged all PC I 3.3V pull-ups to 8.2K per PC I s pec.

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

8

D

Added LAN D is able Jum per. Added IC H /IC H 0 s calability jum pers .

C

21

Description

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:43 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

37

OF

40

8

7

6

5

4

3

2

1

Revision History (Changes from Rev0.9 to Rev0.95) De s c r ip t io n Sh e e t 2 Ch a n g e d "V id e o En c o d e r " b o x o n B lo c k Dia g r a m to " Dig ita l V id e o O u t De v ic e " B o x . 3 4

A d d e d De v ic e Ta b le

22

Ch a n g e R2 0 7 f r o m 4 7 K to 1 0 K

Ch a n g e d Re f e r e n c e De s ig n a to r o n 3 7 0 - p in S o c ke t f r o m J2 0 to X 1

23

Mo v e d RP3 1 f r o m p g . 1 6 to p u ll- u p Ke y /Mo u s e lin e s to f ilte r e d V CC5 .

Ch a n g e d Re f e r e n c e De s ig n a to r o n 3 7 0 - p in S o c ke t f r o m J2 0 to X 1

A d d e d 4 7 0 p F Ca p s o n MIDI lin e s ( C3 2 7 ,C3 2 8 ) .

Ch a n g e d C1 f r o m 2 2 u F,3 0 % to 4 7 u F,1 0 %

D

6

8 9

De s c r ip t io n Sh e e t 20 Ch a n g e d R1 1 7 ,R1 1 8 ,R1 2 1 ,R1 2 2 f r o m 2 7 o h m to 1 5 o h m- 1 % Re s is to r s

25

Cle a n e d Up V G A Co n n e c to r S c h e ma tic

Ch a n g e d S e r ie s Te r min a tio n Re s is to r V a lu e s f r o m 2 2 O h ms to : R3 7 ,R3 8 ,R5 5 ,R5 6 ,R5 7 =4 3 o h m,2 % ; R3 9 ,R4 0 ,R4 1 ,R4 2 ,R4 3 ,R4 6 ,R4 7 ,R5 8 ,R5 9 ,R6 0 ,R6 1 =3 3 o h m,2 % ; R4 5 ,R4 8 ,R4 9 ,R5 0 ,R5 1 ,R5 2 ,R5 3 ,R5 4 ,R6 3 =3 3 o h m,5 % ; R4 4 ,R2 2 6 =1 0 o h m,5 % T’e d REFCL K a n d a d d e d R2 2 6 ( to s e p a r a te te r min a tio n to ICH a n d S IO) . Re n a me d CL K 1 4 to S IO_ CL K 1 4 a n d ICH_ CL K 1 4 f o r e a c h n e w NET o u t o f th e T. Ch a n g e d C1 4 4 a n d C1 8 5 f r o m 4 .7 u F to 2 2 u F.

A d d e d Pr o v is io n s to a d d PI Filte r s o n V S Y NC a n d HSY NC L in e s Ch a n g e d 5 V S u p p ly to Q u ic k S w itc h to p u ll- d o w n o n DIO DE o u tp u t. A ls o p u lle d DDC lin e s u p to th e s a me s u p p ly p o w e r in g th e Qu ic k S w itc h . Ch a n g e R1 3 2 ,R1 3 3 f r o m 8 .2 K to 1 K Pu ll- Up s

A d d e d Ca p S ite to G MCH Hu b Clk A d d e d 0 K Re s is to r ( R2 3 1 ) in s e r ie s w ith DCL K _ W R

26

Re mo v e d A C9 7 De b u g Co n n e c to r ( J5 )

Ch a n g e d Re f e r e n c e De s ig n a to r o n O s c illa to r S o c ke t f r o m U3 4 to X 2

27

Ch a n g e d R4 p u ll- u p f r o m 6 2 K to 4 .7 K a n d a d d e d 0 .1 u F De c o u p lin g to V IO p in ( C2 6 2 ) .

Up d a te d Pin Nu mb e r s to ma tc h G MCH 0 .7 EDS B a llo u t

28

Ch a n g e R1 4 0 /R1 4 1 to 4 .7 K Re s is to r s

A d d e d 0 K Re s is to r ( R2 3 2 ) in s e r ie s w ith L RCL K

29

Mo d if ie d CK _ PW RDW N# G e n e r a tio n Cir c u itr y to p u ll o f f U3 3 NA ND g a te a n d in v e r t th r o u g h U1 3 to g e t c o r r e c t lo g ic le v e l. Pr e v io u s ly it w a s ta p p e d o f f th e b a s e o f B JT Q 6 . Th is w o u ld h a v e ke p t CK _ PW RDW N# f r o m c h a r g in g h ig h e r th a n 0 .7 V ( d r o p a c r o s s B E ju n c tio Ch a n g e d R1 9 1 to 1 0 K , R1 9 2 to 0 K , a n d R1 9 3 to 4 .7 K

Co r r e c te d Co n n e c tio n o f De b u g O s c illa to r f r o m DDCS DA to DOTCL K NET. C

A d d e d De c o u p lin g f o r L A N Po w e r ( C3 3 6 - C3 4 1 )

A d d e d Ca p S ite to ICH Hu b Clk Re p la c e Be a d FB 2 1 w ith In d u c to r ( L 4 ) - 6 8 n H to c r e a te L C f ilte r ( <1 3 0 kHz )

14

30

Ch a n g e d Re f e r e n c e De s ig n a to r o n U8 to V R5 , U1 1 to V R3 , a n d U2 7 to V R4

Ch a n g e d Te s t O s c illa to r Cir c u it ( U3 4 ) to r e mo v e s h o r te d ju mp e r a n d a d d d e c o u p lin g . Ch a n g e d p in n a me s o n 4 8 MHz o s c illa to r s y mb o l. Mo v e d R6 7 ,R6 8 ,R6 9 to S h e e t 2 5 .

Ch a n g e d C2 6 8 a n d C2 5 9 to 1 .0 u F,X 7 R c a p s A d d e d 2 mo r e S i4 4 1 0 DY FETs in p a r a lle l w ith tw o th e r e ( Q 7 /Q 8 )

Re n a me NET CL K 1 4 to ICH_ CL K 1 4

Ch a n g e d C1 6 0 - C1 6 3 to 2 7 0 0 u F a n d a d d e d o n e mo r e ( C3 4 2 ) in p a r a lle l.

Re n a me Pin L 1 to V CCSUS 1 a n d Pin N1 to V CCS US2

Ch a n g e C1 5 3 to 2 2 0 p F

Re n a me NET G PIO 2 3 to G PIO 2 3 _ FPL ED, a n d NET G PIO2 6 to G PIO 2 6 _ FPL ED

Ch a n g e d c o n n e c tio n s o f COMP a n d S S to s h o w th e m r e tu r n in g d ir e c tly to S G ND p in .

Ch a n g e d V a lu e o f C1 1 f r o m 0 .1 u F to 1 .0 u F Ch a n g e d Re f e r e n c e De s ig n a to r o n U9 to X 3

15

A d d e d 0 K RPA CK ( RP6 8 ) in s e r ie s to G ROUND o n FW H ID lin e s f o r Te s t/De b u g .

16

Ch a n g e d Pin 8 7 Na me f r o m RTS 1 # _ S Y S OP to RTS 1 # a n d Pin 5 0 n a me f r o m G P2 7 /IO _ S MI# /TES T to S P2 7 /IO_ S MI# Re n a me NET CL K 1 4 to S IO _ CL K 1 4

16

A d d e d In d u c to r ( L 1 3 ) to f ilte r 5 V in p u t to V RM 31

15

B

Ch a n g e r e f e r e n c e d e s ig n a to r S 1 to S W 1 Ch a n g e C7 9 to 1 .0 u F A d d Fr o n t Pa n e l Du a l L ED Cir c u it c o n tr o lle d b y ICH G PIO s

32

Ch a n g e A TX c o n n e c to r Re f e r e n c e De s ig n a to r f r o m U6 to J2 9 . Ch a n g e r e f e r e n c e d e s ig n a to r S 2 to S W 2

33

Re mo v e d Pu ll- Up s f r o m GPIO 2 3 /GPIO 2 6

16

Mo v e d RP3 1 to p g . 2 3 to p u ll- u p K e y /Mo u s e lin e s to f ilte r e d V CC5 .

Pu lle d L DRQ # 1 Up to 3 .3 V S b y ( in s te a d o f 3 .3 V ) .

17

S w a p p e d A CK 6 4 # a n d REQ6 4 # to r o u te to c o r r e c t p in s p e r PCI s p e c .

Ch a n g e d PCI Pu ll- Up Re s is to r ( R9 9 ,R1 0 0 ,RP5 3 ,RP4 6 ,RP4 7 ) v a lu e s f r o m 8 .2 K to 2 .7 K a n d c o n n e c te d to 5 V . A ls o c o n n e c te d RP4 0 a n d RP4 3 to 5 V ( f r o m 3 .3 V ) to ma in ta in c o mp a tib ility w ith mo r e 5 V PCI c a r d s . Re mo v e d RP4 9 ( V ID Pu ll- Up s ) S in c e in te r n a l to L TC1 7 5 3

18

S w a p p e d A CK 6 4 # a n d REQ6 4 # to r o u te to c o r r e c t p in s p e r PCI s p e c . Re p la c e d JP6 Ju mp e r w ith 0 K Re s is to r S tu f f in g O p tio n ( R2 3 3 , R2 3 4 )

A

19

In s e r te d 0 K S tu f f in g Re s is to r s in S e r ie s w ith A TA 6 6 Ca b le De te c t ( R2 3 5 ,R2 3 6 )

19

S w a p p e d 7 4 L S 0 7 o u t f o r 7 4 L V C0 7 A a n d c o n n e c te d to 3 .3 V .

35

A d d e d a d d itio n a l De c o u p lin g f o r V a r io u s Co mp o n e n ts ( C3 4 3 - C3 8 9 ) A

Ch a n g e d C2 1 7 - C2 2 0 f r o m 0 .1 u F to 0 .0 1 u F A LL

Ch a n g e d Re f e r e n c e De s ig n a to r s o n A ll Fe r r ite B e a d s f r o m FB * to L *. REV:

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

REVISION HISTORY, PART 3 DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

8

7

C

Ch a n g e d Re f e r e n c e De s ig n a to r o n U1 5 a n d U2 5 to Q9 a n d Q 1 0 r e s p e c tiv e ly .

A d d e d L C f ilte r to 1 .8 V p la n e c o n n e c te d to b a lls U6 a n d E1 9 .

Ro u te d L PC_ SMI# a n d L PC_ PME# to G PIO [5 :6 ] r e s p e c tiv e ly f r o m G PIO[1 2 :1 3 ] r e s p e c tiv e ly . B

D

Mo v e d R6 7 ,R6 8 ,R6 9 f r o m S h e e t 9 .

6

5

4

3

FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:43 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

38

OF

40

8

7

6

5

4

3

2

1

Revision History (Changes from Rev0.95 to Rev0.99) S he e t De scrip tio n 4 Changed C1 to 33uF and L2 to 4.7uH.

D

5 6

7 8 C

9

S he e t De scrip tio n Change C330 to a 100pF c ap and S c aled B ac k Dec oupling on power planes 24 to U28.. Connec ted E 21 to V CC_DE T P ull-Up S wapped Connec tivity of F TCLK 0 and F TCLK 1. A dded 0603 Cap S ite on UHCLK 25 F ix ed Connec tivity of CR2, CR4, CR5, CR6 and CR7. In all c as es P ins 1 and 2 were s wapped. Rem oved RP 50 and routed TCK and TM S to 330ohm pull-ups in RP 44. Change L8,L9,L10 P art Num ber to B LM 11B 750S Changed Rpac k c onnec tions per Lay out B ac k A nnotation Changed F 3 from 2.0A F us e to 2.5A F us e. Changed R39-R43,R46,R47,R58-R61 to 33ohm , 5% (from 2% ) 27 Rem oved P ull-up from LA NTCK (U29.D14) and m ade No Connec t. R136 m oved to S heet 16 to P ull-up LP D (U16.27). Routed CK _P W RDN# to Cloc k Chip (S LP _S 3# thru 8.2K res is tor by default). Rem oved C338,C339,C340,C341 and Changed C336,C337 to 4.7uF P olariz ed Capac itors . A dded 0603 Cap S ite on G M CHHCLK Changed INTA # (U29.H2) from P IRQ #D to P IRQ #A and Changed LA N IDS E L (R142.1) from A D19 to A D20. Changed HUB RE F V oltage Divider Res is tor V alues (R182 and R185) from 1K 28 M ade C74 a 470pF -1500V c ap and added "F or E S T Tes ting" Note. 1% to 301ohm -1% and added A C Dec ouping Dis c rete S ites (C394,C395,R245, R246) A dded 22ohm s eries term (R242) to LTCLK Net (U22.K 22). Changed J28.14 c onnec tion from A CTLE D to S P E E DLE D and Changed R219.1 c onnec tion from V CC3S B Y to A CTLE D M oved C323, C324 to page 34 and m ade C324 0.01uF . A dded P rovis ion for Is olating 82559 either on S US _S TA T# or P W RO K Rem oved L5 and C325. Change C5 to 33uF . Connec t U22.U6 and U22.E 19 29 Changed Referenc e Des ignator U14 to Q 10 and U16 to Q 11. direc t to V CC1_8 P lane. Change U22.A B 21 and U22.A B 23 to c onnec t to V CC1_8. Rem oved S eries Term s on Digital V ideo O ut P ort Renam ed NE T CK _P W RD to IN_U5, and Deleted c onnec tion to U13 pin 9 A dded 0K (R31) in s eries with Debug O s c illator Rem oved CK _P W RDW N# NE T, R240 Routed DC_M D27 (c ore detec t S trap) to 10K to 220 pull-up on V CCDE T net.

14 B

16 19

20

A

22

Changed C148 from 2.2uF M onolithic to 2.2uF P olariz ed Changed Referenc e Des ignator on B A T1 to X4 (it is a s oc k et footprint ). P ulled Up S US S TA T to 3.3V through 4.7K (R136, whic h was rem oved from LA N page) res is tor and dis c onnec ted from ICH0. Changes to P 66DE TE CT and S 66DE TE CT NE Ts to s upport both Drive and Hos t S ided 80 c onduc tor c able detec tion: A dded C392 and C393 (0.047uF , X7R, 16V , 10% ) to G ND, 0ohm Res is tors in S eries (R235,R236), and 15K P ulldowns (R243,R244) to G ND. F ix ed Connec t ivity of Res is tor R124. US B V 5 Net now Connec t s direc tly to L26 term inal 1, and R124 dis c onnec ted from L26 t erm inal 1. E lim inated unwanted res is tor divider on 5V power pins at US B port. A dded S eries Res is tors (0K ) to dec ouple ICH US B s ignals from s tac k ed c onnec tor if rout ed up A M R c onnec tor. Changed Net Nam e G _ICHRI# to ICHRI#_C

30

31 32

Connec ted Q 4.{5-8}/Q 7.{5-8}, C193, R150 to Net 5V IN ins tead of direc t to V CC5. A dded 0K Rpac k (RP 69) in S eries to V ID[3:0] pins of V R3. Changed S wit c h S y m bol to 4-pin devic e to m atc h phy s ic al devic e. Changed RefDes U6 to J29.

B

A dded provis ion for s ending early powerok to Cloc k P D# pin for c lean P owerup 33

S wapped S IP Rpac k s on U and ICH pull-ups to 4-E lem ent Rpac k s per Lay out B ac k A nnot ation Change RP 48 from 1K Rpac k to 330ohm Rpac k , and R202, and R203 from 1K res is tors to 330ohm res is t ors for future upgrade c om patibility . A dded A ddit ional Dec oupling on V CC12- and V CC12 1.3

REVISION HISTORY, PART 4 DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

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FOLSOM, CALIFORNIA 95630 2

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TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

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Changed S wit c h S y m bol to 4-pin devic e to m atc h phy s ic al devic e.

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INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

11-23-1998_13:43 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

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Revision History:Changes from Rev0.99 and On Changes from Rev0.99 to Rev1.0 D

D

- Back Annotated from Layout (Reference Designator Changes/Rpack Routing Swaps) - Changed Series Term Values on U and APIC Clocks to 33ohm (Sheet 6) - Changed Series Term Values on Memory, Hub, and DOT Clocks to 22ohm (Sheet 6) - Added 10K Pull-Ups on SLP_S3# and SLP_S5# (Sheet 14) - Added 2 1200uF Caps on VCC3_3SBY Plane (Sheet 29)

Changes from Rev1.0 to Rev1.1

C

- Removed X1, R77, R78, R79 (Debug Oscillator Socket) from Sheet 9 - Connected C377 to VCC3_3SBY Plane - Corrected Pinout of 2x5 Com Port Headers (Sheet 22) - Added 2x1 Header (JP23) to sheet 32 for Chasses Reset Button

C

Changes from Rev1.1 to Rev1.2 - Added RP70 and RP71 to Sheet 8 (SM_MA Series ) - Removed 330Ohm Pull-Ups from FLUSH# and TestHi (W35 on 370-Pin Socket) - Added 110Ohm, 1% Pull-Downs to pins S35 and E27 of 370-pin Socket (RTTCTRL and SLEWCTRL) - Changed C347 from a 2200pF Cap to a 0.047uF Cap

Changes from Rev1.2 to Rev1.3 B

- Changed VCCDET Net name to VCOREDET - Changed Value of R125 to 174ohm, 1% (from 178ohm, 1%) - Changed value of C347 back to 2200pF Cap (from 0.047uF Cap) - Designated R126 as No Stuff per SiI 154 Specification - Removed R123 pull-up and connected SiI154 pin 13 to reset. - Changed RP50, RP49, and R169 from 330ohm to 150ohm

B

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TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

1.3

REVISION HISTORY, PART 5 DRAWN BY: R

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

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FOLSOM, CALIFORNIA 95630 2

INTEL CORPORATION PLATFORM COMPONENTS DIVISION LAST REVISED:

5-26-1999_17:09 1

PROJECT: INTEL(R) 810 CHIPSET SHEET:

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