Lt Spice n2re

(Focus Test Pattern)

LTspice/SwitcherCAD III Mike Engelhardt Linear Technology Corporation

Copyright © 2004, 2005 Linear Technology Corporation

Historical Timeline 1969

CANCER (Computer Analysis of Nonlinear Circuits Excluding Radiation)

1972

SPICE 1 (Simulation Program with Integrated Circuit Emphasis)

1975

SPICE 2 (L. Nagel’s Ph.D. thesis is the guide)

1981

Linear Technology Corp. founded

1983

SPICE 2G6

1985

SPICE 3

1991 1993 1996

1999 2004

DOS SwitcherCAD(equation based) SPICE 3F4 µPower SwitcherCAD(simulation based)

LTspice/SwitcherCAD III(SPICE based) 500,000 base LTspice s(excluding updates & redistrib.) Copyright © 2004, 2005 Linear Technology Corporation

LT1533 Case Study • Voltage and current slew rate limiting • Complex control logic • External timing capacitor • Timing-cap current look-up table • Demo board available • Difficult to get efficiency analytically


Demo Board Schematic


Demo Board


The Bench


Minimum Slew Limits Vin = 5V Vout = +/-5V Iout = 28mA


With Voltage Slew Limit Vin = 5V Vout = ±5V Iout = 28mA


LT1533 Efficiency Comparison

SwCAD III

Demo Board

Min. Slew Rate Limit

73.0%

73.0%

With Current Slew Limit

66.0%

65.4%

With Voltage Slew Limit

63.0%

62.0%


Drafting Your Own Circuits • General purpose schematic capture - Unlimited schematic size - Unlimited depth of hierarchy - Graphical symbol editor

- Complete documentation • Integrated with Industry superlative SPICE simulator - Unlimited, professional-quality SPICE proven for IC design - Unmatched combination of robustness, accuracy, speed and compatibility - Advanced analysis/simulation options, parameter sweeps, FFT’s, etc. - Run 3rd party models - Active independent s’ group • Macromodels of over 950 Linear Technology products


Waveform Display Features • Plot expressions of data assisted with cross probing -

Cross probe voltages, device and port currents Differential crossprobing Dissipation expression composed by the schematic Dimensional analysis

• Waveform average and RMS calculator • Fourier analysis (both .four statements and FFT's) • Parametric plotting (X-Y plotting) • Multiple plot planes - Attached cursors ganged across plot panes • Eye diagrams • Complex data: Bode, Nyquist, and Cartesian • Dynamic waveform data compression Copyright © 2004, 2005 Linear Technology Corporation

LTspice Core Simulator

• Rewrite Berkeley SPICE 3F4/5 for machines with faster U’s than RAM - Reduced address calculation and function calling overhead - Improved timestep control and numerical methods - Enhanced integration methods and convergence improvements - Alternate solver/SPARSE matrix package 1000x more accurate. - Circuit size limited by computer memory • Added/Enhanced semiconductor models - Diode recombination current - JFET impact ionization current - BJT quasi-saturation - VBIC - Binned BSIM3v3.2.4 - BSIM4.4.0 - VDMOS(a new vertical double diffused MOSFET for power MOS) - EKV 2.6 - BSIMSOI3.2 • Advanced Analog Behavioral Modeling Technology - Traditional ABM, specialized behavioral devices, HDL, co-simulation • Leadership in the SPICE community - Subcircuit port current monitoring - Unlimited output file size, i.e., >> 2GB Copyright © 2004, 2005 Linear Technology Corporation

Benchmarking SPICE Transistor-level performance LTspice PSPICE¹ hspice² ab_ac ab_integ ab_opamp arom astabl b330 bias bjtff bjtinv counter cram e1480 g1310 gm1 gm17 gm19 gm2 gm3 gm6 hussamp jge latch

4.750* 0.109* 5.454* 3.656 1.046* 2.172 3.234* 2.453* 7.594* 7.234* 0.625* 0.250 3.969* 5.562* 2.703* 12.625 1.125* 3.453* 5.109* 0.781* 33.875 0.969*

1] PSPICE is a Cadence Trademark

7.59 .23 6.44 6.94 4.52 3.16 5.19 4.17 13.03 15.16 .91 (fails) 10.91 12.39 4.47 (fails) 4.91 8.66 13.45 (fails) (fails) 2.30

14.63 0.17 7.72 3.34* 5.21 1.90* 8.63 2.94 14.28 7.40 0.74 0.09* 5.45 11.14 2.92 9.37* 3.21 8.13 11.84 1.42 9.08* 2.42

2] hspice is a Synopsis Trademark


Benchmarking SPICE(Cont.) LTspice PSPICE hspice loc mike2 mosrect mux8 nagle nand opampal optrans pump rca reg0 rich3 ring ring11 schmitecl schmitfast schmitslow slowlatch todd3 toronto vreg

WINS:

46.687 8.86* 5.797* 37.83 9.734* 17.22 6.531* 12.00 0.672* 1.28 2.250 1.08* 5.109 1.41* 7.500 6.17 0.016* .23 1.719 1.53 4.406* 37.22 35.610 (fails) 5.562* 10.33 2.360* 3.11 0.015* .16 8.297* 21.16 10.781* 23.84 0.156 .22 0.156 .22 5.031* 11.74 0.735* 2.16

30

3

10.64 21.39 29.14 11.91 1.53 2.45 4.50 3.14* 0.49 1.45* 28.78 4.67* 19.36 4.72 0.06 29.09 37.28 0.11* 0.06* 11.72 2.86

10


LTspice Behavioral Simulator • PSPICE style behavioral modeling - Legacy POLY() statements

- Arbitrary expressions - Laplace - Look-up tables. • Arbitrary capacitance: write an expression for the charge. • Arbitrary inductor: write an expression for the flux. • An original mixed-mode simulator -- not xspice based.


Mixed-Mode Simulator • Computationally lightweight • Tight between analog and digital circuitry - Implemented as a mix of intrinsic SPICE devices and ~30 optimizing HDL compilers. - Predictors aid timestep control.

• Easy to program so that models for new products are usually quick to be generated.


Example Mixed-Mode Simulation


LTspice's Special Enhancements for SMPS Simulation • Automatic Steady State Detection and Efficiency Computation • Node Reduction • VDMOS MOSFET Model • Mixed-Mode Simulator with intrinsic SMPS controller functions • Nonlinear magnetics with gapped magnetic circuit solver


SPICE Solver Overview Circuit to Simulate I

D

1mA

SPICE Solver Initial Solution Guess

Newton-Raphson Iteration

V[0] = 0V

V[n]

V[n+1] D

I

D

I

D

I

Linearize 1mA

[G][V]=[I] 1mA

G[n]

I[n]

Solve Matrix for Voltages

1mA

Linearize About New Voltage Solution G[n]

G[n+1]

I[n]


I[n+1]

G[n]

I[n]

Circuit Matrix Nodal analysis: [G][V] = [I] G: Conductivity matrix V: Unknown voltage vector I: Known current vector Modified Nodal analysis: [ G “1”] [v] = [I] [“1” R ] [i] = [V] G: Conductivity matrix v: Unknown voltage vector i: Unknown current vector V: Known voltage vector I: Known current vector

• Node count is more important than part count. • It’s best to avoid floating voltage sources Copyright © 2004, 2005 Linear Technology Corporation

Capacitor Companion Model


Inductor Companion Model


VDMOS MOSFET Normal Monolithic MOSFET (Used in IC’s)

VDMOS (Discrete Power MOSFET) Source

Source

Gate

Gate

Drain

Bulk(Substrate)

Drain Drain-Source Current Path


LTC Proprietary VDMOS Model Replace a problematic subcircuit with a single new intrinsic SPICE device


VDMOS Gate Charge Behavior


Two-Phase SMPS & PLL Capture

Total elapsed time: 19.809 seconds. Copyright © 2004, 2005 Linear Technology Corporation

Chan et al. Nonlinear Magnetics A computationally lightweight model that uses only three parameters to specify the core’s major hysteresis loop: Hc: Coercive force [Amp-turns/meter] Br: Remnant Flux Density [Tesla] Bs: Saturation Flux Density [Tesla]


Gapped Core Magnetic Solver • Core physical dimensions specified with four parameters: Lm: Lg : A: N:

Magnetic Length(excl. gap)[meter] Length of gap [meter] cross sectional area [meter**2] number of turns


Core Saturation Considerations • • • •

Saturation flux density goes down monotonically with temperature Maximum service temperature plus self-heating Controller peak current production scatter Startup/transient/short circuit conditions

If you use the worst inductor that works in simulation, you will have failures over service temperature and production scatter. Copyright © 2004, 2005 Linear Technology Corporation

Simulating Transformers

Mutual coupling K-statement placed as a SPICE directive on the schematic


Multiple Windings =

For N windings, the number of mutual couplings is


Misc. Advanced Features • Waveform plot annotations • Hierarchy • BUS’s • Fast Access file format. • .measure statements • Optional double precision data files • Read/Write .wav files • URL's in a .lib and .inc statements • Color Preference Editor • Programmable Keyboard Shortcuts


Misc. Advanced Techniques • -defined parameters & functions • .step’ing a -defined parameter - Overlay simulation runs - Parameter sweeps - Monte Carlo - Optimization • Open loop response from closed loop system • Using the Universal Opamp Model • Adding 3rd party models


Common Pitfalls • Mirror & Rotate buttons greyed out • Copy block from one schematic to another

• Hidden filename extensions • Start-up overshoot • Dissipation: RMS or Average?

• Finding steady state


Adding

rd 3

Party Models

• RCL databases - standard.res - standard.cap - standard.ind - standard.bead • Intrinsic Devices - standard.dio - standard.bjt - standard.mos - standard.jft • Subcircuits - define on schematic - program symbol to automatically include the required library - explicitly .inc the model


Built-in Help System


Updates With Field Sync • Incrementally updates your installation off the web • Automatically merges databases of devices • Free Lifetime Updates


Reporting a Bug • Make sure you’re using the current version with Field sync.

• All bug reports are appreciated and will be resolved.


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