Mod 5 Counter 55y4c

Changes need to do: “count : buffer integer 0 to 15; And: “if clear = 1 or count >= 5) then

Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;

Entity mod5_counter is Port (rst, clk: in bit; count: buffer integer range 0 to 15); End mod5_counter;

Architecture test of mod5_counter is

Begin Process Begin

Wait until clk' event and clk = '1';

If (clr= '1' or count >= 5) then Count <=0;

Else Count <= count + 1; End if;

End process;

End test;

Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;

Entity mod5 is Port (clr, clk: in bit; count: buffer integer range 0 to 4); End mod5;

Architecture test of mod5 is

Begin Process Begin

Wait until clk' event and clk = '1';

If (clr= '1' or count >= 4) then Count <=0;

Else Count <= count + 1;

End if;

End process;

End test;