Positive Clamper 442k4u

Positive Clamper: The positive clamper circuit is shown in fig. 1, which introduces positive dc voltage equal to the peak of input signal. The operation of the circuit is same as of negative clamper.

Fig. 1

Fig. 2

Let the input signal swings form +10 V to -10 V. During first negative half cycle as Vi rises from 0 to -10 V, the diode conducts. Assuming an ideal diode, its voltage, which is also the output must be zero during the time from 0 to t 1. The capacitor charges during this period to 10 V, with the polarity shown. After that Vi starts to drop which means the anode of D is negative relative to cathode, (V D= vi - vC) thus reverse biasing the diode and preventing the capacitor from discharging. Fig. 2. Since the capacitor is holding its charge it behaves as a DC voltage source while the diode appears as an open circuit, therefore the equivalent circuit becomes an input supply in series with +10 V dc voltage and the resultant output voltage is the sum of instantaneous input voltage and dc voltage (+10 V). To clamp the input signal by a voltage other than peak value, a dc source is required. As shown in fig. 3, the dc source is reverse biasing the diode. The input voltage swings from +10 V to -10 V. In the negative half cycle when the voltage exceed 5V then D conduct. During input voltage variation from –5 V to -10 V, the capacitor charges to 5 V with the polarity shown in fig. 3. After that D becomes reverse biased and open circuited. Then complete ac signal is shifted upward by 5 V. The output waveform is shown in fig. 4.

Fig. 3

Fig. 4

Voltage Doubler : A voltage doubler circuit is shown in fig. 5. The circuit produces a dc voltage, which is double the peak input voltage.

Fig. 5

Fig. 6

At the peak of the negative half cycle D1 is forward based, and D2 is reverse based. This charges C1 to the peak voltage Vp with the polarity shown. At the peak of the positive half cycle D 1 is reverse biased and D2 is forward biased. Because the source and C1 are in series, C2 will change toward 2Vp. e.g. Capacitor voltage increases continuously and finally becomes 20V. The voltage waveform is shown in fig. 6. To understand the circuit operation, let the input voltage varies from -10 V to +10 V. The different stages of circuit from 0 to t10 are shown in fig. 7(a).

Fig. 7(a) During 0 to t1, the input voltage is negative, D1 is forward biased the capacitor is charged to –10 V with the polarity as shown in fig. 7b.

Fig. 7(b) During t1 to t2, D2 becomes forward biased and conducts and at t2, when Vi is 10V total voltage change is 20V. If C1 = C2 = C, both the capacitor voltages charge to +10 V i.e. C1 voltage becomes 0 and C2 charges to +10V.

Fig. 7(c) From t2 to t3 there is no conduction as both D1 and D2 are reverse biased. During t3 to t4 D1 is forward biased and conducts. C1 again charges to +10V

Fig. 7(d) During t4 to t5 both D1 and D2 are reverse biased and do not conduct. During t5 to t6 D2 is forward biased and conducts. The capacitor C2 voltage becomes +15 V and C1 voltage becomes +5 V.

Fig. 7(e) Again during t6 to t7 there is no conduction and during t7 to t8, D1 conducts. The capacitor C1 recharges to 10 V.

Fig. 7(f) During t8 to t9 both D1 and D2 are reverse biased and there is no conduction. During t9 to t10 D2 conducts and capacitor C2 voltage becomes + 17.5 V and C1 voltage becomes 7.5V. This process continues till the capacitor C1 voltage becomes +20V.

Fig. 7(g)