Spyglass Cdc 4gg33

Datasheet

SpyGlass CDC Comprehensive, Low-Noise Clock Domain Crossing Verification

Overview Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens or sometimes even hundreds of asynchronous clock domains, making it very difficult to using conventional simulation or static timing analysis (STA). RTL simulation is not designed to metastability effects which cause data transfer issues across asynchronous clock boundaries and STA does not address asynchronous clock domains issues.

Introduction CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle, and may even find their way into silicon, necessitating costly respins. Besides the traditional CDC issues, Reset Clock Domain (RDC) issues can also cause metastability in signals. Use of asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up/boot sequences, etc. As a consequence, RDC issues are causing more and more design errors. (Please refer to the SpyGlass RDC Datasheet for more information about these reset domain crossing capabilities.) For both of these types of issues, SpyGlass® provides a high-powered, comprehensive solution. SpyGlass RTL Signoff Lint Clock & reset verification Power estimation & reduction Power intent verification Timing constraint verification Design for test

Figure 1: SpyGlass RTL Signoff Solution

Features & Benefits `` Protocol Independent Analysis, recognition of widest variety of synchronizers and auto detection of quasi-static signals resulting in the lowest number of false violations `` Architecture for scalable CDC and RDC verification `` Simple setup by automatically extracting the clock, reset and clock domains information; It can also extract the same information from existing SDC constraints providing a jump start to the s `` Comprehensive structural and functional analysis using formal based and simulation based solutions to deliver signoff quality `` Highest performance and CDC/RDC centric debug capabilities

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Figure 2: Typical CDC bugs

`` Hierarchical SoC flow to IP based design methodologies to deliver quickest turnaround time for very large size SoCs

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`` Low learning curve and ease of adoption

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`` Integrated with other SpyGlass solutions for RTL signoff for lint, constraints, DFT and power

`` CDC-centric debug capabilities

Market Leader

Methodology

CDC Bugs The success of static CDC verification tools is determined by two critical measures—the time taken to sign off the RTL and the completeness of CDC verification. Conventional CDC analysis tools fall short in both areas. They generate large amounts of noise (false violations), extending the verification cycle, and provide poor coverage on various types of CDC issues. Figure 2 describes the class of bugs/scenarios, which, if not verified correctly, can cause design respins. These bugs can be structural as well as functional in nature.

SpyGlass CDC Verification Synopsys’ SpyGlass CDC architecture is based on six pillars of scalable CDC verification (see Figure 3).

SpyGlass CDC

Figure 3: Scalable CDC verification

Ease of Use and Functionality `` Simple setup assisted by automatically extracting the clock, reset and clock domains information. The tool can also extract the same information from existing SDC constraints, providing a jump-start to the s `` Comprehensive structural and functional CDC analysis using formal-based and simulation-based solutions to deliver signoff-quality CDC verification `` Protocol-independent analysis, recognition of the widest variety of synchronizers and auto detection of quasi-static signals resulting in the lowest number of false violations

`` Hierarchical SoC flow to IPbased design methodologies to deliver quickest turnaround time for very large SoCs `` Integrated with the SpyGlass solution which targets other RTL analysis, like Lint, DFT, constraints and power

Solving Problems At the RTL & Netlist Level SpyGlass CDC provides an easy-to-use and comprehensive guide for solving CDC problems at the RTL and gate-level netlist to avoid costly respins. `` Methodology documentation and rulesets delivered as part of the product `` -guided CDC methodology results in fewer, more meaningful violations, saving time for the RTL designer `` Walks s through a series of recommended steps to analyze CDC problems at block-level as well as chiplevel; the steps include design setup, setup checks, design-unit integration, chip-level CDC verification, report review and CDC verification signoff

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Separating True from False Violations To isolate real clock domain crossing issues, it is necessary to detect various synchronization schemes, not just basic two-flop or multi-flop synchronizers, and perform comprehensive protocolindependent analysis. As part of the protocol-independent analysis, SpyGlass CDC correlates control and data signals resulting in a good understanding of the design intent. It also detects the list of potential quasi-static signals. s review the auto generated list of quasi-static signals and use them as part of the setup. This helps to produce CDC analysis with the lowest possible noise.

SpyGlass CDC has integrated structural and functional CDC analysis. s make use of formal based functional CDC analysis to CDC protocols. s also have the flexibility to generate SystemVerilog Assertions (SVA) to CDC protocols and assumptions made for structural analysis. SpyGlass CDC also provides a signoffquality hierarchical SoC flow to perform CDC analysis for very large SoCs. This helps s to use a divide-andconquer approach to achieve the highest productivity and quickest turnaround time. The SpyGlass Predictive Analyzer® technology significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex SoCs fueling today’s consumer electronics revolution.

Synopsys, Inc. • 690 East Middlefield Road • Mountain View, CA 94043 • www.synopsys.com ©2015 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is available at http://www.synopsys.com/copyright.html . All other names mentioned herein are trademarks or ed trademarks of their respective owners. 10/15.RP.CS6534.