What Are The Advantages And Disadvantages Of The Finfet Technology 3g2d5m

What are the advantages and disadvantages of the FinFET technology? Answer

Daniel Fishman, Senior FA engineer and Technical Leader at Intel Answered Mar 16

Currently this the best architecture and manufacturing technology for U/GPU. The switch to FinFET was due to multiple reasons - but the major one is channel control. Below 32/28 nm DIBL and othe device parameters are such that you can no longer control your transistor. So if you wish to continue to scale down - FinFETs, Nanowires or any other form of 3D channel is a must. The cost is another issue. FinFETs are costlier than planar devices - but it can range from few percent up to 45%. 3D stacking is working quite well in NVM but for logic it is much complex and have not been commercialized yet. Bottom line - for logic (U/GPU/FPGA) FinFET is the only way to go below 28 nm node. In memory (flash particularly) the manufactures can stay on planar devices and make 3D stacking. FinFET transistors - are the latest mass produced, Si based transistors - used in every major ULSI products. 

FinFETs were invented in order to overcome various performance issues on Planar transistors. See the charts below:

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FinFETs have significantly better performance - Vt, Speed and leakage - due to a major geometrical change in the channel design. See the illustration below:

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FinFETs are harder to manufacture and have more complex challenges (design, reliability etc.) vs. the previous planar devices. FinFETs are the current manufacturing platform for all major semiconductor companies. It is expected that future devices will be based on FinFET platform.

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Venkata Kusumitha, Analog by Birth, Digital by Design Updated Jul 18

How we can say a particular technology is well suited in manufacturing of IC’s in VLSI…!?! Power…. Performance… Area..!!! (PPA) These 3 strategies determine the extent a particular is beneficial or not. Let's look how FINFET technology brings out the best out of it..!! Taking advantage of process scaling With reduced dimensions and improved transistor performance.. We can build smaller/faster cells and memories.  Balancing reduced gate leakage with increased dynamic power  Managing the dynamic power of finFETs  Optimizing logic library design  Efficient layout to reduce area and total power  Usage of combinational and sequential cells  Memory compiler design Venkata Kusumitha 

It offers a number of advantages over the planar MOSFET. From the device designer's perspective: 1) Higher transconductance (current out per voltage in) 2) Lower apparent input capacitance for the same gain 3) Less wafer area per transistor to get high gain, as the fin height can be increased in order to get high gain 4) Fully depleted structure, enabling better on/off contrast 5) I-V curves get flatter, meaning lower dynamic power consumption. From the physicist's perspective: 1) Channel quantization, leading to sharper contrast between on/off states 2) Channel quantization, leading to better current density due to confined density of states instead of free density of states 3) Again, channel quantization, reducing short-channel effects by more effectively physically separating the source and drain rather than letting them couple as a PNP or NPN structure beneath the channel And lastly, from the consumer/'s perspective: 1) Faster switching speed. (comes from lower input capacitance and higher dynamic current density) 2) Lower power consumption (comes from lower parasitic capacitance and better on/off characteristics).