Digital System Design Using Verilog December 2011 5v4n47

10EC121

USN

M.Tech. Degree Examination, December 2011 Digital System Design using Verilog Max. Marks:l00

Time: 3 hrs.

Note: Answer any FIVE full questions. 1 a. b.

'2

a.

What does a verilog module define. Explain in brief the three principal design tasks that benefit the use of verilog. (08 Marks) What is meant by design methodology? Explain the basic steps of design methodology, in brief. (12 Marks) Using

AND-OR-INVERTER

(AOI)

logic

implement

the

given Boolean

function

F = (x + y.z).(y.z). Show how the Boolean equation for F can be transformed into SOP form. Use the laws of Boolean algebra for reduction and implement the SOP form the result. (08 Marks)

b.

Write a verilog model to devise a one-hot code to represent the days of the week (Monday through Sunday). (06 Marks) c. Draw the circuit diagrams of parity trees for generating and checking odd parity for an 8-bit code. (06 Marks)

3

a. With a neat figure, explain the equality comparator and inequality comparator. (08 Marks) b. Develop a verilog model of a converter that converts a 4-bit binary code input to a 4-bit gray coded output. (08 Marks) c. What number is represented by the signal fixed-point binary number 111101, assuming the binary point is four places from the right? (04 Marks)

4

a.

Design a control sequence for the control signals ofthe sequential complex multiplier.

b.

What is the main difference between a testbench for a combinational circuit and a testbench for a sequential circuit? Explain with an example. (06 Marks) What is GALS? Explain. (04 Marks)

(10 Marks)

c. 5

a. b. c.

Design a IGx8-bit memory using four 256Mx4-bit memory components. (08 Develop a verilog model of a dual-port 4k x 16-bit flow through SSRAM. One port data to be written and read, while the other port only allows data to be read. (08 Determine whether there is an error in the ECC word 000111000100 and if so correct

Marks)

allows Marks)

it.

(04 Marks)

6

..

.~

'0

7

z ~ .•.. o

c..

.5

8

a. b. c.

What is the benefit of allowing PLD in a system to be reprogrammed? Explain. What distinguishes a platform FPGA from a simple FPGA? Explain in brief. Write a Gurnnut assembly language program to find the greater of two values.

a. b.

Briefly explain the serial interface standards for I/O devices. With a neat diagram, explain the architecture for Sobel accelerator datapath.

a. b.

Briefly describe the purpose of floor planning placement and routing. (10 Marks) With a neat circuit diagram, explain 4-bit LFSRs and 4-bit GFSR and their purposes.

(06 Marks) (04 Marks) (10 Marks) (10 Marks) (10 Marks)

(10 Marks)

*****