Pages From Digital Design - An Embedded Systems Approach Using Verilog 456r44

C.2 Combinational Functions

APPENDIX C

519

by being broken into smaller subexpressions. For a synthesis tool to be able to infer combinational logic from an always block, we must follow a number of rules. First, the format of the block must be always @(event-list) statement;

The event list is a list of all of the inputs to the combinational block. This ensures that whenever any of the inputs changes value, the block determines new values for the outputs. If any input is read in the block but is not in the event list, the synthesis tool would typically issue a warning message. One simple way to ensure that we don’t inadvertently omit any input from the event list is to use an alternate form, @*, which stands for “all inputs read in the block.” While this is recommended, it was introduced into Veri a relatively recent revision of the language, and may not be uniformly ed by all synthesis tools. The statement in the always block can be a conditional statement, such as a case statement or if statement, containing nested assignments. An example is an always block of the form:

always @* case (select-expression) choice-1: target = expression-1; choice-2: target = expression-2; ... choice-n: target = expression-n; endcase

A synthesis tool could infer a multiplexer, as shown in Figure C.2, provided the choice values were distinct and included all possible values of

expression-1

…

expression-2

expression-n select-expression

1 2 … n

F I G U R E C . 2 Hardware inferred for a selected assignment.

520

APPENDIX C

verilog for synthesis

the select expression. The select inputs of the multiplexer are connected to the output of the combinational logic inferred from the select expression. Each of the assignment expressions would be synthesized to combinational logic connected to the particular data input of the multiplexer identified by the corresponding choice value. The choice values are expressions, but they must not involve any inputs. Usually, they are just literal values. The effect of inclusion of an if statement is illustrated by an always block of the form:

always @* if (condition-1) target = expression-1; else if (condition-1) target = expression-1; ... else target = expression-n;

Each of the expressions and conditions implies combinational logic. The outputs of the expression logic are connected to decision logic driven by the condition logic, such as that shown in Figure C.3. Since the conditions are tested one by one until a true condition is found, the decision logic is priority based, with conditions appearing earlier in the conditional assignment having priority over those appearing later. As a consequence, the propagation delay for the inferred logic may be as long as the sum of propagation delays of the inferred decision component. Of course, a condition-1 expression-1

1 0

condition-2 expression-2

1 0

…

F I G U R E C . 3 Hardware inferred for a conditional assignment.

condition-n–1 expression-n–1

1 0

expression-n